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Advantages APEX PLLs Over Virtex DLLs
Altera Corporation Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com https://websupport.altera.com
Altera enhanced phase-locked loop (PLL) circuitry APEXdevices increase device board-level performance. PLLs minimize clock skew clock delay support clock synthesis applications. support multiple-clock Altera added four PLLs APEX 20KE devices. Clock delay clock skew affect system timing printed circuit board (PCB) reliability. address these issues, designers either PLLs found APEX devices delay-locked loops (DLLs) found Xilinx Virtex devices. Although both used reduce amount skew delay system clocks, PLLs more flexible than DLLs frequency synthesis applications. This technical brief describes performance advantages PLLs over DLLs. PLLs APEX devices help meet clock management requirements integrating multiple system-level functions onto single device. APEX architecture features four PLLs device contains ClockLockTM, ClockBoostTM, ClockShiftcircuitry increased performance flexible clock frequency multiplication division. Table describes functions each circuitry type.
Table APEX Circuitry Features
Circuitry
ClockLock ClockBoost ClockShift
Description
Reduces internal delay clock skew between other devices PCB. Provides programmable clock frequency multiplication division, allows time domain multiplexing. Provides programmable phase shift precise clock delay management.
Fundamentals
circuits monitor reference signal, such system clock, manage synthesize other clocks. PLL, phase comparator measures difference between phase frequency external reference signal internal feedback signal. Based this difference, phase comparator adjusts voltage-controlled oscillator (VCO), which produces timing signal clock that back phase detector. This signal compared with incoming reference signal. When reference signal feedback signal identical, "locked" onto reference signal. continues monitor reference signal adjust output compensate temperature voltage fluctuations. Figure shows block diagram APEX PLL.
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Advantages APEX PLLs Over Virtex DLLs
Figure APEX Circuitry
Phase Comparator
Voltage-Controlled Oscillator FOUT1
Input Clock
Locked Clock Outputs ClockShift Circuitry FOUT2
Fundamentals
circuits also monitor reference signal clock management. operation fundamentally same PLL, except that delay line used instead generate output timing signal. delay line inserts given amount delay between input clock feedback clock, that rising edges align. Figure shows block diagram Virtex DLL.
Figure Virtex Circuitry
Note
CLKIN
Variable Delay Line
CLKOUT
Clock Distribution Network
Control CLKFB
Note:
Source: Xilinx XAPP 132: Using Virtex Delay-Locked Loop.
Advantages APEX PLLs Over Virtex DLLs
APEX 20KE PLLs provide several advantages over Virtex-E DLLs, including:
APEX 20KE PLLs provide full multiplication division capabilities. ClockShift circuitry provides fine control clock phase clock delay. APEX 20KE PLLs support low-voltage differential signaling (LVDS) standard with data transfer rates Megabits second (Mbps). APEX 20KE PLLs support very input clock frequencies MHz). APEX 20KE PLLs support T1/E1 rate conversions. APEX 20KE PLLs filter high-frequency jitter.
Table compares features APEX Virtex DLL.
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Advantages APEX PLLs Over Virtex DLLs
Table APEX Virtex Comparison
Feature
Circuitry Number PLLs (DLLs) Clock multiplication Clock division Coarse clock adjustment Fine clock adjustment Input frequency range Output frequency range 622-Mbps output LVDS support T1/E1 rate conversion Notes:
Source: Virtex data sheet. Xilinx claims Virtex supports clock multiplication cascading DLLs together. 270° usable higher frequencies. maximum output frequency LVDS. General purpose maximum output frequency MHz.
APEX 20KE
Analog number number 90°, 180°, 270° resolution 360°)
Virtex-E
Digital 1.5, 2.5, only 90°, 180°, 270° None
ClockBoost Circuitry Programmable Clock Synthesis
system clock different frequency than some components. CPU, example, require internal clock that several times faster than system clock. APEX 20KE analog PLLs provide scaling that supports frequency multiplication division number 106. This advanced feature provides designers with true programmable clock synthesis, greatly enhancing design flexibility performance. Virtex-E digital DLLs provide only multiplication only allow division 1.5, 2.5, shown Table This limited frequency synthesis support does address needs highperformance designs.
ClockShift Circuitry Precise Phase Time Delay Management
APEX 20KE ClockShift circuitry provides programmable phase shift precise time delay management. fine clock adjustment uses incremental step delays allowing output clock lead input clock 360°. coarse clock adjustment allows clock phase adjusted 90°, 180°, 270°. programmable delay also lets designers implement strict timing margins that cannot without clock adjustment. This feature enables designers improve times meet high-speed interface requirements. Virtex-E DLLs limited clock phase adjustments 90°, 180°, 270° only support fine clock adjustments required designs with strict timing requirements.
LVDS Support
LVDS high-speed interface standard that supports data rates speeds Mbps. Standard LVDS implementation currently used discreet chips requires clock multiplicaiton. APEX 20KE devices have special deskew circuitry, dedicated parallel-to-serial circuitry, PLLs that provide higher clock multiplication support LVDS Mbps. Xilinx claims that DLLs have maximum output clock rate MHz. Because their digital circuitry, DLLs support clock multiplicaiton, making LVDS support Mbps highly unlikely.
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Advantages APEX PLLs Over Virtex DLLs
T1/E1 Conversion Rates
general purpose PLLs APEX 20KE devices include special circuitry support T1/E1 conversion. telecommunications standard (used United States) uses 1.544 clock rate while telecommunications standard (used Europe) uses 2.048 clock rate. PLLs support special mode that allows clock rate conversion vice versa. Virtex-E DLLs support this conversion.
PLLs Filter High-Frequency Jitter
analog circuitry APEX 20KE translates time-continuous transfer function. This transfer function acts filter input clock, attenuating highfrequency jitter. discrete delay line architecture digital capable filtering jitter input clock. DLLs, input jitter accumulates output. Xilinx output jitter specification (cycle cycle) input jitter. input jitter passed through outupt. example, input clock jitter going into DLL, output clock will have jitter
Conclusion
APEX PLLs, supported advanced ClockLock, ClockBoost, ClockShift circuitry, provide significant improvements system performance design versatility minimizing clock skew clock delay. flexible clock synthesis robust clock shift capabilities APEX PLLs provide precise phase delay adjustment. Designers increase system performance minimizing tCO. PLLs allow support high-performance standards such LVDS provide flexibility capability unattainable Virtex-E DLLs. With these advantages, APEX PLLs dramatically increase system performance.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 1999 Altera Corporation. Altera, Quartus, APEX, APEX 20K, APEX 20KE, ClockLock, ClockBoost, ClockShift, System-On-aProgrammble-Chip trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. Virtex trademark Xilinx, Inc. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
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