Synopsys East Middlefield Road Mountain View, 94043 (650) 962-5000 htt

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Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software
Synopsys East Middlefield Road Mountain View, 94043 (650) 962-5000 http://www.synopsys.com
Altera® MAX+PLUS® software easily interacts with third-party tools such Synopsys FPGA Express software. With MAX+PLUS software, target Altera programmable logic devices (PLDs) using FPGA Express software your synthesis tool. Altera/Synopsys FPGA Express tool lets quickly synthesize implement designs Altera devices, even perform multiple design iterations single day. This technical brief describes FPGA Express environment target Altera device generate EDIF netlist file, Assignment Configuration File (.acf), Library Mapping File (.lmf) MAX+PLUS software. Figure shows flow diagram Altera/Synopsys FPGA Express interface PCs.
Figure Altera/ Synopsys FPGA Express Interface
.vhd
FPGA Express Software
.acf .edf .lmf
MAX+PLUS Software
.vho .edo
.pof .sof
complete instructions synthesize design using FPGA Express software then import into MAX+PLUS software compilation, should refer MAX+PLUS Altera Commitment Cooperative Engineering Solution (ACCESSSM) Guidelines, which available Altera Technical Support (AtlasSM) section Altera site http://www.altera.com. guidelines also available HTML format \lit\html\maxkey directory MAX+PLUS CD-ROM (version higher).
Using FPGA Express Software
following procedure describes FPGA Express environment target Altera device generate EDIF netlist file. create project, select (File menu). Specify project name Name choose Create. Identify Sources dialog box, select your source files. Choose Open.
Altera Corporation
M-TB-042-01
Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software
source files analyzed errors identified. should correct errors reanalyze source files before continuing FPGA Express environment. also invoke built-in text editor correct errors double-clicking error messages. Choose Options (Synthesis menu). Click Project tab. choose turn Default Export Timing Constraints Option option, turn Insert LCELL Buffers, Style WYSIWYG option (for FLEX devices only), select state machine style from Default-FSM Encoding option. Choose Figure
Figure Options Dialog
Turning Default Export Timing Constraints Option option tells FPGA Express software export timing constraints MAX+PLUS ACF. Insert LCELL Buffers, Style WYSIWYG option instructs FPGA Express software architecture-specific logic resources directs synthesis style WYSIWYG. Default Encoding option selects state machine encoding methodology. Select top-level module entity from your project choose Create Implementation (Synthesis menu). Verify that name top-level module entity appears Implementation Name box. Then select desired Vendor, Device, Family, Speed Grade target your selected Altera device. Choose Figure
Figure Create Implementation Dialog
Altera Corporation
Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software
Click Design Implementation icon select Optimize Chip (Synthesis menu) logic resources. also edit constraints optimizing design. Figure
Figure Optimize Chip Dialog
Click Design-Optimized icon choose Export Netlist (Synthesis menu). Specify destination folder save EDIF Input File (.edf). Choose Save. destination folder should contain EDIF file, ACF, LMF.
import EDIF netlist file into MAX+PLUS software compilation. MAX+PLUS Compiler, select Custom EDIF Netlist Reader Settings dialog (Interfaces menu). Then, make sure LMF#1 points generated FPGA Express software. Refer MAX+PLUS Help complete details.
More Information
Altera provides extensive support documentation help successfully interface MAX+PLUS software with third-party design entry tools. technical support, contact Altera Applications (800) 800-EPLD. also e-mail your technical questions Altera sos@altera.com. answers common questions regarding Altera/Synopsys interface, search Atlas Solutions Altera site. following documents also provide more detailed information:
MAX+PLUS ACCESS Guidelines MAX+PLUS Programmable Logic Development System Software Data Sheet Software Support
documents available contacting Literature Services (888) 3-ALTERA; also download them from Altera site http://www.altera.com.
Altera Corporation
Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 1998 Altera Corporation. Altera, ACCESS, Atlas, MAX, MAX+PLUS, MAX+PLUS trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Synopsys East Middlefield Road Mountain View, 94043 (650) 962-5000 htt

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