2813.3 Numerically Controlled Oscillator/Modulator Intersil

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2813.3 Numerically Controlled Oscillator/Modulator Intersil

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HSP45116/883
2813.3
Numerically Controlled Oscillator/Modulator
Intersil HSP45116/883 combines high performance quadrature numerically controlled oscillator (NCO) high speed 16-bit Complex Multiplier/Accumulator (CMAC) single This combination functions allows complex vector multiplied internally generated (cos, sin) vector quadrature modulation demodulation. shown Block Diagram, HSP45116/883 divided into three main sections. Phase/Frequency Control Section (PFCS) Sine/Cosine Section together form complex NCO. CMAC multiplies output Sine/Cosine Section with external complex vector. inputs Phase/Frequency Control Section consist microprocessor interface individual control lines. phase resolution PFCS bits, which results frequency resolution better than 0.006Hz 25.6MHz. output PFCS argument sine cosine. spurious free dynamic range complex sinusoid greater than 90dBc. output vector from Sine/Cosine Section inputs Complex Multiplier/Accumulator. CMAC multiplies this (cos, sin) vector external complex vector accumulate result. resulting complex vectors available through 20-bit output ports which maintain 90dB spectral purity. This result accumulated internally implement accumulate dump filter. quadrature down converter implemented loading center frequency into Phase/Frequency Control Section. signal downconverted Vector Input CMAC, which multiplies data rotating vector from Sine/Cosine Section. resulting complex output down converted signal.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. CMAC Chip 15MHz 25.6MHz Versions 32-Bit Frequency Control 16-Bit Phase Modulation 16-Bit CMAC 0.006Hz Tuning Resolution 25.6MHz Spurious Frequency Components -90dBc Fully Static CMOS
Applications
Frequency Synthesis Modulation PSK, FSK, Demodulation, Phase Shifter Polar Cartesian Conversions
Ordering Information
PART NUMBER HSP45116GM-15/883 HS45116GM-25/883 TEMP. RANGE (oC) PACKAGE PKG. G145.A G145.A
Block Diagram
VECTOR INPUT SINE/ COSINE ARGUMENT
MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS
PHASE/ FREQUENCY CONTROL SECTION
SINE/ COSINE SECTION CMAC
VECTOR OUTPUT
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HSP45116/883
Absolute Maximum Ratings
Supply Voltage +8.0V Input Output Voltage Applied .GND -0.5V +0.5V Rating Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) Package 30.0 Maximum Package Power Dissipation 125oC Package 2.16W Maximum Junction Temperature 175oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC Number Transistors Gates .103,000 Transistors
Operating Conditions
Temperature Range -55oC 125oC Supply Range +4.5V +5.5V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested PARAMETER Logical Input Voltage Logical Zero Input Voltage Logical Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage SYMBOL VIHC VILC ICCSB ICCOP TEST CONDITIONS 5.5V 4.5V 5.5V 4.5V -400µA 4.5V (Note +2.0mA 4.5V (Note 5.5V VOUT 5.5V GND, 5.5V, (Note 15MHz, 5.5V (Notes (Note GROUP SUBGROUPS TEMPERATURE (oC) UNITS
Output Voltage
Input Leakage Current
Output Leakage Current Standby Power Supply Current Operating Power Supply Current
Functional Test NOTES:
Interchanging force sense conditions permitted. Operating Supply Current proportional frequency, typical rating 10mA/MHz. Tested follows: 1MHz, (clock inputs) 3.4V, (all other inputs) 2.6V, 0.4V, 1.5V, 1.5V. Output test load circuit with switch open 40pF.
HSP45116/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested (15MHz) PARAMETER Period High High Setup Time; ADO-1, Going High Hold Time; AD0, AD1, from Going High Setup Time CO-15 from Going High Hold Time CO-15 from Going High Setup Time High Setup Time MODO-1 Going High Hold Time MODO-1 from Going High Setup Time PACI Going High Hold Time PACI from Going High Setup Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from Going High Hold Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from Going High Setup Time RINO-18, IMINO-18 Going High Hold Time RINO-18, IMINO-18, Going High Output Delay R0O-19, I0O-19 SYMBOL tAWS NOTES GROUP SUBGROUPS TEMPERATURE (oC) (25.6MHz) UNITS
tAWH
tCWS
tCWA
tMCS
(Note
tMCH
tPCS
tPCH
tECS
tECH
HSP45116/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed 100% Tested (15MHz) PARAMETER Output Delay DETO-1 Output Delay PACO Output Delay TICO Output Enable Time OER, OEI, OEREXT, OEIEXT OUTMUXO-1 Output Delay NOTES: testing performed follows: 4.5V 5.5V. Input levels (CLK Input) 4.0V input levels (all other inputs) 3.0V timing reference levels (CLK) 2.0V; others 1.5V. Output load test load circuit with switch closed 40pF. Output transition measured 1.5V 1.5V. Applicable only when outputs being monitored ENCFREG, ENPHREG, ENTIREG active. Transition measured ±200mV from steady state voltage, output loading test load circuit, with switch closed 40pF. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS TEMPERATURE (oC) UNITS SYMBOL tDEO (Note NOTES GROUP SUBGROUPS TEMPERATURE (oC) (25.6MHz) UNITS
PARAMETER Input Capacitance
SYMBOL
TEST CONDITIONS Open, 1MHz measurements referenced device
NOTES
Output Capacitance Output Disable Time Output Rise Time Output Fall Time NOTES:
COUT From 0.8V 2.0V From 2.0V 0.8V
parameters Table controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Loading specified test load circuit with 40pF. TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Tess Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples SUBGROUPS
HSP45116/883 Burn-In Circuit
VIEW
IMIN4
IMIN8
IMIN9
IO18
IO15
IO12
IO10
IMIN11 IMIN15 IMIN16
IMIN
IMIN5
IMIN7
IMIN10 IMIN13 IMIN14
IO19
IO16
IO14
IO11
RIN15
RIN18
IMIN2
IMIN3
IMIN6
IMIN12 IMIN17 IMIN18
IO17
IO13
RO18
RIN13
RIN17
IMIN0
INDEX
RO19
RO17
RIN10
RIN14
RIN16
RO16
RO15
RIN7
RIN11
RIN12
RO14
RO13
RO11
RIN9
RIN8
RO12
RO10
RIN6
RIN5
RIN3
RIN1
RIN4
RIN2
RIN0
ENPH
RBYTILD
PACO
DET1
PEAK
MOD1 ENCF MODPI /2PI OUTMUX1
OEREXT
ENOF BINFMT MOD0
LOAD
OUTMUX0
OEIEXT
DET0
TICO
PACI
PMSEL CLROFR ENTIREG
ENPHAC
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
HSP45116/883 Burn-in Circuit
NOTE: ±20%) resistor connected pins except GND. 5.5V ±0.5V with 0.1µF (min) capacitor between position. 100kHz ±10%, F0/2, F1/2 F10/2, duty cycle. Input Voltage limits: 0.8V max, 4.5V ±10%. NAME IMIN(0) RIN(18) RIN(17) RIN(16) RIN(15) RIN(14) RIN(13) RIN(12) RIN(11) RIN(10) RIN(9) RIN(8) RIN(7) RIN(6) RIN(5) RIN(4) RIN(3) RIN(2) RIN(1) RIN(0) SH(1) SH(0) ENPHREG ENOFREG PEAK RBYTILD BINFMT TICO MOD(1) MOD(0) PACI LOAD PMSEL CLROFR ENCFREG BURN-INSIGNAL NAME ENPHAC ENTIREG MODPI/2PI AD(1) AD(0) C(15) C(14) C(13) C(12) C(11) C(10) C(9) C(8) C(7) C(6) C(5) C(4) C(3) C(2) C(1) C(0) OUTMUX(1) OUTMUX(0) OEREXT OEIEXT PACO DET0 DET1 RO(0) RO(1) BURN-IN SIGNAL NAME RO(2) RO(3) RO(4) RO(5) RO(6) RO(7) RO(8) RO(9) RO(10) RO(11) RO(12) RO(13) RO(14) RO(15) RO(16) RO(17) RO(18) RO(19) IO(0) IO(1) IO(2) IO(3) IO(4) IO(5) IO(6) IO(7) IO(8) IO(9) IO(10) IO(11) IO(12) IO(13) IO(14) IO(15) IO(16) IO(17) BURN-IN SIGNAL NAME IO(18) IO(19) IMIN(18) IMIN(17) IMIN(16) IMIN(15) IMIN(14) IMIN(13) IMIN(12 IMIN(11) IMIN(10) IMIN(9) IMIN(8) IMIN(7) IMIN(6) IMIN(5) IMIN(4) IMIN(3) IMIN(2) IMIN(1) BURN-IN SIGNAL None None None None None None None None
Characteristics
DIMENSIONS: mils mils 1mils METALLIZATION: Type: Si-Al, Si-Al-Cu Thickness: GLASSIVATION: Type: Nitrox Thickness: WORST CASE DENSITY: 105A/cm2

2813.3 Numerically Controlled Oscillator/Modulator Intersil

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