Overview Compiled Memory Naming Convention. Characteristics Timing Pow
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Compiled Memory
Overview Compiled Memory Naming Convention. Characteristics Timing Power. Built-In Self Test Built-In Redundancy-Analysis Compiled Memory Selection Guide.
High-Density Compiled Memory
SPSRAM_HDL SPSRAMR_HDL DPSRAM_HDL SPARAM_HDL DROM_HDL MROM_HDL ARFRAM_HDL FIFO_HDL CAM_HDL High-Density Single-Port Synchronous SRAM High-Density Single-Port Synchronous SRAM with Redundancy. 5-39 High-Density Dual-Port Synchronous SRAM 5-49 High-Density Single-Port Asynchronous SRAM. 5-71 High-Density Synchronous Diffusion Programmable ROM. 5-102 High-Density Synchronous Metal-2 Programmable ROM. 5-114 High-Density Multi-Port Asynchronous Register File. 5-126 High-Density Synchronous First-In First-Out Memory 5-146 High-Density Synchronous Content Addressable Memory. 5-158 SPSRAMBW_HDL High-Density Single-Port Synchronous SRAM with Bit-Write 5-24
DPSRAMBW_HDL High-Density Dual-Port Synchronous SRAM with Bit-Write. 5-60 SPARAMBW_HDL High-Density Single-Port Asynchronous SRAM with Bit-Write 5-86
Low-Power Compiled Memory
SPSRAM_LPL SPSRAMBW_LPL DPSRAM_LPL SPARAM_LPL SPARAMBW_LPL Low-Power Single-Port Synchronous SRAM 5-171 Power Single-Port Synchronous SRAM with Bit-Write 5-181 Low-Power Dual-Port Synchronous SRAM. 5-192 Low-Power Single-Port Asynchronous SRAM 5-215 Low-Power Single-Port Asynchronous SRAM with Bit-Write 5-226
DPSRAMBW_LPL Low-Power Dual-Port Synchronous SRAM with Bit-Write. 5-203
COMPILED MEMORY
Overview
OVERVIEW
This section overview STDL130 compiled memory. STDL130 compiled memories provide application-specific memory solution high-density low-power application. That different compiled memory libraries available STDL130: STDL130-HD(High-Density) STDL130-LP(Low-Power). high-density compiled memories suitable high integration application. low-power compiled memories suitable portable applications. Each these memory types customized satisfy specific circuit requirements. Each memory uses state-of-the-art design architecture techniques. final memory block implemented stand-alone, pitch-matched customized leafcells. compiled memory fully generated user-configurable compiler, called memory compiler. user defines memory related specifications such word depth, word, column type. compiler then produces following items: Complete functional model simulation Tabular model timing power characteristics Automatic generated datasheet including information specific memory configuration Full schematic netlist layout verification Phantom cell chip-level floor planning layout
Additional information about memory compilers obtained from your local Samsung Technology Design Centers.
COMPILED MEMORY NAMING CONVENTION
this chapter, describe naming convention memory. memory name, Figure consists following convention.
`memory_name':=
Figure 5-1.
Compiled Memory Naming Convention
first string, `memory_code', means name memory type. STDL130 compiled memory, available memory types follows: SPSRAM SPSRAMBW SPSRAMR DPSRAM DPSRAMBW SPARAM SPARAMBW DROM MROM ARFRAM FIFO Single-Port Synchronous SRAM Single-Port Synchronous SRAM with Bit-Write Single-Port Synchronous SRAM with Redundancy Dual-Port Synchronous SRAM Dual-Port Synchronous SRAM with Bit-Write Single-Port Asynchronous SRAM Single-Port Asynchronous SRAM with Bit-Write Synchronous Diffusion-Programmable Synchronous Metal2-Programmable Multi-Port Asynchronous Register File Synchronous First-In First-Out Memory Synchronous Content Addressable Memory
Samsung ASIC
STDL130
Characteristics Timing Power
COMPILED MEMORY
second string, 'appl_code', means specific application suitably support compiled memory application code HD(High-Density) LP(Low-Power). third string, 'procs_code', represents process process code Generic process Low-Power process(L). case Generic process, don't have specify 'procs_code'. there process code, means that memory developed under Generic process. process code means that memory under Low-power process. fourth string, 'opt_code', represents number read write ports multi-port memory option code composed following convention:
`opt_code' <n>r<m>w
Currently this field only used ARFRAM, where total number read ports (1~2) total number write ports (1~2). last string, 'config_code', represents configuration memory specified. This configuration code composed following convention:
`config_code' <WORD> <BPW> <YMUX> <BANK>
Where, WORD word depth, word, YMUX available column type BANK number bank used. example, 'spsram_hdl_1024x32m16b2' refers High-Density single-port synchronous SRAM with 1024 words, bits, column bank under Generic process. Second, 'arfram_hdl_1r2w_32x32m2' refers High-Density three-port read/2 write) asynchronous register file with word, bits column under Generic process. 'spsram_lpl_1024x32m16' refers Low-Power single-port synchronous SRAM with 1024 words, bits column under Low-power process.
CHARACTERISTICS TIMING POWER
STDL130 compiled memories fully optimized 1.8V 0.15V supply voltage. Compiled memory this section been characterized using typical-process degree 1.8V supply. worst-case best-case parameters found using derating factor calculated from following equation: tWC(tBC) KP_local KV_local KT_local tNOM Where, worst-case propagation delay best-case propagation delay tNOM typical-case propagation delay characterized under typical-process, degree 1.8V supply KP_local local process derating factor corresponding each memory type. KV_local local voltage derating factor corresponding each memory type. KT_local local temperature derating factor that varies memory type.
Note that KP_local, KV_local KT_local only used compiled memories.
STDL130
Samsung ASIC
COMPILED MEMORY
Characteristics Timing Power
two-dimensional timing characteristics table look-up model been adopted yield more accuracy. Based combination input slopes output loads, propagation delay measured from input crossing output crossing VDD. timing values reported tables also taken from same voltage level switching characteristics with 0.2ns input slope 10SL (Standard Load) output load. power consumption read write modes measured input slope 0.2ns, output load 10SL input switching activity factor 0.5. total power consumption calculated following equation: Ptotal ((SAread Pread) (SAwrite Pwrite)) fMAX Where, Ptotal total power consumption microwatts Pread read power consumption microwatts Pwrite write power consumption microwatts SAread read access ratio every cycle SAwrite write access ratio every cycle fMAX clock frequency MHz.
value SAread SAwrite between However, SAread SAwrite must less than equal power values reported tables also taken from switching activity, SA=0.5. compiled memory, read power consumption, write power consumption standby power consumption available. standby power consumption measured condition that (Chip Select Negative) disabled other signals their normal operating mode except that (Output Enable Negative) held low. signals active during standby mode, standby power near zero only static leakage power consumed. dual-port memories, power consumption measured with only port active other port isolated.
Samsung ASIC
STDL130
Built-In Self Test Built-in redundancy-analysis
COMPILED MEMORY
BUILT-IN SELF TEST BUILT-IN REDUNDANCY-ANALYSIS
Samsung provides engineering design services support Built-In Self-Test (BIST) Built-In Redundancy Analysis (BIRA) compiled memories. BIST recommended test solution compiled memories. Samsung BIST circuits designed detect complete range fault types such stuck-at faults, transition faults, coupling faults, address macrocells same different types exist together circuit, Samsung supports BIST memories single architecture. BIRA design services also provided test redundancy RAMs with testers. BIRA tests SRAM generates fail information after redundancy analysis. fail information gathered logic tester automatically processed transferred laser repair machine. multiple redundancy RAMs, Samsung BIRA architecture integration module supp parallel testing, minimum test usage, optimize logic tester interface. more detailed information regarding BIST BIRA, please contact your local Samsung Technology Design Centers.
STDL130
Samsung ASIC
COMPILED MEMORY
Selection Guide Compiled Memory
SELECTION GUIDE COMPILED MEMORY
High-Density Compiled Memory High-Density SPSRAM_HDL Description High-Density Single-Port Synchronous Static Duty-free clock operation Zero hold time address, data-in other control pins Dual bank available Flexible aspect ratio (Ymux High-Density Single-Port Synchronous Static Bit-write feature available Duty-free clock operation Zero hold time address, data-in other control pins Dual bank available Flexible aspect ratio(Ymux High-Density Single-Port Synchronous Static with Redundancy Bit-write feature available Duty-free clock operation Zero hold time address, data-in other control pins Row-only redundancy available Failure analysis BIRA laser repair Flexible aspect ratio(Ymux High-Density Dual-Port Synchronous Static Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux High-Density Dual-Port Synchronous Static Bit-write feature available Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux High-Density Single-Port Asynchronous Static Synchronous write operation Asynchronous read operation Dual bank available Flexible aspect ratio(Ymux High-Density Single-Port Asynchronous Static Bit-write feature available Synchronous write operation Asynchronous read operation Dual bank available Flexible aspect ratio(Ymux
SPSRAMBW_HDL
SPSRAMR_HDL
DPSRAM_HDL
DPSRAMBW_HDL
SPARAM_HDL
SPARAMBW_HDL
Samsung ASIC
STDL130
Selection Guide Compiled Memory
COMPILED MEMORY
High-Density DROM_HDL
Description High-Density Synchronous Diffusion programmable Diffusion programmable coded Duty-free clock operation Zero hold time address other control pins Dual bank available Flexible aspect ratio(Ymux High-Density Synchronous Metal-2 programmable Metal-2 programmable coded Duty-free clock operation Zero hold time address other control pins Dual bank available Flexible aspect ratio(Ymux High-Density Multi-Port Asynchronous Register File Synchronous write operation Asynchronous read operation 1-to-2 write ports 1-to-2 read ports Flexible aspect ratio(Ymux High-Density Synchronous First-In First-Out Memory Duty-free clock operation Reset Re-transmit operation available Flexible aspect ratio(Ymux High-Density Synchronous Binary Content Addressable Memory Duty-free clock operation Single cycle compare operation Built-in priority address encoder available Global hit/miss handling
MROM_HDL
ARFRAM_HDL
FIFO_HDL
CAM_HDL
STDL130
Samsung ASIC
COMPILED MEMORY
Selection Guide Compiled Memory
Low-Power Compiled Memory Low-Power SPSRAM_LPL Description Low-Power Single-Port Synchronous Static Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux Low-Power Single-Port Synchronous Static Bit-write feature available Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux Low-Power Dual-Port Synchronous Static Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux Low-Power Dual-Port Synchronous Static Bit-write feature available Duty-free clock operation Zero hold time address, data-in other control pins Flexible aspect ratio(Ymux Low-Power Single-Port Asynchronous Static Synchronous write operation Asynchronous read operation Flexible aspect ratio(Ymux Low-Power Single-Port Asynchronous Static Bit-write feature available Synchronous write operation/ Asynchronous read operation Flexible aspect ratio(Ymux
SPSRAMBW_LPL
DPSRAM_LPL
DPSRAMBW_LPL
SPARAM_LPL
SPARAMBW_LPL
Samsung ASIC
STDL130
NOTE
STDL130
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Logic Symbol
spsram_hdl_<w>x<b>m<y>b<ba> [m-1:0] [b-1:0] NOTES: Words(w) number words. Bpw(b) number bits word. Ymux(y) column types. Banks(ba) number banks. log2w DOUT [b-1:0]
Features
Suitable high-density application Separated data Synchronous operation Duty-free clock cycle Asynchronous tri-state output Latched inputs outputs Automatic power-down Zero standby current Zero hold time noise output optimization Flexible aspect ratio Dual-bank scheme available 512Kbits capacity number words number bits word
Function Description
SPSRAM_HDL single-port synchronous static which provided compiler. SPSRAM_HDL intended high-density applications. rising edge write cycle initiated when low. data DI[] written into memory location specified A[]. During write cycle, DOUT[] remains stable. rising edge read cycle initiated when high low. data DOUT[] become valid after delay. While standby mode that high, data stored memory retained DOUT[] remains stable. When high, DOUT[] placed high-impedance state.
SPSRAM_HDL Function Table
Valid Valid Valid DOUT DOUT(t-1) DOUT(t-1) MEM(A) COMMENT Unconditional tri-state output De-selected (standby mode) Write cycle Read cycle
Parameter Description
SPSRAM_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number bits word(b), Column mux(y) Number banks(ba).
Samsung ASIC
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static
Parameters Words Step Step Step
Ymux(y) 2048 4096
Ymux(y) 4096 8192
Ymux(y) 8192 16384
Ymux(y) 16384 32768
Descriptions
Name Type Clock Description Clock input. CSN, WEN, DI[] latched into rising edge rising edge write mode. high rising edge read mode. Upon falling edge precharge state.
Chip Enable Chip enable input. chip enable active-low latched into rising edge When low, enabled reading writing, depending state WEN. When high, goes standby mode disabled reading writing. DOUT remains previous data output. Read/Write Enable Read write enable input. read/write enable latched into rising edge When low, data written addressed location DOUT remains stable. When high, data from addressed word presented DOUT. Data output enable input. data output enable asynchronously operated regardless inputs. When high, DOUT disabled goes high-impedance state. Address input bus. address latched into rising edge Data input bus. Data latched rising edge Data input written into addressed location write mode.
Data Output Enable Address Data Input
DOUT Data Output Data output bus. Data output valid after rising edge while read mode. Data output remains previous data output while write mode.
Capacitance
11.53 6.79 4.74 4.74 4.74 4.74
Unit: [SL] DOUT 17.08
NOTE: Each pin's capacitance exactly same regardless available types same bank.
STDL130
5-10
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Block Diagrams
SPSRAM_HDL different physical architectures word depth. Optionally, these architectures generated from SPSRAM_HDL compiler. dual-bank, bank selected address only activated while other bank idle mode. 1-bank architecture, power ports located middle-edge bottom edge both right- left-sides memory. 2-bank architecture, power ports located middle-edge bottom-edge both right- left-sides memory. signal ports only located bottom sides memory regardless architecture.
<1-bank architecture>
Word-line Decoder
Word-line Decoder
X-Dec
Core
Core
Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp.
Driver
Address Clock Buffers A[m-1:0]
Driver
DOUT[b/2-1:0]
DI[b/2-1:0]
DI[b-1:b/2]
DOUT[b-1:b/2]
Samsung ASIC
5-11
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static
<2-bank architecture
Word-line Decoder Word-line Decoder X-Dec
Core
Core
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block Word-line Decoder Word-line Decoder
X-Dec
Core
Core
Driver
Address Clock Buffers A[m-1:0]
Driver
DI[b-1:b/2]
DOUT[b-1:b/2]
DOUT[b/2-1:0]
DI[b/2-1:0]
Application Notes
Permitting over-the-cell routing. chip-level layout, over-the-cell routing SPSRAM_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides SPSRAM_HDL. Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode except that tied low. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
STDL130
5-12
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckh Clock pulse width high tckl Clock pulse width Address setup time Address hold time setup time hold time Data-In setup time Data-In hold time setup time hold time tacc Data access time De-access time DOUT drive high-Z time DOUT high-Z drive time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations. Definition Area (µm) Width physical width X-direction Height physical height Y-direction
Samsung ASIC
5-13
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.76 0.86 0.43 0.94 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.35 1.80 0.23 0.26 0.81 142.92 147.51 43.36 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.76 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.36 1.77 0.23 0.26 0.81 157.33 160.94 50.90 580.84 260.18 2.83 0.86 0.43 0.95 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.43 1.87 0.24 0.28 0.83 201.95 213.72 59.78 687.08 226.08 2.81 0.86 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.41 1.82 0.24 0.28 0.83 218.13 225.75 69.38 815.72 307.34 2.97 0.86 0.43 0.95 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.57 2.00 0.26 0.30 0.86 266.87 295.29 76.54 879.08 320.40 2.90 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.50 1.90 0.26 0.31 0.86 283.21 299.35 88.80 1050.60 401.66 3.10 0.86 0.43 0.96 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.70 2.12 0.27 0.32 0.89 333.79 387.45 92.47 1091.68 414.72 2.98 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.58 1.97 0.26 0.32 0.89 353.99 381.82 107.68 1306.08 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-14
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 1024 3.22 0.86 0.43 0.96 0.01 0.45 0.01 0.47 0.01 0.78 0.01 2.82 2.23 0.28 0.34 0.93 400.77 486.61 109.16 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 1024 3.07 0.86 0.43 0.98 0.01 0.45 0.01 0.47 0.01 0.78 0.01 2.67 2.04 0.27 0.34 0.93 423.79 466.56 128.13 1540.96 590.30 1536 3.50 0.86 0.43 0.98 0.01 0.45 0.01 0.46 0.01 0.78 0.01 3.10 2.50 0.28 0.35 0.96 487.08 627.73 125.99 1475.68 697.68 1536 3.20 0.86 0.43 0.98 0.01 0.45 0.01 0.46 0.01 0.78 0.01 2.80 2.16 0.28 0.35 0.96 500.41 574.55 150.32 1775.84 778.94 2048 3.54 0.86 0.43 0.99 0.01 0.45 0.01 0.46 0.01 0.78 0.01 3.14 2.53 0.29 0.37 0.99 554.10 773.90 142.60 1667.68 886.32 2048 3.34 0.86 0.43 0.98 0.01 0.45 0.01 0.45 0.01 0.78 0.01 2.94 2.28 0.29 0.37 0.99 579.97 692.54 173.15 2010.72 967.58 4096 3.69 0.86 0.43 0.99 0.01 0.45 0.01 0.44 0.01 0.77 0.01 3.28 2.60 0.29 0.37 0.99 637.90 847.50 187.80 2010.72 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.76 0.86 0.43 0.94 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.36 1.80 0.22 0.25 0.79 115.89 121.97 28.42 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.76 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.36 1.78 0.22 0.25 0.79 128.12 135.55 35.49 537.96 260.18 2.84 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.44 1.87 0.23 0.26 0.81 161.52 172.91 37.37 687.08 226.08 2.81 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.41 1.53 0.23 0.27 0.81 174.14 186.19 46.13 751.40 307.34 1024 2.97 0.86 0.43 0.95 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.57 2.01 0.24 0.28 0.83 213.41 234.13 46.68 879.08 320.40 1024 2.90 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.50 1.90 0.24 0.29 0.83 224.08 242.76 57.38 964.84 401.66 1536 3.10 0.86 0.43 0.96 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.70 2.12 0.25 0.29 0.85 267.64 302.94 55.09 1091.68 414.72 1536 2.99 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.59 1.98 0.25 0.29 0.85 280.42 307.23 68.02 1198.88 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-16
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2048 3.22 0.87 0.43 0.97 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.82 2.23 0.26 0.31 0.88 320.61 373.67 64.35 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2048 3.07 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.67 2.04 0.25 0.31 0.88 334.59 370.59 79.89 1412.32 590.30 3072 3.50 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 3.10 2.51 0.26 0.32 0.90 392.94 472.29 73.53 1475.68 697.68 3072 3.20 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.80 2.16 0.26 0.32 0.91 394.03 447.52 92.67 1625.76 778.94 4096 3.54 0.86 0.43 0.99 0.01 0.45 0.01 0.47 0.01 0.78 0.01 3.14 2.53 0.27 0.33 0.92 447.00 566.60 82.77 1667.68 886.32 4096 3.34 0.86 0.43 0.98 0.01 0.45 0.01 0.47 0.01 0.78 0.01 2.94 2.28 0.27 0.33 0.93 455.58 530.31 105.83 1839.20 967.58 8192 3.69 0.86 0.43 0.99 0.01 0.45 0.01 0.46 0.01 0.77 0.01 3.28 2.60 0.27 0.34 0.92 503.90 623.00 113.90 1839.20 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-17
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.78 0.86 0.43 0.94 0.01 0.45 0.01 0.53 0.01 0.78 0.01 2.38 1.80 0.21 0.24 0.78 87.90 90.00 22.05 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.80 0.86 0.43 0.98 0.01 0.45 0.01 0.53 0.01 0.78 0.01 2.40 1.78 0.21 0.24 0.78 100.11 103.74 28.83 516.52 260.18 1024 2.86 0.86 0.43 0.95 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.46 1.87 0.22 0.25 0.80 119.43 123.54 27.82 687.08 226.08 1024 2.86 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.45 1.83 0.22 0.26 0.80 132.00 137.73 36.06 719.24 307.34 2048 3.00 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.59 2.01 0.23 0.27 0.82 157.04 164.68 33.94 879.08 320.40 2048 2.94 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.54 1.90 0.23 0.27 0.82 167.59 176.19 43.73 921.96 401.66 3072 3.12 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.72 2.12 0.24 0.28 0.84 197.52 211.42 39.02 1091.68 414.72 3072 3.03 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.63 1.98 0.24 0.28 0.83 209.08 221.12 50.43 1145.28 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-18
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 4096 3.24 0.86 0.43 0.96 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.84 2.23 0.25 0.29 0.85 236.66 258.62 45.15 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 4096 3.11 0.87 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.71 2.04 0.24 0.29 0.85 248.58 264.40 58.64 1348.00 590.30 6144 3.53 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 3.12 2.51 0.25 0.30 0.87 294.99 325.95 51.23 1475.68 697.68 6144 3.25 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.84 2.16 0.25 0.30 0.87 292.89 316.89 67.22 1550.72 778.94 8192 3.56 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.78 0.01 3.16 2.53 0.26 0.31 0.89 334.10 384.20 54.47 1667.68 886.32 8192 3.38 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 2.98 2.28 0.26 0.32 0.89 339.11 373.19 75.94 1753.44 967.58 16384 3.73 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.77 0.01 3.32 2.60 0.26 0.32 0.89 382.90 434.40 80.95 1753.44 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-19
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 1024 2.82 0.86 0.43 0.94 0.01 0.45 0.01 0.53 0.01 0.78 0.01 2.42 1.80 0.21 0.24 0.78 73.89 73.64 18.35 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 1024 2.88 0.86 0.43 0.98 0.01 0.45 0.01 0.53 0.01 0.77 0.01 2.47 1.78 0.21 0.24 0.78 85.99 87.51 24.98 505.80 260.18 2048 2.90 0.86 0.43 0.95 0.01 0.45 0.01 0.52 0.01 0.78 0.01 2.50 1.88 0.22 0.25 0.79 98.33 98.14 22.28 687.08 226.08 2048 2.93 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.77 0.01 2.53 1.83 0.22 0.25 0.79 110.74 112.86 30.23 703.16 307.34 4096 3.04 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.63 2.01 0.23 0.26 0.81 128.92 128.81 26.55 879.08 320.40 4096 3.02 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.61 1.90 0.23 0.27 0.81 139.15 141.89 35.84 900.52 401.66 6144 3.17 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.76 2.12 0.24 0.27 0.83 162.33 163.90 29.50 1091.68 414.72 6144 3.10 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 2.70 1.98 0.23 0.28 0.83 173.07 176.34 39.89 1118.48 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-20
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 8192 3.29 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.89 2.23 0.24 0.28 0.84 194.55 199.19 33.10 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 8192 3.18 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 2.78 2.04 0.24 0.29 0.84 205.42 209.62 46.14 1315.84 590.30 12288 3.57 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 3.17 2.50 0.25 0.29 0.86 246.16 251.06 38.26 1475.68 697.68 12288 3.32 0.87 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 2.92 2.16 0.25 0.29 0.86 242.31 249.72 52.54 1513.20 778.94 16384 3.60 0.86 0.43 0.99 0.01 0.45 0.01 0.49 0.01 0.78 0.01 3.20 2.53 0.25 0.30 0.87 278.50 291.20 42.62 1667.68 886.32 16384 3.45 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 3.05 2.28 0.25 0.30 0.87 280.88 292.51 58.96 1710.56 967.58 32768 3.80 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.77 0.01 3.40 2.60 0.25 0.30 0.87 321.80 337.50 62.26 1710.56 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-21
STDL130
SPSRAM_HDL
High-Density Single-Port Synchronous Static Timing Diagrams
Read Cycle
tcyc tacc DOUT[] Valid M[A0] M[A1] M[A2] tckh
(CSN low, low, don't care)
Write Cycle
tcyc DI[] (CSN= low, don't care) tckh
STDL130
5-22
Samsung ASIC
SPSRAM_HDL
High-Density Single-Port Synchronous Static
Read Cycle with Controlled
tcyc tacc DOUT[] M[A0] M[A1] tckh
(OEN low, high, don't care)
Controlled Output Enable
DOUT[] Hi-Z VALID Hi-Z
(CK, WEN, don't care)
NOTE: "don't care" means condition that these pins normal operation mode.
Samsung ASIC
5-23
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Logic Symbol
spsrambw_hdl_<w>x<b>m<y>b<ba> BWEN [b-1:0] [m-1:0] [b-1:0] DOUT [b-1:0]
Features
Suitable high-density application Bit-write capability Separated data Synchronous operation Duty-free clock cycle Asynchronous tristate output Latched inputs outputs Automatic power-down Zero standby current Zero hold time noise output optimization Flexible aspect ratio Dual-bank scheme available 512Kbits capacity number words to128 number word
NOTES: Words(w) number words. Bpw(b) number bits word. Ymux(y) column types. Banks(ba) number banks. log2w
Function Description
SPSRAMBW_HDL single-port synchronous static with bit-write capability which provided compiler. SPSRAMBW_HDL intended high-density applications. Basically, functionality exactly same SPSRAM_HDL except bit-write operation which controlled BWEN[], named bit-write enable signal bus. Each BWEN[] enables disables write operation corresponding DI[]. rising edge write cycle initiated when low. data bits DI[], which their corresponding bit(s) BWEN[] low, written into memory location specified A[]. When bits BWEN[] high, data DI[] written into memory location specified A[]. When bits BWEN[] low, data DI[] written into memory location specified A[], which exactly same write operation SPSRAM_HDL. During write cycle, DOUT[] remains stable. rising edge read cycle initiated when high low. data DOUT[] become valid after delay. While standby mode that high, DI[] disabled, data stored memory retained DOUT[] remains stable. When high, DOUT[] placed high-impedance state.
SPSRAMBW_HDL Function Table
Valid Valid Valid Valid BWEN Valid Valid Valid DOUT DOUT(t-1) DOUT(t-1) DOUT(t-1) DOUT(t-1) MEM(A) Comment Unconditional tri-state output De-selected (standby mode) Word-write cycle Bit-write cycle operation Read Cycle
STDL130
5-24
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Parameter Description
SPSRAMBW_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number bits word(b), Column mux(y) Number banks(ba) Parameters Ymux(y) Ymux(y) Ymux(y) Ymux =(y) Words Step Step Step 2048 4096 4096 8192 8192 16384 16384 32768
Descriptions
Name Type Clock Description Clock input. CSN, WEN, DI[] latched into rising edge rising edge write mode. high rising edge read mode. Upon falling edge precharge state.
Chip Enable Chip enable input. chip enable active-low latched into rising edge When low, enabled reading writing, depending state WEN. When high, goes standby mode disabled reading writing. DOUT remains previous data output. Read/Write Enable Read write enable input. read/write enable latched into rising edge When low, data written addressed location DOUT remains stable. When high, data from addressed word presented DOUT. Bit-write enable input bus. bit-write enable latched into rising edge Each BWEN[] enables/disables write operation corresponding data bit. BWEN[i] corresponds DI[i] bit-write. BWEN[0] BWEN[1] high, DI[0] written into memory location specified A[], DI[1] written. Data output enable input. data output enable asynchronously operated regardless input. When high, DOUT disabled goes high-impedance state. Address input bus. address latched into rising edge Data input bus. Data latched rising edge Data input written into addressed location write mode.
BWEN[]
Bit-Write Enable
Data Output Enable Address Data Input
DI[] DOUT[]
Data Output Data output bus. Data output valid after rising edge while read mode. Data output remains previous data output while write mode.
Samsung ASIC
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Capacitance
11.53 6.79 4.74 BWEN 4.74 4.74 4.74 4.74 Unit: [SL] DOUT 17.08
NOTE: Each pin's capacitance exactly same regardless available types same bank.
Block Diagrams
SPSRAMBW_HDL different physical architectures word depth. Optionally, these architectures generated from SPSRAMBW_HDL compiler. dual-bank, bank selected address only activated while other bank idle mode. 1-bank architecture, power ports located middle-edge bottom edge both right- left-sides memory. 2-bank architecture, power ports located middle-edge bottom-edge both right- left-sides memory. signal ports only located bottom sides memory regardless architecture.
<1-bank architecture>
Word-line Decoder
Word-line Decoder
X-Dec
Core
Core
Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp.
Driver
Address Clock Buffers
Driver
BWEN[b/2-1:0]
BWEN[b-1:b/2] DI[b-1:b/2]
DOUT[b-1:b/2]
DOUT[b/2-1:0]
DI[b/2-1:0]
A[m-1:0]
STDL130
5-26
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write
<2-bank architecture
Word-line Decoder Word-line Decoder X-Dec
Core
Core
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block Word-line Decoder Word-line Decoder
X-Dec
Core
Core
Driver
Address Clock Buffers A[m-1:0]
Driver
BWEN[b/2-1:0]
DOUT[b-1:b/2] BWEN[b-1:b/2] DI[b-1:b/2]
DOUT[b/2-1:0]
DI[b/2-1:0]
Application Notes
Permitting Over-the-cell routing chip-level layout, over-the-cell routing SPSRAMBW_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides SPSRAMBW_HDL. byte-write word-write operation with SPSRAMBW_HDL. Refer function table. byte-write operation, number BWEN[] signal should divided byte eight BWEN signals should tied connection wire. this case, DI[] controlled byte-wired BWEN signal instead each BWEN bit. word-write operation, functionality exactly same SPSRAM_HDL. BWEN[] signal tied state, DI[] only controlled WEN. Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode except that tied low. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
Samsung ASIC
5-27
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckh Clock pulse width high tckl Clock pulse width Address setup time Address hold time setup time hold time Data-In setup time Data-In hold time setup time hold time tbws BWEN setup time tbwh BWEN hold time tacc Data access time De-access time DOUT drive high-Z time DOUT high-Z drive time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations. Definition Area (µm) Width physical width X-direction Height physical height Y-direction
STDL130
5-28
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.76 0.86 0.43 0.94 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.49 0.01 2.35 1.80 0.23 0.26 0.81 149.56 154.13 49.98 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.76 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.49 0.01 2.36 1.77 0.23 0.26 0.81 163.93 167.56 57.51 580.84 260.18 2.83 0.86 0.43 0.95 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.47 0.01 2.43 1.87 0.24 0.28 0.83 212.12 223.87 69.92 687.08 226.08 2.81 0.86 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.47 0.01 2.41 1.82 0.24 0.28 0.83 228.26 235.91 79.53 815.72 307.34 2.97 0.86 0.43 0.95 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.45 0.01 2.57 2.00 0.26 0.30 0.86 280.56 308.95 90.21 879.08 320.40 2.90 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.46 0.01 2.50 1.90 0.26 0.31 0.86 296.88 313.05 102.49 1050.60 401.66 3.10 0.86 0.43 0.96 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.44 0.01 2.70 2.12 0.27 0.32 0.89 350.76 404.47 109.47 1091.68 414.72 2.98 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.46 0.01 2.58 1.97 0.26 0.32 0.89 371.13 398.99 124.82 1306.08 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-29
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 1024 3.22 0.86 0.43 0.96 0.01 0.45 0.01 0.47 0.01 0.78 0.01 0.43 0.01 2.82 2.23 0.28 0.34 0.93 421.34 507.19 128.75 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 1024 3.07 0.86 0.43 0.98 0.01 0.45 0.01 0.47 0.01 0.78 0.01 0.45 0.01 2.67 2.04 0.27 0.34 0.93 444.55 487.37 148.89 1540.96 590.30 1536 3.50 0.86 0.43 0.98 0.01 0.45 0.01 0.46 0.01 0.78 0.01 0.41 0.01 3.10 2.50 0.28 0.35 0.96 511.18 651.81 150.10 1475.68 697.68 1536 3.20 0.86 0.43 0.98 0.01 0.45 0.01 0.46 0.01 0.78 0.01 0.45 0.01 2.80 2.16 0.28 0.35 0.96 524.83 598.99 174.75 1775.84 778.94 2048 3.54 0.86 0.43 0.99 0.01 0.45 0.01 0.46 0.01 0.78 0.01 0.40 0.01 3.14 2.53 0.29 0.37 0.99 581.85 801.67 170.32 1667.68 886.32 2048 3.34 0.86 0.43 0.98 0.01 0.45 0.01 0.45 0.01 0.78 0.01 0.45 0.01 2.94 2.28 0.29 0.37 0.99 608.05 720.66 201.31 2010.72 967.58 4096 3.69 0.86 0.43 0.99 0.01 0.45 0.01 0.44 0.01 0.77 0.01 0.48 0.01 3.28 2.60 0.29 0.37 0.99 666.40 876.01 216.24 2010.72 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-30
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.76 0.86 0.43 0.94 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.50 0.01 2.36 1.80 0.22 0.25 0.79 118.96 125.05 31.50 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.76 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.50 0.01 2.36 1.78 0.22 0.25 0.79 131.20 138.65 38.58 537.96 260.18 2.84 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.48 0.01 2.44 1.87 0.23 0.26 0.81 166.33 177.76 42.22 687.08 226.08 2.81 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.49 0.01 2.41 1.53 0.23 0.27 0.81 178.98 191.07 50.99 751.40 307.34 1024 2.97 0.86 0.43 0.95 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.47 0.01 2.57 2.01 0.24 0.28 0.83 219.97 240.76 53.29 879.08 320.40 1024 2.90 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.48 0.01 2.50 1.90 0.24 0.29 0.83 230.70 249.42 64.02 964.84 401.66 1536 3.10 0.86 0.43 0.96 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.46 0.01 2.70 2.12 0.25 0.29 0.85 275.80 311.14 63.28 1091.68 414.72 1536 2.99 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.47 0.01 2.59 1.98 0.25 0.29 0.85 288.66 315.46 76.29 1198.88 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-31
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2048 3.22 0.87 0.43 0.97 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.45 0.01 2.82 2.23 0.26 0.31 0.88 330.59 383.70 74.34 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2048 3.07 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.47 0.01 2.67 2.04 0.25 0.31 0.88 344.67 380.68 90.02 1412.32 590.30 3072 3.50 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.44 0.01 3.10 2.51 0.26 0.32 0.90 404.75 484.13 85.37 1475.68 697.68 3072 3.20 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.47 0.01 2.80 2.16 0.26 0.32 0.91 406.02 459.49 104.67 1625.76 778.94 4096 3.54 0.86 0.43 0.99 0.01 0.45 0.01 0.47 0.01 0.78 0.01 0.42 0.01 3.14 2.53 0.27 0.33 0.92 460.58 580.26 96.38 1667.68 886.32 4096 3.34 0.86 0.43 0.98 0.01 0.45 0.01 0.47 0.01 0.78 0.01 0.47 0.01 2.94 2.28 0.27 0.33 0.93 469.51 544.15 119.71 1839.20 967.58 8192 3.69 0.86 0.43 0.99 0.01 0.45 0.01 0.46 0.01 0.77 0.01 0.50 0.01 3.28 2.60 0.27 0.34 0.92 517.89 637.04 127.91 1839.20 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-32
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.78 0.86 0.43 0.94 0.01 0.45 0.01 0.53 0.01 0.78 0.01 0.51 0.01 2.38 1.80 0.21 0.24 0.78 89.21 91.32 23.37 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 2.80 0.86 0.43 0.98 0.01 0.45 0.01 0.53 0.01 0.78 0.01 0.52 0.01 2.40 1.78 0.21 0.24 0.78 101.43 105.08 30.17 516.52 260.18 1024 2.86 0.86 0.43 0.95 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.49 0.01 2.46 1.87 0.22 0.25 0.80 121.62 125.75 30.03 687.08 226.08 1024 2.86 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.50 0.01 2.45 1.83 0.22 0.26 0.80 134.21 139.96 38.28 719.24 307.34 2048 3.00 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.48 0.01 2.59 2.01 0.23 0.27 0.82 160.11 167.80 37.03 879.08 320.40 2048 2.94 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.50 0.01 2.54 1.90 0.23 0.27 0.82 170.70 179.30 46.84 921.96 401.66 3072 3.12 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.47 0.01 2.72 2.12 0.24 0.28 0.84 201.29 215.24 42.82 1091.68 414.72 3072 3.03 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.50 0.01 2.63 1.98 0.24 0.28 0.83 212.89 224.97 54.27 1145.28 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-33
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 4096 3.24 0.86 0.43 0.96 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.46 0.01 2.84 2.23 0.25 0.29 0.85 241.37 263.34 49.88 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 4096 3.11 0.87 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.50 0.01 2.71 2.04 0.24 0.29 0.85 253.35 269.22 63.43 1348.00 590.30 6144 3.53 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.46 0.01 3.12 2.51 0.25 0.30 0.87 300.65 331.64 56.91 1475.68 697.68 6144 3.25 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.49 0.01 2.84 2.16 0.25 0.30 0.87 298.65 322.68 72.98 1550.72 778.94 8192 3.56 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.46 0.01 3.16 2.53 0.26 0.31 0.89 340.70 390.77 64.07 1667.68 886.32 8192 3.38 0.86 0.43 0.98 0.01 0.45 0.01 0.48 0.01 0.78 0.01 0.49 0.01 2.98 2.28 0.26 0.32 0.89 345.86 379.97 82.67 1753.44 967.58 16384 3.73 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.77 0.01 0.52 0.01 3.32 2.60 0.26 0.32 0.89 389.65 441.17 87.74 1753.44 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-34
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 1024 2.82 0.86 0.43 0.94 0.01 0.45 0.01 0.53 0.01 0.78 0.01 0.53 0.01 2.42 1.80 0.21 0.24 0.78 74.32 74.08 18.79 495.08 178.92 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 1024 2.88 0.86 0.43 0.98 0.01 0.45 0.01 0.53 0.01 0.77 0.01 0.55 0.01 2.47 1.78 0.21 0.24 0.78 86.46 87.95 25.42 505.80 260.18 2048 2.90 0.86 0.43 0.95 0.01 0.45 0.01 0.52 0.01 0.78 0.01 0.51 0.01 2.50 1.88 0.22 0.25 0.79 99.19 99.02 23.16 687.08 226.08 2048 2.93 0.86 0.43 0.98 0.01 0.45 0.01 0.52 0.01 0.77 0.01 0.54 0.01 2.53 1.83 0.22 0.25 0.79 111.66 113.74 31.12 703.16 307.34 4096 3.04 0.86 0.43 0.95 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.49 0.01 2.63 2.01 0.23 0.26 0.81 130.21 130.12 27.89 879.08 320.40 4096 3.02 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.53 0.01 2.61 1.90 0.23 0.27 0.81 140.50 143.22 37.19 900.52 401.66 6144 3.17 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.49 0.01 2.76 2.12 0.24 0.27 0.83 163.91 165.47 31.08 1091.68 414.72 6144 3.10 0.86 0.43 0.98 0.01 0.45 0.01 0.51 0.01 0.78 0.01 0.53 0.01 2.70 1.98 0.23 0.28 0.83 174.70 177.90 41.49 1118.48 495.98
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 8192 3.29 0.86 0.43 0.96 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.49 0.01 2.89 2.23 0.24 0.28 0.84 196.64 201.29 35.98 1283.68 509.04 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 8192 3.18 0.87 0.43 0.98 0.01 0.45 0.01 0.50 0.01 0.78 0.01 0.52 0.01 2.78 2.04 0.24 0.29 0.84 207.56 211.70 48.26 1315.84 590.30 12288 3.57 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.48 0.01 3.17 2.50 0.25 0.29 0.86 248.73 253.62 40.85 1475.68 697.68 12288 3.32 0.87 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.52 0.01 2.92 2.16 0.25 0.29 0.86 244.94 252.35 55.18 1315.20 778.94 16384 3.60 0.86 0.43 0.99 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.48 0.01 3.20 2.53 0.25 0.30 0.87 281.66 294.27 45.73 1667.68 886.32 16384 3.45 0.86 0.43 0.98 0.01 0.45 0.01 0.49 0.01 0.78 0.01 0.52 0.01 3.05 2.28 0.25 0.30 0.87 284.00 295.71 62.11 1710.56 967.58 32768 3.80 0.86 0.43 0.99 0.01 0.45 0.01 0.48 0.01 0.77 0.01 0.54 0.01 3.40 2.60 0.25 0.30 0.87 324.94 340.72 65.44 1710.56 1722.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-36
Samsung ASIC
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write Timing Diagrams
Read Cycle
tcyc tacc DOUT[] Valid M[A0] M[A1] M[A2] tckh
(CSN low, low, BWEN, don't care)
Write Cycle
tcyc tbws tbwh BWEN[] DI[] tckh
(CSN= low, don't care)
Samsung ASIC
5-37
STDL130
SPSRAMBW_HDL
High-Density Single-Port Synchronous Static with Bit-Write
Read Cycle with CSN-Controlled
tcyc tacc DOUT[] M[A0] M[A1] tckh
(OEN low, high, BWEN, don't care)
OEN-Controlled Output Enable
DOUT[] Hi-Z VALID Hi-Z
(CSN, WEN, BWEN, don't care)
NOTE: "don't care" means condition that these pins normal operation mode.
STDL130
5-38
Samsung ASIC
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Logic Symbol
spsramr_hdl_<w>x<b>m<y>b<ba> BWEN[b-1:0] [m-1:0] [b-1:0] DOUT [b-1:0]
Features
Suitable high-capacity application Heuristic row-redundancy available Bit-write capability Separated data Synchronous operation Duty-free clock cycle Asynchronous tri-state output control Latched inputs outputs Automatic power-down Zero standby current Zero hold time noise output optimization Flexible aspect ratio Dual-bank scheme available 64Kbits 1Mbits capacity number words number bits word
NOTES: Words number words. number word. Ymux column types. Banks(ba) number banks. log2w
Function Description
SPSRAMR_HDL repairable single-port synchronous static with bit-write capability which provided compiler. SPSRAMR_HDL intended high-capacity applications. Basically, functionality exactly same SPSRAMBW_HDL. Each BWEN[] enables disable write operation corresponding DI[]. rising edge write cycle initiated when low. data bytes bits DI[], which their corresponding bit(s) BWEN[] low, written into memory location specified A[]. When bits BWEN[] high, data DI[] written into memory location specified A[]. When bits BWEN[] low, data DI[] written into memory location specified A[], which exactly same write operation SPSRAM_HDL. During write cycle, DOUT[] remains stable. rising edge read cycle initiated when high low. data DOUT[] become valid after delay. While standby mode that high, DI[] disabled, data stored memory retained DOUT[] remains stable. When high, DOUT[] placed high-impedance state.
SPSRAMR_HDL Function Table Valid Valid Valid Valid BWEN Valid Valid Valid DOUT DOUT(t-1) DOUT(t-1) DOUT(t-1) DOUT(t-1) MEM(A) Comment Unconditional tri-state output De-selected (standby mode) Word-write cycle Bit-write cycle operation Read cycle
Samsung ASIC
5-39
STDL130
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Parameter Description
SPSRAMR_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number word(b), Column mux(y) Number banks(ba). Parameters Words Ymux(y) 2048 4096 4096 8192 Ymux(y) 4096 8192 8192 16384 Ymux(y) 8192 16384 16384 32768
Step Step Step
Descriptions
Name Description Clock input. CSN, WEN, DI[] latched into rising edge rising edge write mode. high rising edge read mode. Upon falling edge precharge state. Chip Enable Chip Enable input. chip enable active-low latched into rising edge When low, enabled reading writing, depending state WEN. When high, goes standby mode disabled reading writing. DOUT remains previous data output. Read/Write Read write enable input. read/write enable latched into Enable rising edge When low, data written addressed location DOUT remains stable. When high, data from addressed word present DOUT. Bit-Write Bit-write enable input bus. bit-write enable latched into Enable rising edge Each BWEN[] enables/disables write operation corresponding data bit. BWEN[i] corresponds DI[i] bit-write. BWEN[0] BWEN[1] high, DI[0] written into memory location specified A[], DI[1] written. Data Output Data output enable input. data output enable asynchronously operated Enable regardless input. When high, DOUT disabled goes high-impedance state. Address Address input bus. address latched into rising edge Data Input Data input bus. Data latched rising edge Data input written into addressed location write mode. Data Output Data output bus. Data output valid after rising edge while read mode. Data output remains previous data output while write mode. Type Clock
BWEN[]
DI[] DOUT[]
STDL130
5-40
Samsung ASIC
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Capacitance
13.2922 3.1070 3.2305 BWEN 3.5597 5.2058 3.3539 3.4774 (Unit DOUT 9.4444
NOTE: Each pin's capacitance exactly same regardless available types same bank
Block Diagrams
SPSRAMR_HDL different physical architectures word depth. Optionally, these architectures generated from SPSRAMR_HDL compiler. dual-bank, bank selected address only activated while other bank idle mode. 1-bank architecture, power ports located middle-edge bottom edge both right- left-sides memory. 2-bank architecture, power ports located top-edge, middle-edge bottom-edge both right- left-sides memory. signal ports only located bottom sides memory regardless architecture.
<1-bank architecture>
Word-line Decoder
Word-line Decoder
X-Dec
Core
Core
Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp.
Driver
Address Clock Buffers
Driver
BWEN[b/2-1:0]
BWEN[b-1:b/2]
DI[b/2-1:0]
DOUT[b/2-1:0]
DOUT[b-1:b/2]
DI[b-1:b/2]
A[m-1:0]
Samsung ASIC
5-41
STDL130
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy
<2-bank architecture
Word-line Decoder Word-line Decoder X-Dec
Core
Core
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block Word-line Decoder Word-line Decoder
X-Dec
Core
Core
Driver
Address Clock Buffers A[m-1:0]
Driver
BWEN[b-1:b/2]
DI[b/2-1:0]
DOUT[b/2-1:0]
BWEN[b/2-1:0]
DOUT[b-1:b/2]
DI[b-1:b/2]
Application Notes
Permitting over-the-cell routing. chip-level layout, over-the-cell routing SPSRAMR_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides SPSRAMR_HDL. byte-write word-write operation with SPSRAMR_HDL. Refer function table. byte-write operation, number BWEN[] signal should divided byte eight BWEN signals should tied connection wire. this case, DI[] controlled byte-wired BWEN signal instead each BWEN bit. word-write operation, functionality exactly same SPSRAM_HDL. BWEN[] signal tied state, DI[] only controlled WEN. Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
STDL130
5-42
Samsung ASIC
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckl Clock pulse width tckh Clock pulse width high Address setup time Address hold time setup time hold time Data-In setup time Data-In hold time setup time hold time tbws BWEN setup time tbwh BWEN hold time tacc Data access time De-access time DOUT drive high-Z time DOUT high-Z drive time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations. Definition Area (µm) Width physical width X-direction Height physical height Y-direction
Samsung ASIC
5-43
STDL130
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2048 4.13 0.69 0.40 0.62 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.75 0.01 3.93 3.59 0.35 0.54 0.81 290.85 338.02 56.39 998.96 521.58 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 4096 4.22 0.70 0.40 0.64 0.01 0.40 0.01 0.70 0.01 0.66 0.01 0.75 0.01 4.02 3.62 0.36 0.54 0.81 397.69 452.41 73.16 1084.72 991.64 2048 4.18 0.69 0.40 0.62 0.01 0.39 0.01 0.69 0.01 0.66 0.01 0.74 0.01 3.98 3.61 0.38 0.56 0.88 515.51 608.79 99.11 1766.96 521.58 4096 4.27 0.70 0.40 0.64 0.01 0.40 0.01 0.69 0.01 0.66 0.01 0.74 0.01 4.07 3.64 0.38 0.58 0.88 704.49 812.22 126.46 1938.48 991.64 04096 4.34 0.69 0.40 0.62 0.01 0.39 0.01 0.69 0.01 0.66 0.01 0.74 0.01 3.99 3.61 0.38 0.56 0.88 521.76 675.71 99.18 1766.96 912.54 8192 4.40 0.69 0.40 0.65 0.01 0.40 0.01 0.69 0.01 0.66 0.01 0.74 0.01 4.14 3.69 0.38 0.56 0.88 727.02 893.49 133.67 1938.48 1773.56 4096 4.53 0.69 0.40 0.62 0.01 0.39 0.01 0.68 0.01 0.66 0.01 0.73 0.01 4.12 3.63 0.39 0.58 1.06 968.50 1282.80 184.29 3302.96 926.22 8192 4.58 0.69 0.40 0.65 0.01 0.40 0.01 0.68 0.01 0.66 0.01 0.73 0.01 4.28 3.70 0.39 0.58 1.06 1352.60 1689.60 246.90 3646.00 1800.92
NOTE: Standby power measured condition that other signals normal operation while disable mode.
STDL130
5-44
Samsung ASIC
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 4096 4.15 0.69 0.41 0.62 0.01 0.39 0.01 0.70 0.01 0.65 0.01 0.75 0.01 3.95 3.59 0.35 0.54 0.80 275.02 296.53 45.67 998.96 521.58 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 8192 4.26 0.70 0.40 0.64 0.01 0.39 0.01 0.71 0.01 0.66 0.01 0.75 0.01 4.05 3.62 0.35 0.54 0.80 388.37 417.77 68.35 1041.84 991.64 4096 4.21 0.69 0.41 0.62 0.01 0.39 0.01 0.69 0.01 0.65 0.01 0.74 0.01 4.01 3.61 0.37 0.57 0.86 483.42 524.89 77.48 1766.96 521.58 8192 4.31 0.70 0.40 0.64 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.74 0.01 4.11 3.64 0.37 0.56 0.86 685.81 742.84 116.73 1852.72 991.64 8192 4.35 0.69 0.41 0.62 0.01 0.39 0.01 0.69 0.01 0.65 0.01 0.74 0.01 4.01 3.61 0.37 0.56 0.86 489.52 561.36 77.64 1766.96 912.54 16384 4.40 0.69 0.40 0.65 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.74 0.01 4.18 3.69 0.37 0.56 0.86 703.61 789.48 120.65 1852.72 1773.56 8192 4.55 0.69 0.41 0.62 0.01 0.39 0.01 0.68 0.01 0.65 0.01 0.73 0.01 4.15 3.63 0.38 0.57 1.00 904.64 1050.70 141.37 3302.96 926.22 16384 4.57 0.69 0.40 0.65 0.01 0.39 0.01 0.69 0.01 0.66 0.01 0.73 0.01 4.32 3.70 0.38 0.57 1.00 1306.60 1479.60 220.87 3474.48 1800.92
NOTE: Standby power measured condition that other signals normal operation while disable mode.
Samsung ASIC
STDL130
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 8192 4.19 0.69 0.40 0.62 0.01 0.39 0.01 0.71 0.01 0.66 0.01 0.75 0.01 3.99 3.58 0.35 0.53 0.80 262.23 270.93 36.36 998.96 521.58 (Typical process, 1.8V, 25°C, Output load=10SL, Input slope=0.2 SA=0.5) 16384 4.33 0.69 0.41 0.64 0.01 0.40 0.01 0.70 0.01 0.65 0.01 0.75 0.01 4.13 3.62 0.35 0.53 0.81 374.33 391.47 58.00 1020.40 991.64 8192 4.25 0.69 0.40 0.62 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.75 0.01 4.04 3.61 0.36 0.55 0.85 458.38 474.11 58.94 1766.96 521.58 16384 4.39 0.69 0.41 0.64 0.01 0.39 0.01 0.69 0.01 0.65 0.01 0.74 0.01 4.18 3.64 0.36 0.55 0.86 658.11 689.45 96.02 1809.84 991.64 16384 4.44 0.69 0.40 0.62 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.74 0.01 4.08 3.62 0.36 0.55 0.85 464.87 495.36 58.90 1766.96 912.54 32768 4.50 0.69 0.40 0.65 0.01 0.39 0.01 0.70 0.01 0.66 0.01 0.80 0.01 4.29 3.70 0.36 0.55 0.86 672.90 719.43 98.31 1809.84 1773.56 16384 4.54 0.69 0.40 0.62 0.01 0.39 0.01 0.69 0.01 0.66 0.01 0.74 0.01 4.19 3.63 0.38 0.57 0.97 854.92 916.87 104.12 3302.96 926.22 32768 4.61 0.69 0.40 0.65 0.01 0.39 0.01 0.69 0.01 0.66 0.01 0.73 0.01 4.39 3.70 0.38 0.57 0.97 1246.50 1338.00 176.19 3388.72 1800.92
NOTE: Standby power measured condition that other signals normal operation while disable mode.
STDL130
5-46
Samsung ASIC
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy Timing Diagrams
Read Cycle
tcyc tacc DOUT[] Valid M[A0] M[A1] M[A2] tckh
(CSN low, low, BWEN, don't care)
Write Cycle
tcyc tbws tbwh BWEN[] DI[] tckh
(CSN= low, don't care)
Samsung ASIC
5-47
STDL130
SPSRAMR_HDL
Single-Port Synchronous Static with Redundancy
Read Cycle with CSN-Controlled
tcyc tacc DOUT[] M[A0] M[A1] tckh
(OEN low, high, BWEN, don't care)
OEN-Controlled Output Enable
DOUT[] Hi-Z valid Hi-Z
(CSN, WEN, BWEN, don't care)
NOTE: "don't care" means condition that these pins normal operation mode.
STDL130
5-48
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Logic Symbol
dpsram_hdl_<w>x<b>m<y> CSN1 CSN2 WEN1 WEN2 OEN1 OEN2 [m-1:0] [m-1:0] [b-1:0] [b-1:0]
Features
DOUT1 [b-1:0]
Suitable high-density application Separated data Synchronous operation Duty-free clock cycle Asynchronous tri-state output control Latched inputs outputs Automatic power-down Zero standby current Zero hold time noise output optimization Flexible aspect ratio 256Kbits capacity number words number bits word
DOUT2 [b-1:0]
NOTES: Words number words. number bits word. Ymux column types. log2w
Function Description
DPSRAM_HDL dual-port synchronous static which provided compiler. DPSRAM_HDL intended high-density applications. Each port fully independent. rising edge CK1(CK2), write cycle initiated when WEN1 (WEN2) CSN1 (CSN2) low. data DI1[] (DI2[]) written into memory location specified A1[](A2[]). During write cycle, DOUT1[] (DOUT2[]) remains stable. rising edge read cycle initiated when WEN1 (WEN2) high CSN1(CSN2) low. data DOUT1[] (DOUT2[]) become valid after delay. While standby mode that CSN1(CSN2) high, A1[](A2[]) DI1[] (DI2[]) disabled, data stored memory retained DOUT1[] (DOUT2[]) remains stable. When OEN1 (OEN2) high, DOUT1[] (DOUT2[]) placed high-impedance state. DPSRAM_HDL Function Table CSN1 CSN2 WEN1 WEN2 OEN1 OEN2 Valid Valid Valid DOUT1 DOUT2 DOUT(t-1) DOUT(t-1) MEM(A) Comment Unconditional tri-state output De-selected (standby mode) Write cycle Read cycle
Samsung ASIC
5-49
STDL130
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Parameter Description
DPSRAM_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number bits word(b) Column mux(y). Parameters Words Step Step Ymux(y) 2048 Ymux(y) 4096 Ymux(y) 8192 Ymux(y) 16384
Descriptions
Name CSN1 CSN2 Description Clock input. CSN, WEN, DI[] latched into rising edge rising edge write mode. high rising edge read mode. Chip Enable Chip enable input. chip enable active-low latched into rising edge When low, enabled reading writing, depending state WEN. When high, goes standby mode disabled reading writing. DOUT remains previous data output. Read/Write Read write enable input. read/write enable latched into Enable rising edge When low, data written addressed location DOUT remains stable. When high, data from addressed word presented DOUT. Data Output Data output enable input. data output enable asynchronously operated Enable regardless state other inputs. When high, DOUT disabled goes high-impedance state. Address Address input bus. address latched into rising edge Data Input Data input bus. Data latched rising edge Data input written into addressed location write mode. Type Clock
WEN1 WEN2
OEN1 OEN2 DOUT1 DOUT2
Data Output Data output bus. Data output valid after rising edge while read mode. Data output remains previous data output while write mode. (Unit 4.84 11.67 4.84 5.49 DOUT 35.72
Capacitance
33.44 4.84
NOTE: Each pin's capacitance exactly same regardless available types.
STDL130
5-50
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Block Diagram
DPSRAM_HDL supports only 1-bank architecture. power ports located edge bottom edge both right- left-sides memory. However, DPSRAM_HDL symmetrical ports located opposite edges memory. Port1 located bottom memory while Port2 located memory.
DOUT2[b-1:b/2]
DOUT2[b/2-1:0]
DI2[b/2-1:0]
DI2[b-1:b/2]
A2[m-1:0]
WEN2
OEN2
CSN2
Driver Y-Dec Sense Amp. Word-line Decoder
Address Clock Buffers Control Block Word-line Decoder
Driver Y-Dec Sense Amp.
X-Dec
Core
Core
Y-Dec Sense Amp. DOUT1[b/2-1:0] DI1[b/2-1:0] Driver
Control Block Address Clock Buffers A1[m-1:0] WEN1 CSN1 OEN1
Y-Dec Sense Amp. Driver DI1[b-1:b/2] DOUT1[b-1:b/2]
Samsung ASIC
5-51
STDL130
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Application Notes
Permitting over-the-cell routing chip-level layout, over-the-cell routing DPSRAM_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides DPSRAM_HDL. Contention mode same address access DPSRAM_HDL, simultaneous operation both ports same memory address, write/write, write/read read/write operation, causes contention problem. Simultaneous operation defined state which both ports enabled, both address buses equal rising edge DPSRAM_HDL scheme preventing contention. simultaneous operation, silicon will behave unpredictably. write operation cannot data appearing outputs valid. Please refer timing diagrams want avoid contention mode between both ports. write/write operation, data stored current address will unpredictable. write/read read/write operation, read port invalid while write port still valid. want avoid contention mode, have give value greater than (clock-to-clock setup time). However, simultaneous read/read allowable without restrictions. Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode except that tied low. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
STDL130
5-52
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckl Clock pulse width tckh Clock pulse width high Clock-to-clock setup time Address setup time Address hold time setup time hold time Data-In setup time Data-In hold time setup time hold time tacc Data access time De-access time DOUT drive high-Z time DOUT high-Z drive time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations Definition Area (µm) Width physical width X-direction Height physical height Y-direction
Samsung ASIC
5-53
STDL130
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.60 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 2.32 2.19 0.48 0.59 0.72 85.12 91.14 30.47 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.67 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 2.39 2.25 0.52 0.61 0.76 143.24 158.37 47.91 893.80 217.72 2.78 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.73 0.01 0.46 0.01 2.51 2.35 0.56 0.64 0.79 204.85 232.43 66.63 1239.40 264.92 2.97 0.88 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 2.69 2.53 0.59 0.66 0.83 274.26 322.29 87.95 1585.00 359.32 3.11 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.69 0.01 0.46 0.01 2.83 2.64 0.59 0.68 0.84 354.25 425.64 110.35 2008.60 453.60 1024 3.27 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.66 0.01 0.47 0.01 2.99 2.78 0.62 0.71 0.87 430.52 530.99 131.36 2354.20 547.86 1536 3.58 0.81 0.42 1.90 0.48 0.01 0.56 0.01 0.63 0.01 0.47 0.01 3.30 3.05 0.66 0.75 0.90 526.29 679.63 157.27 2699.80 736.38 2048 3.63 0.78 0.42 1.99 0.45 0.01 0.56 0.01 0.60 0.01 0.48 0.01 3.35 3.08 0.69 0.79 0.93 604.69 826.61 183.05 3045.40 925.16
NOTES: power consumption DPSRAM_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-54
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.62 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 2.34 2.21 0.48 0.59 0.72 78.94 77.66 25.85 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.69 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 2.42 2.27 0.52 0.61 0.76 130.90 130.73 38.65 893.80 217.72 2.81 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 2.53 2.37 0.55 0.64 0.79 186.34 189.00 52.75 1239.40 264.92 1024 2.99 0.88 0.42 1.28 0.52 0.01 0.57 0.01 0.70 0.01 0.46 0.01 2.71 2.55 0.59 0.66 0.82 249.50 259.15 69.44 1585.00 359.32 1536 3.13 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.70 0.01 0.46 0.01 2.85 2.66 0.59 0.67 0.83 322.74 341.26 88.26 2008.60 453.60 2048 3.30 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.67 0.01 0.47 0.01 3.02 2.80 0.62 0.71 0.87 390.88 421.80 104.91 2354.20 547.86 3072 3.60 0.52 0.42 1.90 0.48 0.01 0.56 0.01 0.64 0.01 0.47 0.01 3.32 3.07 0.65 0.74 0.90 478.87 533.41 126.45 2699.80 736.38 4096 3.65 0.79 0.42 1.99 0.45 0.01 0.56 0.01 0.61 0.01 0.48 0.01 3.37 3.10 0.68 0.78 0.93 549.35 635.85 148.04 3045.40 925.16
NOTES: power consumption DPSRAM_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
STDL130
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.66 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 2.38 2.25 0.48 0.59 0.72 76.55 71.82 23.63 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.74 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 2.46 2.32 0.52 0.62 0.75 124.80 116.86 33.56 893.80 217.72 1024 2.85 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 2.57 2.41 0.55 0.64 0.79 176.52 166.27 44.78 1239.40 264.92 2048 3.03 0.89 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 2.75 2.59 0.59 0.66 0.82 235.95 225.58 64.01 1585.00 359.32 3072 3.17 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.70 0.01 0.46 0.01 2.89 2.70 0.59 0.67 0.83 306.04 296.70 74.97 2008.60 453.60 4096 3.34 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.67 0.01 0.47 0.01 3.06 2.84 0.62 0.71 0.86 370.88 364.14 88.83 2354.20 547.86 6144 3.64 0.82 0.42 1.90 0.48 0.01 0.56 0.01 0.64 0.01 0.47 0.01 3.36 3.11 0.65 0.74 0.89 455.52 457.15 107.67 2699.80 736.38 8192 3.69 0.79 0.42 1.99 0.45 0.01 0.56 0.01 0.61 0.01 0.48 0.01 3.41 3.14 0.68 0.78 0.92 522.06 536.50 126.50 3045.40 925.16
NOTES: power consumption DPSRAM_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-56
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.74 0.99 0.42 0.92 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 2.45 2.33 0.48 0.60 0.72 76.14 70.22 22.75 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 1024 2.81 0.96 0.42 0.99 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 2.53 2.39 0.52 0.62 0.75 122.30 110.68 31.11 893.80 217.72 2048 2.92 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 2.64 2.49 0.55 0.64 0.79 171.91 155.18 40.76 1239.40 264.92 4096 3.11 0.89 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 2.83 2.66 0.59 0.66 0.82 229.17 208.77 53.00 1585.00 359.32 6144 3.25 0.88 0.42 1.41 0.51 0.01 0.56 0.01 0.69 0.01 0.46 0.01 2.97 2.77 0.60 0.66 0.84 298.21 274.68 68.33 2008.60 453.60 8192 3.42 0.86 0.42 1.58 0.50 0.01 0.56 0.01 0.68 0.01 0.47 0.01 3.14 2.91 0.62 0.70 0.87 361.04 335.43 80.78 2354.20 547.86 12288 3.72 0.84 0.42 1.90 0.48 0.01 0.56 0.01 0.66 0.01 0.48 0.01 3.44 3.18 0.65 0.74 0.89 443.86 418.81 98.25 2699.80 736.38 16384 3.77 0.82 0.42 1.99 0.45 0.01 0.56 0.01 0.64 0.01 0.48 0.01 3.49 3.21 0.68 0.78 0.92 508.62 486.29 115.73 3045.40 925.16
NOTES: power consumption DPSRAM_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-57
STDL130
DPSRAM_HDL
High-Density Dual-Port Synchronous Static Timing Diagrams
Read Cycle
tcyc tacc DOUT[] Valid M[A0] M[A1] M[A2] tckh
(CSN low, low, DI[] don't care)
Write Cycle
tcyc DI[] (CSN= low, don't care) tckh
STDL130
5-58
Samsung ASIC
DPSRAM_HDL
High-Density Dual-Port Synchronous Static
Read Cycle with CSN-Controlled
tcyc tckl tacc DOUT[] M[A0] M[A1] tckh
(OEN low, high, DI[] don't care)
OEN-Controlled Output Enable
DOUT[] Hi-Z VALID Hi-Z
(CSN, A[], WEN, DI[] don't care)
Contention Mode
(A1[] A2[])
NOTE: "don't care" means condition that these pins normal operation mode.
Samsung ASIC
5-59
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Logic Symbol
dpsrambw_hdl_<w>x<b>m<y> CSN1 DOUT1 [b-1:0] CSN2 WEN1 WEN2 BWEN1[b-1:0] BWEN2[b-1:0] OEN1 OEN2 [m-1:0] DOUT2 [b-1:0] [m-1:0] [b-1:0] [b-1:0]
Features
Suitable high-density application Separated data Synchronous operation Duty-free clock cycle Asynchronous tri-state output control Latched inputs outputs Automatic power-down Zero standby current Zero hold time noise output optimization Flexible aspect ratio 256Kbits capacity number words number bits word
NOTES: Words number words. number bits word. Ymux column types. log2w
Function Description
DPSRAMBW_HDL dual-port synchronous static with bit-write capability which provided compiler. DPSRAMBW_HDL intended high-density applications. Each port fully independent. Basically, functionality exactly same DPSRAM_HDL except bit-write operation which controlled BWEN1[](BWEN2[]), named bit-write enable signal bus. Each BWEN1[](BWEN2[]) enables disable write operation corresponding DI1[](DI2[]). rising edge CK1(CK2), write cycle initiated when WEN1(WEN2) CSN1(CSN2) low. data bits DI1[](DI2[]), which their corresponding bit(s) BWEN1[](BWEN2[]) low, written into memory location specified A1[](A2[]). When bits BWEN1[](BWEN2[]) high, data DI1[](DI2[]) written into memory location specified A1[](A2[]). When bits BWEN1[](BWEM2[]) low, data DI1[](DI2[]) written into memory location specified A1[](A2[]), which exactly same write operation DPSRAMBW_HDL. During write cycle, DOUT1[](DOUT2[]) remains stable. rising edge CK1(CK2), read cycle initiated when WEN1(WEN2) high CSN1(CSN2) low. data DOUT1[](DOUT2[]) become valid after delay. While standby mode that CSN1(CSN2) high, A1[](A2[]) DI1[](DI2[]) disabled, data stored memory retained DOUT1[](DOUT2[]) remains stable. When OEN1(OEN2) high, DOUT1[](DOUT2[]) placed high-impedance state. DPSRAMBW_HDL Function Table CSN1 CSN2 WEN1 WEN2 OEN1 OEN2 Valid Valid Valid Valid BWEN1 BWEN2 Valid Valid Valid DOUT1 DOUT2 DOUT(t-1) DOUT(t-1) DOUT(t-1) DOUT(t-1) MEM(A) Comment Unconditional tri-state output De-selected (standby mode) Word-write cycle Bit-write cycle operation Read cycle
STDL130
5-60
Samsung ASIC
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Parameter Description
DPSRAMBW_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number bits word(b) Column mux(y). Parameters Words Step Step Ymux(y) 2048 Ymux(y) 4096 Ymux(y) 8192 Ymux(y) 16384
Descriptions
Name Description Clock input. CSN, WEN, DI[] latched into rising edge rising edge write mode. high rising edge read mode. Upon falling edge precharge state. Chip Enable Chip enable input. chip enable active-low latched into rising edge When low, enabled reading writing, depending state WEN. When high, goes standby mode disabled reading writing. DOUT remains previous data output. Read/Write Read write enable input. read/write enable latched into Enable rising edge When low, data written addressed location DOUT remains stable. When high, data from addressed word presented DOUT. Bit-Write Enable Bit-write enable input bus. bit-write enable latched into rising edge Each BWEN[] enables/disables write operation corresponding data bit. BWEN[i] corresponds DI[i] bit-write. BWEN[0] BWEN[1] high, DI[0] written into memory location specified A[], DI[1] written. Data output enable input. data output enable asynchronously operated regardless state other inputs. When high, DOUT disabled goes high-impedance state. Address input bus. address latched into rising edge Data input bus. Data latched rising edge Data input written into addressed location write mode. Type Clock
CSN1 CSN2
WEN1 WEN2
BWEN1[ BWEN2[
OEN1 OEN2 DOUT1 DOUT2
Data Output Enable Address Data Input
Data Output Data output bus. Data output valid after rising edge while read mode. Data output remains previous data output while write mode. (Unit 4.84 11.67 4.84 BWEN 5.49 5.49 DOUT 35.72
Capacitance
33.44 4.84
NOTE: Each pin's capacitance exactly same regardless available types.
Samsung ASIC
5-61
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static Bit-Write Block Diagram
DPSRAMBW_HDL supports only 1-bank architecture. power ports located edge bottom edge both right- left-sides memory. However, DPSRAMBW_HDL symmetrical ports located opposite edges memory. Port1 located bottom memory while Port2 located memory.
DOUT2[b-1:b/2] BWEN2[b-1:b/2] DI2[b-1:b/2]
BWEN2[b/2-1:0] DOUT2[b/2-1:0]
DI2[b/2-1:0]
A2[m-1:0]
WEN2
CSN2
OEN2
Driver Y-Dec Sense Amp. Word-line Decoder
Address Clock Buffers Control Block Word-line Decoder
Driver Y-Dec Sense Amp.
X-Dec
Core
Core
Y-Dec Sense Amp. DI1[b/2-1:0] BWEN1[b/2-1:0] DOUT1[b/2-1:0] Driver
Control Block Address Clock Buffers A1[m-1:0] WEN1 CSN1 OEN1
Y-Dec Sense Amp. Driver DOUT1[b-1:b/2] DI1[b-1:b/2] BWEN1[b-1:b/2]
STDL130
5-62
Samsung ASIC
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Application Notes
Permitting over-the-cell routing chip-level layout, over-the-cell routing DPSRAMBW_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides DPSRAMBW_HDL. Contention mode same address access DPSRAMBW_HDL, simultaneous operation both ports same memory address, write/write, write/read read/write operation, causes contention problem. Simultaneous operation defined state which both ports enabled, both address buses equal rising edge DPSRAMBW_HDL scheme preventing contention. simultaneous operation, silicon will behave unpredictably. write operation cannot data appearing outputs valid. Please refer timing diagrams want avoid contention mode between both ports. write/write operation, data stored current address will unpredictable. write/read read/write operation, read port invalid while write port still valid. want avoid contention mode, have give value greater than (clock-to-clock setup time). However, simultaneous read/read allowable without restrictions. byte-write word-write operation with DPSRAMBW_HDL Refer function table. byte-write operation, number BWEN[] signal should divided byte eight BWEN signals should tied connection wire. this case, DI[] controlled byte-wired BWEN signal instead each BWEN bit. word-write operation, functionality exactly same DPSRAM_HDL. BWEN[] signal tied state, DI[] only controlled WEN. Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode except that tied low. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
Samsung ASIC
5-63
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckl Clock pulse width tckh Clock pulse width high Clock-to-clock setup time Address setup time Address hold time setup time hold time Data-In setup time Data-In hold time setup time hold time tbws BWEN setup time tbwh BWEN hold time tacc Data access time De-access time DOUT drive high-Z time DOUT high-Z drive time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations. Definition Area (µm) Width physical width X-direction Height physical height Y-direction
STDL130
5-64
Samsung ASIC
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.60 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 0.77 0.01 2.32 2.19 0.48 0.59 0.72 89.07 95.09 34.42 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.67 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 0.74 0.01 2.39 2.25 0.52 0.61 0.76 151.14 166.27 55.81 893.80 217.72 2.78 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.73 0.01 0.46 0.01 0.70 0.01 2.51 2.35 0.56 0.64 0.79 216.71 244.29 78.49 1239.40 264.92 2.97 0.88 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 0.66 0.01 2.69 2.53 0.59 0.66 0.83 290.07 338.10 103.76 1585.00 359.32 3.11 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.69 0.01 0.46 0.01 0.66 0.01 2.83 2.64 0.59 0.68 0.84 373.98 445.38 130.08 2008.60 453.60 1024 3.27 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.66 0.01 0.47 0.01 0.63 0.01 2.99 2.78 0.62 0.71 0.87 454.24 554.71 155.07 2354.20 547.86 1536 3.58 0.81 0.42 1.90 0.48 0.01 0.56 0.01 0.63 0.01 0.47 0.01 0.59 0.01 3.30 3.05 0.66 0.75 0.90 553.97 707.31 184.95 2699.80 736.38 2048 3.63 0.78 0.42 1.99 0.45 0.01 0.56 0.01 0.60 0.01 0.48 0.01 0.56 0.01 3.35 3.08 0.69 0.79 0.93 636.24 858.16 214.60 3045.40 925.16
NOTES: power consumption DPSRAMBW_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.62 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 0.78 0.01 2.34 2.21 0.48 0.59 0.72 80.92 79.63 27.82 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.69 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 0.74 0.01 2.42 2.27 0.52 0.61 0.76 134.86 134.68 42.60 893.80 217.72 2.81 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 0.70 0.01 2.53 2.37 0.55 0.64 0.79 192.27 194.93 58.68 1239.40 264.92 1024 2.99 0.88 0.42 1.28 0.52 0.01 0.57 0.01 0.70 0.01 0.46 0.01 0.66 0.01 2.71 2.55 0.59 0.66 0.82 257.42 267.07 77.35 1585.00 359.32 1536 3.13 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.70 0.01 0.46 0.01 0.66 0.01 2.85 2.66 0.59 0.67 0.83 332.62 351.14 98.14 2008.60 453.60 2048 3.30 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.67 0.01 0.47 0.01 0.63 0.01 3.02 2.80 0.62 0.71 0.87 402.73 433.65 116.76 2354.20 547.86 3072 3.60 0.52 0.42 1.90 0.48 0.01 0.56 0.01 0.64 0.01 0.47 0.01 0.60 0.01 3.32 3.07 0.65 0.74 0.90 492.70 547.23 140.27 2699.80 736.38 4096 3.65 0.79 0.42 1.99 0.45 0.01 0.56 0.01 0.61 0.01 0.48 0.01 0.57 0.01 3.37 3.10 0.68 0.78 0.93 565.13 651.63 163.82 3045.40 925.16
NOTES: power consumption DPSRAMBW_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-66
Samsung ASIC
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.66 0.99 0.42 0.93 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 0.78 0.01 2.38 2.25 0.48 0.59 0.72 77.53 72.81 24.62 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2.74 0.95 0.42 1.00 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 0.74 0.01 2.46 2.32 0.52 0.62 0.75 126.78 118.83 35.53 893.80 217.72 1024 2.85 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 0.70 0.01 2.57 2.41 0.55 0.64 0.79 179.48 169.23 47.74 1239.40 264.92 2048 3.03 0.89 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 0.67 0.01 2.75 2.59 0.59 0.66 0.82 239.90 229.53 62.54 1585.00 359.32 3072 3.17 0.88 0.42 1.40 0.51 0.01 0.56 0.01 0.70 0.01 0.46 0.01 0.66 0.01 2.89 2.70 0.59 0.67 0.83 310.98 301.65 79.91 2008.60 453.60 4096 3.34 0.85 0.42 1.58 0.50 0.01 0.56 0.01 0.67 0.01 0.47 0.01 0.63 0.01 3.06 2.84 0.62 0.71 0.86 376.81 370.06 94.75 2354.20 547.86 6144 3.64 0.82 0.42 1.90 0.48 0.01 0.56 0.01 0.64 0.01 0.47 0.01 0.60 0.01 3.36 3.11 0.65 0.74 0.89 462.42 464.05 114.57 2699.80 736.38 8192 3.69 0.79 0.42 1.99 0.45 0.01 0.56 0.01 0.61 0.01 0.48 0.01 0.57 0.01 3.41 3.14 0.68 0.78 0.92 529.95 544.39 134.39 3045.40 925.16
NOTES: power consumption DPSRAMBW_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-67
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tckl tckh tbws tbwh tacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 2.74 0.99 0.42 0.92 0.51 0.01 0.56 0.01 0.81 0.01 0.44 0.01 0.78 0.01 2.45 2.33 0.48 0.60 0.72 76.63 70.72 23.25 548.20 194.12 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 1024 2.81 0.96 0.42 0.99 0.51 0.01 0.56 0.01 0.77 0.01 0.45 0.01 0.74 0.01 2.53 2.39 0.52 0.62 0.75 123.28 11.67. 32.10 893.80 217.72 2048 2.92 0.92 0.42 1.10 0.51 0.01 0.56 0.01 0.74 0.01 0.46 0.01 0.70 0.01 2.64 2.49 0.55 0.64 0.79 173.38 156.66 42.24 1239.40 264.92 4096 3.11 0.89 0.42 1.28 0.52 0.01 0.56 0.01 0.70 0.01 0.46 0.01 0.67 0.01 2.83 2.66 0.59 0.66 0.82 231.14 210.75 54.98 1585.00 359.32 6144 3.25 0.88 0.42 1.41 0.51 0.01 0.56 0.01 0.69 0.01 0.46 0.01 0.66 0.01 2.97 2.77 0.60 0.66 0.84 300.68 277.15 70.80 2008.60 453.60 8192 3.42 0.86 0.42 1.58 0.50 0.01 0.56 0.01 0.68 0.01 0.47 0.01 0.63 0.01 3.14 2.91 0.62 0.70 0.87 364.00 338.40 83.75 2354.20 547.86 12288 3.72 0.84 0.42 1.90 0.48 0.01 0.56 0.01 0.66 0.01 0.48 0.01 0.60 0.01 3.44 3.18 0.65 0.74 0.89 447.32 422.26 101.71 2699.80 736.38 16384 3.77 0.82 0.42 1.99 0.45 0.01 0.56 0.01 0.64 0.01 0.48 0.01 0.57 0.01 3.49 3.21 0.68 0.78 0.92 512.56 490.22 119.67 3045.40 925.16
NOTES: power consumption DPSRAMBW_HDL, only port measured other port isolated. Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-68
Samsung ASIC
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write Timing Diagrams
Read Cycle
tcyc tacc DOUT[] Valid M[A0] M[A1] M[A2] tckh
(CSN low, low, DI[], BWEN[]= don't care)
Write Cycle
tcyc tbws tbwh BWEN[] DI[] (CSN= low, don't care) tckh
Samsung ASIC
5-69
STDL130
DPSRAMBW_HDL
High-Density Dual-Port Synchronous Static with Bit-Write
Read Cycle with CSN-Controlled
tcyc tckl tacc DOUT[] M[A0] M[A1] tckh
(OEN low, high, DI[], BWEN[] don't care)
OEN-Controlled Output Enable
DOUT[] Hi-Z VALID Hi-Z
(CSN, A[], WEN, DI[], BWEN[] don't care)
Contention Mode
(A1[] A2[])
NOTE: "don't care" means condition that these pins normal operation mode.
STDL130
5-70
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Logic Symbol
sparam_hdl_<w>x<b>m<y>b<ba> [m-1:0] [b-1:0] DOUT [b-1:0]
Features
Suitable high-density application Separated data Asynchronous operation Asynchronous tri-state output Address transition detector Write-enable transition detector Chip-select transition detector Bank-select transition detector Automatic power-down mode available noise output optimization Zero standby current Zero hold time Flexible aspect ratio Dual bank scheme available 512Kbits capacity number words number word
NOTES: Words number words. number bits word. Ymux column types. Banks(ba) number banks. log2w
Function Description
SPARAM_HDL single-port asynchronous static which provided compiler. SPARAM_HDL intended high-density applications. falling edge WEN, write cycle initiated. rising edge WEN, write cycle ended. During write cycle, data DI[] written into memory location specified A[]. read cycle initiated when high low. data DOUT[] become valid after delay whenever transition detected. While standby mode that high, DI[] disabled, data stored memory retained DOUT[] remains stable. When high, DOUT[] placed high-impedance state.
SPARAM_HDL Function Table
Valid Valid Stable Toggle Valid Valid Valid DOUT DOUT(t-1) DOUT(t-1) MEM(A) DOUT(t-1) MEM(A) Comment Unconditional tri-state output De-selected (standby mode) Write cycle starts Write cycle ends Read Cycle starts Write Cycle Read Cycle
Samsung ASIC
5-71
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Parameter Description
SPARAM_HDL compiler that automatically generates symbol, netlist, timing model, power model layout according following parameters; Number words(w), Number word(b), Column mux(y) Number banks(ba). Parameters Words(w) Step Step Bpw(b) Step Ymux 2048 4096 Ymux 4096 8192 Ymux 8192 16384 Ymux 16384 1024 32768
Descriptions
Name Chip Enable Description Chip select input. chip select signal acts memory enable signal selections multiple blocks. When high, memory goes stand-by (power down) mode access memory occur. Conversely, low, read write access occur. When falls, access initiated. Write enable input. write enable signal selects type memory access. high state read access state write access. Upon rising edge WEN, write access completed read access initiated. Output enable input. output enable signal controls output drivers from driven tri-state condition unconditionally. Address input bus. should stable when low. address selects location accessed. When address changes, transition detected internal clock pulse generated. Data input bus. data input written accessed location when low. Data output bus. data output data stored accessed location during read access. Data output driver tri-state logic. When low, driver drives certain value. Otherwise, data output keeps Hi-Z state. During write access, data DOUT predictable. Unit: [SL] 4.2154 4.2154 4.2154 3.3665 DOUT 17.6453
Read/Write Enable
Data Output Enable Address
DOUT
Data Input Data Output
Capacitance
4.4212
NOTE: Each pin's capacitance exactly same regardless available types same bank.
STDL130
5-72
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Block Diagrams
SPARAM_HDL different physical architectures word depth. Optionally, these architectures generated from SPARAM_HDL compiler. dual-bank, bank selected address only activated while other bank idle mode. 1-bank architecture, power ports located edge bottom edge both right- left-sides memory. 2-bank architecture, power ports located top-edge, middle-edge bottom-edge both right- left-sides memory. signal ports only located bottom sides memory regardless architecture.
<1-bank architecture>
Core Core
Word-line Decoder
Word-line Decoder
X-Dec
Y-Dec Sense Amp. DOUT[b/2-1:0] DI[b/2-1:0]
Control Block
Y-Dec Sense Amp. DI[b-1:b/2] DOUT[b-1:b/2]
Driver
Address Clock Buffers A[m-1:0]
Driver
Samsung ASIC
5-73
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static
<2-bank architecture
Word-line Decoder Word-line Decoder Core Core X-Dec
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block
Y-Dec Sense Amp. Y-Dec Sense Amp.
Control Block Word-line Decoder Word-line Decoder
X-Dec
Core
Core
Driver
Address Clock Buffers A[m-1:0]
Driver
DOUT[b/2-1:0]
DI[b/2-1:0]
DI[b-1:b/2]
DOUT[b-1:b/2]
Application Notes
Permitting over-the-cell routing chip-level layout, over-the-cell routing SPARAM_HDL permitted only Metal-5 Metal-6 layers. Incoming power should adjusted guarantee more than voltage drop typical-case current levels. Power stripe should tapped from both sides SPARAM_HDL. Avoiding short transition address SPARAM_HDL, rather than write operation which synchronously performed signal, read operation asynchronously performed whenever address transition occurred. this case, short transition address, called skew, happened, since SPARAM_HDL recognizes short address transition stable address transition perform read operation. that time, while read operation, data stored memory corrupted short transition. prevent such fail, stable address cycle time (tcyc) required. essential requirement recognize valid address transition that least minimum address period should equal greater than tacc (access time). Power reduction during standby mode. standby power measured condition that only disable mode other signals operation mode except that tied low. signals activated while standby mode, power will consumed because input switching activities occurred signal transition. Therefore, reduce unnecessary power consumption, should keep stable signals while standby mode.
STDL130
5-74
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Characteristics
Definition Timing (ns) Symbol Description Symbol Description tcyc Address cycle time Address setup time tcas Address setup time rise Address hold time hold time setup time hold time Data-In setup time Data-In hold time twen pulse width tacc Data access time read cycle twacc Data access time rise De-access time twda De-access time rise DOUT high-Z drive time DOUT drive high-Z time valid output time Definition Power Consumption (µW/MHz) Power_read dynamic average power consumption while read cycle Power_write dynamic average power consumption while write cycle Power_standby standby power consumption while high, other signals normal operations Definition Area (µm) Width physical width X-direction Height physical height Y-direction
Samsung ASIC
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=4 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 3.66 0.01 3.91 0.50 3.91 0.26 0.01 0.10 1.50 2.55 3.66 3.22 0.10 1.25 0.51 0.38 0.50 106.82 147.93 18.19 571.13 203.34 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 3.69 0.01 3.94 0.49 3.94 0.24 0.01 0.10 1.56 2.55 3.69 3.26 0.10 1.30 0.51 0.38 0.50 109.07 150.76 41.98 654.20 337.54 3.74 0.01 4.00 0.58 4.00 0.27 0.01 0.10 1.52 2.58 3.74 3.30 0.10 1.27 0.56 0.42 0.54 145.66 227.36 26.00 768.51 250.50 3.76 0.01 4.01 0.54 4.01 0.23 0.01 0.10 1.59 2.56 3.76 3.33 0.10 1.33 0.55 0.42 0.54 148.34 222.60 60.53 891.77 384.70 3.86 0.01 4.12 0.72 4.12 0.33 0.01 0.10 1.54 2.66 3.86 3.42 0.10 1.29 0.60 0.46 0.58 185.28 337.98 34.38 971.28 344.82 3.85 0.01 4.10 0.63 4.10 0.24 0.01 0.10 1.62 2.60 3.85 3.42 0.10 1.37 0.60 0.60 0.59 188.36 309.98 80.04 1132.03 479.02 3.98 0.01 4.24 0.87 4.24 0.39 0.01 0.10 1.57 2.75 3.98 3.54 0.10 1.32 0.65 0.50 0.63 223.15 470.10 42.76 1166.42 439.14 3.94 0.01 4.20 0.73 4.20 0.26 0.01 0.10 1.66 2.65 3.94 3.51 0.10 1.41 0.65 0.50 0.63 227.58 412.86 99.93 1372.30 573.34
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-76
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=4 Parametersy words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 1024 4.11 0.01 4.36 1.02 4.36 0.45 0.01 0.10 1.60 2.84 4.11 3.67 0.10 1.35 0.69 0.54 0.67 263.49 622.09 50.92 1361.57 533.46 1024 4.04 0.01 4.30 0.83 4.30 0.29 0.01 0.10 1.70 2.71 4.04 3.61 0.10 1.45 0.69 0.54 0.67 267.86 528.36 120.49 1612.56 667.66 1536 4.31 0.01 4.56 1.29 4.56 0.59 0.01 0.10 1.63 3.03 4.31 3.87 0.10 1.38 0.74 0.58 0.71 296.63 828.47 58.85 1556.71 722.10 1536 4.18 0.01 4.44 0.98 4.44 0.35 0.01 0.10 1.75 2.80 4.18 3.75 0.10 1.49 0.74 0.58 0.71 310.22 685.32 142.87 1850.58 856.30 2048 4.50 0.01 4.76 1.56 4.76 0.74 0.01 0.10 1.67 3.22 4.50 4.06 0.10 1.00 0.78 0.62 0.75 325.77 1065.62 66.77 1751.85 910.74 2048 4.32 0.01 4.58 1.13 4.58 0.41 0.01 0.10 1.80 2.90 4.32 3.89 0.10 1.10 0.78 0.62 0.75 354.10 859.10 166.12 2088.61 1044.94 4096 4.69 0.01 4.94 1.58 4.94 0.75 0.01 0.10 1.88 3.33 4.69 4.24 0.10 1.62 0.78 0.62 0.75 340.51 1164.62 188.42 2094.89 1799.50
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-77
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 3.65 0.01 3.90 0.52 3.90 0.30 0.01 0.10 1.47 2.58 3.65 3.21 0.10 1.22 0.48 0.35 0.48 95.23 121.65 12.09 571.13 203.34 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 3.68 0.01 3.93 0.51 3.93 0.27 0.01 0.10 1.54 2.58 3.68 3.24 0.10 1.29 0.49 0.35 0.48 96.02 119.95 25.73 611.32 337.54 3.72 0.01 3.97 0.61 3.97 0.32 0.01 0.10 1.49 2.62 3.72 3.28 0.10 1.24 0.51 0.38 0.51 129.08 182.70 16.13 768.51 250.50 3.74 0.01 3.99 0.56 3.99 0.27 0.01 0.10 1.56 2.60 3.74 3.30 0.10 1.31 0.52 0.38 0.51 129.79 175.16 35.90 827.45 384.70 1024 3.83 0.01 4.08 0.74 4.08 0.39 0.01 0.10 1.51 2.70 3.83 3.39 0.10 1.25 0.55 0.41 0.54 164.71 271.57 21.23 971.28 344.82 1024 3.82 0.01 4.07 0.65 4.07 0.29 0.01 0.10 1.59 2.64 3.82 3.38 0.10 1.34 0.55 0.41 0.54 164.75 244.59 47.12 1046.27 479.02 1536 3.94 0.01 4.20 0.89 4.20 0.45 0.01 0.10 1.53 2.79 3.94 3.50 0.10 1.27 0.58 0.44 0.57 199.12 372.68 25.32 1166.42 439.14 1536 3.90 0.01 4.16 0.75 4.16 0.32 0.01 0.10 1.62 2.68 3.90 3.47 0.10 1.36 0.58 0.44 0.57 199.50 322.40 58.29 1265.10 573.34
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-78
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=8 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 2048 4.06 0.01 4.31 1.04 4.31 0.51 0.01 0.10 1.55 2.89 4.06 3.62 0.10 1.29 0.61 0.47 0.60 234.32 488.66 29.27 1361.57 533.46 2048 3.99 0.01 4.24 0.85 4.24 0.34 0.01 0.10 1.65 2.73 3.99 3.56 0.10 1.39 0.61 0.47 0.60 234.78 408.22 69.55 1483.92 667.66 3072 4.24 0.01 4.50 1.32 4.50 0.65 0.01 0.10 1.57 3.08 4.24 3.80 0.10 1.32 0.64 0.50 0.63 264.26 650.97 34.37 1556.71 722.10 3072 4.12 0.01 4.37 1.00 4.37 0.40 0.01 0.10 1.69 2.83 4.12 3.69 0.10 1.43 0.64 0.50 0.63 271.38 531.84 81.22 1700.50 856.30 4096 4.43 0.01 4.69 1.59 4.69 0.79 0.01 0.10 1.60 3.28 4.43 3.99 0.10 1.35 0.67 0.53 0.66 291.29 840.89 39.79 1751.85 910.74 4096 4.25 0.01 4.50 1.16 4.50 0.46 0.01 0.10 1.72 2.93 4.25 3.82 0.10 1.47 0.67 0.53 0.66 309.51 674.21 94.04 1917.09 1044.94 8192 4.62 0.01 4.87 1.62 4.87 0.79 0.01 0.10 1.80 3.37 4.62 4.17 0.10 1.55 0.67 0.53 0.66 295.06 877.34 107.41 1923.37 1799.50
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-79
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 3.67 0.01 3.92 0.52 3.92 0.31 0.01 0.10 1.49 2.59 3.67 3.24 0.10 1.24 0.48 0.35 0.48 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 3.72 0.01 3.97 0.51 3.97 0.30 0.01 0.10 1.58 2.61 3.72 3.28 0.10 1.33 0.49 0.35 0.48 1024 3.74 0.01 3.99 0.61 3.99 0.34 0.01 0.10 1.42 2.63 3.74 3.30 0.10 1.26 0.51 0.38 0.51 1024 3.78 0.01 4.03 0.56 4.03 0.31 0.01 0.10 1.60 2.63 3.78 3.34 0.10 1.35 .0.52 0.38 0.51 2048 3.85 0.01 4.11 0.74 4.11 0.40 0.01 0.10 1.53 2.72 3.85 3.41 0.10 1.28 .0.55 0.41 0.54 2048 3.86 0.01 4.11 0.65 4.11 0.33 0.01 0.10 1.63 2.67 3.86 3.42 0.10 1.37 0.55 0.41 0.54 3072 3.96 0.01 4.22 0.89 4.22 0.46 0.01 0.10 1.55 2.81 3.96 3.52 0.10 1.30 0.58 0.44 0.57 3072 3.94 0.01 4.20 0.75 4.20 0.35 0.01 0.10 1.66 2.72 3.94 3.51 0.10 1.40 0.58 0.44 0.57 1899 280.80 42.67 1211.50 573.34
90.68 106.78 8.76 571.13 203.34
92.93 112.82 19.72 589.88 337.54
122.69 158.97 11.79 768.51 250.50
123.69 155.07 26.68 795.29 384.70
156.78 235.27 15.08 971.28 344.82
156.05 211.80 34.59 1003.39 479.02
190.58 325.07 18.32 1166.42 439.14
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-80
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=16 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 4096 4.08 0.01 4.33 1.04 4.33 0.52 0.01 0.10 1.57 2.90 4.08 3.64 0.10 0.32 0.61 0.47 0.60 225.16 428.62 21.30 1361.57 533.46 4096 4.03 0.01 4.28 0.85 4.28 0.37 0.01 0.10 1.68 2.76 4.03 3.59 0.10 1.43 0.61 0.47 0.60 223.28 358.10 50.91 1419.60 667.66 6144 4.27 0.01 4.52 1.32 4.52 0.67 0.01 0.10 1.59 3.10 4.27 3.83 0.10 0.34 0.64 0.50 0.63 254.77 552.19 25.24 1556.71 722.10 6144 4.16 0.01 4.41 1.00 4.41 0.43 0.01 0.10 1.72 2.87 4.16 3.72 0.10 1.47 0.64 0.50 0.63 258.89 463.79 58.95 1625.46 856.30 8192 4.45 0.01 4.71 1.59 4.71 0.81 0.01 0.10 1.62 3.30 4.45 4.01 0.10 1.37 0.67 0.53 0.66 281.36 690.33 29.00 1751.85 910.74 8192 4.29 0.01 4.54 1.16 4.54 0.50 0.01 0.10 1.76 2.97 4.29 3.85 0.10 1.51 0.67 0.53 0.66 295.77 583.84 67.59 1831.33 1044.94 16384 4.65 0.01 4.91 1.62 4.91 0.83 0.01 0.10 1.84 3.42 4.65 4.21 0.10 1.59 0.67 0.53 0.66 282.36 739.72 75.63 1837.61 1799.50
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-81
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height 1024 3.71 0.01 3.96 0.51 3.96 0.35 0.01 0.10 1.53 2.63 3.71 3.26 0.10 1.28 0.48 0.35 0.48 88.44 100.27 7.60 571.13 203.34 (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 1024 3.79 0.01 4.04 0.51 4.04 0.37 0.01 0.10 1.65 2.67 3.79 3.34 0.10 1.40 0.49 0.35 0.48 88.88 97.76 16.25 579.16 337.54 2048 3.78 0.01 4.03 0.60 4.03 0.37 0.01 0.10 1.55 2.67 3.78 3.34 0.10 1.30 0.51 0.39 0.51 119.52 147.82 9.62 768.51 250.50 2048 3.85 0.01 4.10 0.56 4.10 0.37 0.01 0.10 1.67 2.69 3.85 3.40 0.10 1.42 0.52 0.38 0.51 119.78 140.25 21.42 779.21 384.70 4096 3.89 0.01 4.14 0.74 4.14 0.44 0.01 0.10 1.57 2.74 3.89 2.45 0.10 1.32 0.55 0.42 0.54 153.29 217.95 11.96 971.28 344.82 4096 3.93 0.01 4.18 0.65 4.18 0.39 0.01 0.10 1.70 2.74 3.93 3.48 0.10 1.44 0.55 0.41 0.54 151.86 194.23 26.96 981.95 479.02 6144 4.00 0.01 4.26 0.89 4.26 0.50 0.01 0.10 1.59 2.84 4.00 3.56 0.10 1.34 0.58 0.45 0.57 185.73 300.78 14.57 1166.42 439.14 6144 4.01 0.01 4.27 0.75 4.27 0.41 0.01 0.10 1.73 2.78 4.01 3.57 0.10 1.47 0.58 0.44 0.57 183.40 254.77 32.46 1184.70 573.34
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
STDL130
5-82
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static Reference Table
Ymux=32 Parameters words Timing (ns) tcyc tcas twen tacc twda twacc Power (µW/MHz) Power_read Power_write Power_standby Area (µm) Width Height (Typical process, 1.8V, 25°C, Output load 10SL, Input slope SA=0.5) 8192 4.12 0.01 4.37 1.04 4.37 0.56 0.01 0.10 1.61 2.94 4.12 3.67 0.10 1.36 0.61 0.47 0.60 217.80 395.81 17.00 1361.57 533.46 8192 4.10 0.01 4.35 0.85 4.35 0.44 0.01 0.10 1.76 2.83 4.10 3.66 0.10 1.50 0.61 0.47 0.60 214.66 322.04 38.10 1387.44 667.66 12288 4.31 0.01 4.56 1.32 4.56 0.70 0.01 0.10 1.63 3.13 4.31 3.86 0.10 1.38 0.64 0.50 0.63 247.43 505.23 19.81 1556.71 722.10 12288 4.23 0.01 4.48 1.00 4.48 0.50 0.01 0.10 1.80 2.93 4.23 3.79 0.10 1.54 0.64 0.50 0.63 249.93 421.41 44.13 1587.94 856.30 16384 4.49 0.01 4.75 1.59 4.75 0.85 0.01 0.10 1.66 3.33 4.49 4.05 0.10 1.41 0.67 0.53 0.66 276.03 626.02 22.61 1751.85 910.74 16384 4.36 0.01 4.61 1.16 4.61 0.57 0.01 0.10 1.83 3.04 4.36 3.92 0.10 1.58 0.67 0.53 0.66 287.72 536.05 50.04 1788.45 1044.94 32768 4.72 0.01 4.98 1.62 4.98 0.91 0.01 0.10 1.91 3.49 4.72 4.27 0.10 1.66 0.67 0.53 0.66 277.74 666.02 57.58 1794.73 1799.50
NOTE: Standby power measured condition that other signals normal operation while disable mode low.
Samsung ASIC
5-83
STDL130
SPARAM_HDL
High-Density Single-Port Asynchronous Static Timing Diagrams
Read Cycle
tcyc DOUT[] M[A0] tacc
M[A1]
M[A2]
M[A3]
(WEN high, low, low, DI[] don't care)
Read Cycle with CSN-Controlled
tcyc tcas tacc DOUT[] Valid M[A0] M[A1] tacc M[A2] (OEN low, high, DI[] don't care) tacc
Basic Write Cycle
tcyc DI[] twen
(CSN low, don't care)
STDL130
5-84
Samsung ASIC
SPARAM_HDL
High-Density Single-Port Asynchronous Static
Write Cycle with CSN-Controlled
tcyc DI[] (OEN don't care) twen
Read-Modified-Write Cycle
tcyc DI[] tacc DOUT[] M[A0] twacc twda M[A2] (CSN low, low) NOTES: When hold time after last address transition satisfied, will toggle response successful read initial contents address When hold time after last address transition satisfied, will unknown state. Address bits allowed change while low. they change, then data more addresses memory array corrupted. tacc twen tcyc tcyc
Controlled Output Enable
DOUT[] Hi-Z VALID Hi-Z
(A[], WEN, DI[], don't care) NOTE: "don't care" means condition that these pins normal operation mode.
Samsung ASIC
STDL130
SPARAMBW_HDL
High-Density Single-Port Asynchronous Static with Bit-Write Logic Symbol
sparambw_hdl_<w>x<b>m<y>b<ba> BWEN [b-1:0] [m-1:0] [b-1:0]
Features
Suitable high-density application Bit-write capability Separated data Asynchronous operation Asynchronous tri-state output Address transition detector Write-enable transition detector Chip-select transition detector Bank-select transition detector Automatic power-down mode available noise output optimization Zero standby current Zero hold time BWEN Flexible aspect ratio Dual bank scheme available 512Kbits capacity number words number word
DOUT [b-1:0]
NOTES: Words number words. number bits word. Ymux column types. Banks(ba) number banks. log2w
Function Description
SPARAMBW_HDL single-port synchronous static with bit-write capability which provided compiler. SPARAMBW_HDL intended high-density applications. Basically, functionality exactly same SPARAM_HDL except bit-write operation which controlled BWEN[], named bit-write enable signal bus. Each BWEN[] enables disable write operation corresponding DI[]. falling edge WEN, write cycle initiated when low. data bytes bits DI[], which their corresponding bit(s) BWEN[] low, written into memory location specified A[]. When bits BWEN[] high, data DI[] written into memory location specified A[]. When b
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