Cell Names Function Descriptions Cell Name AD2_LP AD2D2_LP AD2D4_

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Cell Names Function Descriptions Cell Name AD2_LP AD2D2_LP AD2D4_

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LOGIC CELLS
Cell Names Function Descriptions
Cell Name AD2_LP AD2D2_LP AD2D4_LP AD2D8_LP AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP AD3_LP AD3D2_LP AD3D4_LP AD4_LP AD4D2_LP AD4D4_LP AD5_LP AD5D2_LP AD5D4_LP ND2_LP ND2D2_LP ND2D4_LP ND2D8_LP ND2B_LP ND2BD2_LP ND2BD4_LP ND2BD8_LP ND3_LP ND3D2_LP ND3D4_LP ND3D8_LP ND3B_LP ND3BD2_LP ND3BD4_LP ND3BD8_LP ND4_LP ND4D2_LP ND4D4_LP ND5_LP ND5D2_LP Function Description 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive
Samsung ASIC
STDL130
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name ND5D4_LP ND6_LP ND6D2_LP ND6D4_LP ND8_LP ND8D2_LP ND8D4_LP NR2_LP NR2A_LP NR2D2_LP NR2D4_LP NR2D8_LP NR2B_LP NR2BD2_LP NR2BD4_LP NR2BD8_LP NR3_LP NR3A_LP NR3D2_LP NR3D4_LP NR4_LP NR4D2_LP NR4D4_LP NR5_LP NR5D2_LP NR5D4_LP NR6_LP NR6D2_LP NR6D4_LP NR8_LP NR8D2_LP NR8D4_LP OR2_LP OR2D2_LP OR2D4_LP OR2D8_LP OR2B_LP OR2BD2_LP Function Description 5-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 2-Input with Drive 2-Input with P-Transistor, N-Transistor 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with P-Transistor, N-Transistor 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 6-Input with Drive 6-Input with Drive 6-Input with Drive 8-Input with Drive 8-Input with Drive 8-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive
STDL130
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OR2BD4_LP OR2BD8_LP OR3_LP OR3D2_LP OR3D4_LP OR4_LP OR4D2_LP OR4D4_LP OR5_LP OR5D2_LP OR5D4_LP XN2_LP XN2D2_LP XN2D4_LP XN3_LP XN3D2_LP XN3D4_LP XO2_LP XO2D2_LP XO2D4_LP XO3_LP XO3D2_LP XO3D4_LP AO21_LP AO21D2_LP AO21D4_LP AO211_LP AO211D2_LP AO211D4_LP AO2111_LP AO2111D2_LP AO22_LP AO22D2_LP AO22D4_LP AO22A_LP AO221_LP AO221D2_LP AO221D4_LP Function Description 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 4-NOR with Drive 2-AND into 4-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive
Samsung ASIC
STDL130
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO222_LP AO222D2_LP AO222D4_LP AO222A_LP AO2222_LP AO2222D2_LP AO2222D4_LP AO31_LP AO31D2_LP AO31D4_LP AO311_LP AO3111_LP AO32_LP AO32D2_LP AO321_LP AO322_LP AO33_LP AO331_LP AO332_LP OA21_LP OA21D2_LP OA21D4_LP OA211_LP OA211D2_LP OA211D4_LP OA2111_LP OA2111D2_LP OA22_LP OA22D2_LP OA22D4_LP OA22A_LP OA22D2A_LP OA22D4A_LP OA221_LP OA221D2_LP OA221D4_LP OA222_LP OA222D2_LP Function Description Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Inverting 2-of-3 Majority with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 4-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 4-NAND with Drive 2-OR into 4-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive
STDL130
3-10
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA222D4_LP OA2222_LP OA2222D2_LP OA2222D4_LP OA31_LP OA31D2_LP OA31D4_LP OA311_LP OA3111_LP OA32_LP OA321_LP OA322_LP OA33_LP SCG1_LP SCG1D2_LP SCG2_LP SCG2D2_LP SCG2D4_LP SCG3_LP SCG3D2_LP SCG3D4_LP SCG4_LP SCG4D2_LP SCG4D4_LP SCG5_LP SCG5D2_LP SCG5D4_LP SCG6_LP SCG6D2_LP SCG7_LP SCG7D2_LP SCG8_LP SCG8D2_LP SCG9_LP SCG9D2_LP SCG10_LP SCG10D2_LP SCG11_LP Function Description Three 2-ORs into 3-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 4-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-ORs into 2-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive 2-AND into 2-OR with Drive 2-AND into 2-OR with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-AND into 3-OR with Drive 2-AND into 3-OR with Drive 2-OR into 2-AND with Drive 2-OR into 2-AND with Drive 2-ORs into 2-AND with Drive 2-ORs into 2-AND with Drive 2-NORs into 3-NOR with Drive
Samsung ASIC
3-11
STDL130
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name SCG11D2_LP SCG12_LP SCG12D2_LP SCG12D4_LP SCG13_LP SCG13D2_LP SCG14_LP SCG14D2_LP SCG15_LP SCG15D2_LP SCG16_LP SCG16D2_LP SCG17_LP SCG17D2_LP SCG18_LP SCG18D2_LP SCG19_LP SCG19D2_LP SCG20_LP SCG20D2_LP SCG21_LP SCG21D2_LP SCG22_LP SCG22D2_LP DL1D2_LP DL2D2_LP DL5D2_LP DL10D2_LP IV_LP IVD2_LP IVD3_LP IVD4_LP IVD6_LP IVD8_LP IVD16_LP IVD24_LP IVT_LP IVTD2_LP Function Description 2-NORs into 3-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NOR into 2-NAND with Drive 2-NOR into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 3-NAND with Drive 2-NAND into 3-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-AND into 2-NOR with Drive 2-AND into 2-AND into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 3-NOR with Drive 2-NOR into 3-NOR with Drive 2-NAND into 2-OR into 2-NAND with Drive 2-NAND into 2-OR into 2-NAND with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive 10ns Delay Cell with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive
Samsung ASIC
3-12
STDL130
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name IVTD4_LP IVTD8_LP IVTD16_LP NID_LP NID2_LP NID3_LP NID4_LP NID6_LP NID8_LP NID16_LP NID24_LP NIT_LP NITD2_LP NITD4_LP NITD8_LP NITD16_LP CTSB_LP CTSBD2_LP CTSBD3_LP CTSBD4_LP CTSBD6_LP CTSBD8_LP CTSBD16_LP Function Description Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive Clock Tree Synthesis Buffer with Drive
Samsung ASIC
3-13
STDL130
2-Input with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
AD2_LP Input Load (SL) AD2D2_LP AD2D4_LP AD2D8_LP AD2_LP 1.33 Gate Count AD2D2_LP AD2D4_LP 1.67 2.33 AD2D8_LP 4.33
Switching Characteristics
AD2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.046 0.028*SL 0.038 0.020*SL 0.143 0.014*SL 0.158 0.011*SL 0.044 0.028*SL 0.040 0.020*SL 0.139 0.014*SL 0.167 0.011*SL
Parameter
Delay [ns]
Group3*
0.036 0.029*SL 0.030 0.021*SL 0.145 0.014*SL 0.161 0.011*SL 0.037 0.029*SL 0.031 0.021*SL 0.141 0.014*SL 0.171 0.011*SL
0.106 0.053 0.027*SL 0.080 0.042 0.019*SL 0.167 0.137 0.015*SL 0.177 0.150 0.013*SL 0.105 0.052 0.026*SL 0.081 0.042 0.020*SL 0.164 0.134 0.015*SL 0.187 0.160 0.013*SL *Group3 *Group1 *Group2
AD2D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.055 0.013*SL 0.048 0.010*SL 0.164 0.007*SL 0.178 0.006*SL 0.053 0.014*SL 0.049 0.010*SL 0.160 0.007*SL 0.188 0.006*SL
Group3*
0.043 0.014*SL 0.042 0.010*SL 0.172 0.007*SL 0.189 0.006*SL 0.044 0.014*SL 0.043 0.010*SL 0.167 0.007*SL 0.198 0.006*SL
0.081 0.053 0.014*SL 0.066 0.046 0.010*SL 0.174 0.156 0.009*SL 0.187 0.169 0.009*SL 0.080 0.053 0.014*SL 0.066 0.045 0.011*SL 0.170 0.151 0.009*SL 0.196 0.179 0.009*SL *Group1 *Group2 *Group3
STDL130
3-14
Samsung ASIC
2-Input with 1X/2X/4X/8X Drive Switching Characteristics
AD2D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.065 0.007*SL 0.054 0.005*SL 0.189 0.004*SL 0.190 0.004*SL 0.065 0.007*SL 0.054 0.005*SL 0.184 0.004*SL 0.199 0.004*SL
Parameter
Delay [ns]
Group3*
0.056 0.007*SL 0.049 0.005*SL 0.206 0.003*SL 0.208 0.003*SL 0.057 0.007*SL 0.051 0.005*SL 0.201 0.003*SL 0.216 0.003*SL
0.077 0.062 0.007*SL 0.061 0.048 0.006*SL 0.193 0.181 0.006*SL 0.194 0.183 0.005*SL 0.078 0.064 0.007*SL 0.062 0.050 0.006*SL 0.188 0.176 0.006*SL 0.202 0.192 0.005*SL *Group1 *Group2 *Group3
AD2D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.063 0.003*SL 0.050 0.002*SL 0.182 0.002*SL 0.185 0.002*SL 0.064 0.003*SL 0.052 0.002*SL 0.177 0.002*SL 0.193 0.002*SL
Group3*
0.055 0.004*SL 0.050 0.002*SL 0.201 0.002*SL 0.204 0.001*SL 0.056 0.004*SL 0.050 0.002*SL 0.196 0.002*SL 0.213 0.001*SL
0.069 0.061 0.004*SL 0.054 0.049 0.003*SL 0.184 0.177 0.003*SL 0.186 0.180 0.003*SL 0.070 0.062 0.004*SL 0.055 0.048 0.004*SL 0.179 0.172 0.003*SL 0.195 0.189 0.003*SL *Group3 *Group1 *Group2
Samsung ASIC
3-15
STDL130
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) Gate Count AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP AD2B_LP AD2BD2_LP AD2BD4_LP AD2BD8_LP 2.00 2.33 3.00 4.67
Switching Characteristics
AD2B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.045 0.028*SL 0.039 0.020*SL 0.219 0.013*SL 0.189 0.011*SL 0.045 0.028*SL 0.041 0.020*SL 0.141 0.013*SL 0.166 0.011*SL
Parameter
Delay [ns]
Group3*
0.036 0.028*SL 0.029 0.021*SL 0.221 0.013*SL 0.192 0.011*SL 0.037 0.028*SL 0.030 0.021*SL 0.143 0.013*SL 0.169 0.011*SL
0.104 0.051 0.026*SL 0.079 0.039 0.020*SL 0.243 0.214 0.015*SL 0.208 0.182 0.013*SL 0.104 0.051 0.026*SL 0.081 0.042 0.020*SL 0.165 0.135 0.015*SL 0.186 0.159 0.013*SL *Group1 *Group2 *Group3
STDL130
3-16
Samsung ASIC
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
AD2BD2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.056 0.013*SL 0.047 0.009*SL 0.248 0.007*SL 0.208 0.006*SL 0.058 0.013*SL 0.051 0.009*SL 0.166 0.007*SL 0.190 0.006*SL
Parameter
Delay [ns]
Group3*
0.047 0.014*SL 0.043 0.010*SL 0.256 0.007*SL 0.219 0.006*SL 0.047 0.014*SL 0.045 0.010*SL 0.174 0.007*SL 0.202 0.006*SL
0.083 0.056 0.013*SL 0.065 0.046 0.010*SL 0.258 0.239 0.009*SL 0.216 0.199 0.008*SL 0.084 0.057 0.013*SL 0.067 0.046 0.010*SL 0.176 0.157 0.009*SL 0.198 0.181 0.008*SL *Group1 *Group2 *Group3
AD2BD4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.067 0.007*SL 0.054 0.005*SL 0.266 0.004*SL 0.232 0.003*SL 0.067 0.007*SL 0.055 0.005*SL 0.189 0.004*SL 0.200 0.003*SL
Group3*
0.058 0.007*SL 0.052 0.005*SL 0.284 0.003*SL 0.250 0.003*SL 0.058 0.007*SL 0.052 0.005*SL 0.206 0.003*SL 0.218 0.003*SL
0.077 0.061 0.008*SL 0.061 0.048 0.006*SL 0.270 0.258 0.006*SL 0.235 0.225 0.005*SL 0.079 0.065 0.007*SL 0.062 0.051 0.006*SL 0.193 0.181 0.006*SL 0.203 0.193 0.005*SL *Group3 *Group1 *Group2
AD2BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.064 0.003*SL 0.050 0.002*SL 0.282 0.002*SL 0.234 0.002*SL 0.065 0.003*SL 0.052 0.002*SL 0.181 0.002*SL 0.193 0.002*SL
Group3*
0.057 0.004*SL 0.050 0.002*SL 0.302 0.002*SL 0.254 0.001*SL 0.058 0.004*SL 0.050 0.002*SL 0.201 0.002*SL 0.214 0.001*SL
0.070 0.062 0.004*SL 0.054 0.049 0.003*SL 0.283 0.277 0.003*SL 0.235 0.229 0.003*SL 0.070 0.062 0.004*SL 0.055 0.048 0.004*SL 0.183 0.176 0.003*SL 0.195 0.189 0.003*SL *Group3 *Group1 *Group2
Samsung ASIC
3-17
STDL130
AD3_LP/AD3D2_LP/AD3D4_LP
3-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD3_LP Input Load (SL) AD3D2_LP AD3D4_LP AD3_LP 1.67 Gate Count AD3D2_LP 2.00 AD3D4_LP 2.67
Switching Characteristics
AD3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.062 0.028*SL 0.046 0.019*SL 0.191 0.014*SL 0.178 0.011*SL 0.061 0.028*SL 0.046 0.019*SL 0.193 0.014*SL 0.188 0.011*SL 0.061 0.028*SL 0.047 0.019*SL 0.192 0.014*SL 0.197 0.011*SL
Parameter
Delay [ns]
Group3*
0.047 0.029*SL 0.034 0.020*SL 0.197 0.014*SL 0.184 0.011*SL 0.047 0.029*SL 0.035 0.020*SL 0.200 0.014*SL 0.195 0.011*SL 0.047 0.029*SL 0.036 0.020*SL 0.199 0.014*SL 0.204 0.011*SL
0.119 0.065 0.027*SL 0.085 0.048 0.018*SL 0.212 0.178 0.017*SL 0.195 0.167 0.014*SL 0.119 0.066 0.027*SL 0.086 0.049 0.018*SL 0.215 0.181 0.017*SL 0.205 0.178 0.014*SL 0.119 0.066 0.027*SL 0.085 0.048 0.019*SL 0.214 0.180 0.017*SL 0.214 0.186 0.014*SL *Group1 *Group2 *Group3
AD3D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.070 0.014*SL 0.055 0.010*SL 0.210 0.008*SL 0.200 0.007*SL 0.072 0.014*SL 0.057 0.009*SL 0.212 0.008*SL 0.210 0.007*SL 0.073 0.013*SL 0.058 0.009*SL 0.211 0.008*SL 0.219 0.007*SL
Group3*
0.065 0.014*SL 0.051 0.010*SL 0.226 0.007*SL 0.215 0.006*SL 0.065 0.014*SL 0.052 0.010*SL 0.229 0.007*SL 0.226 0.006*SL 0.064 0.014*SL 0.054 0.010*SL 0.228 0.007*SL 0.235 0.006*SL
0.097 0.069 0.014*SL 0.071 0.050 0.011*SL 0.219 0.197 0.011*SL 0.208 0.189 0.009*SL 0.096 0.067 0.015*SL 0.073 0.052 0.011*SL 0.222 0.200 0.011*SL 0.218 0.199 0.009*SL 0.098 0.069 0.014*SL 0.074 0.051 0.011*SL 0.221 0.199 0.011*SL 0.227 0.208 0.009*SL *Group1 *Group2 *Group3
STDL130
3-18
Samsung ASIC
AD3_LP/AD3D2_LP/AD3D4_LP
3-Input with 1X/2X/4X Drive Switching Characteristics
AD3D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.095 0.007*SL 0.068 0.005*SL 0.276 0.005*SL 0.234 0.004*SL 0.095 0.007*SL 0.069 0.005*SL 0.279 0.005*SL 0.242 0.004*SL 0.094 0.007*SL 0.071 0.005*SL 0.278 0.005*SL 0.250 0.004*SL
Parameter
Delay [ns]
Group3*
0.101 0.007*SL 0.070 0.005*SL 0.311 0.004*SL 0.259 0.003*SL 0.101 0.007*SL 0.071 0.005*SL 0.314 0.004*SL 0.268 0.003*SL 0.102 0.007*SL 0.073 0.005*SL 0.313 0.004*SL 0.276 0.003*SL
0.105 0.086 0.009*SL 0.075 0.062 0.006*SL 0.280 0.265 0.008*SL 0.236 0.224 0.006*SL 0.105 0.086 0.009*SL 0.075 0.061 0.007*SL 0.284 0.268 0.008*SL 0.245 0.232 0.006*SL 0.105 0.088 0.009*SL 0.078 0.065 0.006*SL 0.282 0.267 0.008*SL 0.253 0.240 0.006*SL *Group3 *Group1 *Group2
Samsung ASIC
3-19
STDL130
AD4_LP/AD4D2_LP/AD4D4_LP
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
AD4_LP AD4_LP 2.00 Input Load (SL) AD4D2_LP Gate Count AD4D2_LP 2.33 AD4D4_LP AD4D4_LP 3.00
Switching Characteristics
AD4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.076 0.027*SL 0.046 0.019*SL 0.223 0.014*SL 0.186 0.011*SL 0.076 0.027*SL 0.048 0.019*SL 0.232 0.014*SL 0.198 0.011*SL 0.076 0.027*SL 0.052 0.019*SL 0.238 0.014*SL 0.208 0.011*SL 0.076 0.027*SL 0.053 0.019*SL 0.240 0.014*SL 0.215 0.012*SL
Parameter
Delay [ns]
Group3*
0.061 0.028*SL 0.037 0.020*SL 0.237 0.014*SL 0.194 0.011*SL 0.061 0.028*SL 0.037 0.020*SL 0.247 0.014*SL 0.206 0.011*SL 0.061 0.028*SL 0.040 0.020*SL 0.252 0.014*SL 0.217 0.011*SL 0.061 0.028*SL 0.041 0.020*SL 0.254 0.014*SL 0.225 0.011*SL
0.131 0.076 0.028*SL 0.085 0.048 0.019*SL 0.243 0.205 0.019*SL 0.203 0.175 0.014*SL 0.131 0.075 0.028*SL 0.086 0.049 0.019*SL 0.252 0.214 0.019*SL 0.214 0.186 0.014*SL 0.131 0.076 0.028*SL 0.089 0.052 0.019*SL 0.258 0.220 0.019*SL 0.224 0.195 0.014*SL 0.131 0.076 0.028*SL 0.090 0.052 0.019*SL 0.259 0.222 0.019*SL 0.232 0.202 0.015*SL *Group1 *Group2 *Group3
STDL130
3-20
Samsung ASIC
AD4_LP/AD4D2_LP/AD4D4_LP
4-Input with 1X/2X/4X Drive Switching Characteristics
AD4D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.079 0.014*SL 0.052 0.010*SL 0.225 0.008*SL 0.190 0.007*SL 0.079 0.014*SL 0.052 0.010*SL 0.234 0.008*SL 0.201 0.007*SL 0.079 0.014*SL 0.055 0.009*SL 0.240 0.008*SL 0.211 0.007*SL 0.079 0.014*SL 0.056 0.009*SL 0.242 0.008*SL 0.219 0.007*SL
Parameter
Delay [ns]
Group3*
0.076 0.014*SL 0.047 0.010*SL 0.247 0.007*SL 0.204 0.006*SL 0.076 0.014*SL 0.048 0.010*SL 0.256 0.007*SL 0.216 0.006*SL 0.076 0.014*SL 0.050 0.010*SL 0.262 0.007*SL 0.226 0.006*SL 0.076 0.014*SL 0.052 0.010*SL 0.264 0.007*SL 0.234 0.006*SL
0.102 0.071 0.016*SL 0.068 0.046 0.011*SL 0.235 0.211 0.012*SL 0.198 0.180 0.009*SL 0.103 0.073 0.015*SL 0.070 0.049 0.010*SL 0.244 0.220 0.012*SL 0.209 0.191 0.009*SL 0.102 0.071 0.016*SL 0.071 0.050 0.011*SL 0.249 0.226 0.012*SL 0.219 0.200 0.009*SL 0.102 0.071 0.016*SL 0.072 0.050 0.011*SL 0.251 0.227 0.012*SL 0.227 0.208 0.009*SL *Group1 *Group2 *Group3
AD4D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.097 0.007*SL 0.066 0.005*SL 0.281 0.005*SL 0.230 0.004*SL 0.097 0.007*SL 0.068 0.005*SL 0.290 0.005*SL 0.241 0.004*SL 0.097 0.007*SL 0.070 0.005*SL 0.296 0.005*SL 0.251 0.004*SL 0.097 0.007*SL 0.071 0.005*SL 0.298 0.005*SL 0.259 0.004*SL
Group3*
0.108 0.007*SL 0.069 0.005*SL 0.318 0.004*SL 0.255 0.003*SL 0.108 0.007*SL 0.070 0.005*SL 0.327 0.004*SL 0.267 0.003*SL 0.108 0.007*SL 0.072 0.005*SL 0.333 0.004*SL 0.277 0.003*SL 0.108 0.007*SL 0.073 0.005*SL 0.335 0.004*SL 0.286 0.003*SL
0.107 0.089 0.009*SL 0.073 0.061 0.006*SL 0.285 0.269 0.008*SL 0.233 0.221 0.006*SL 0.107 0.087 0.010*SL 0.074 0.060 0.007*SL 0.294 0.279 0.008*SL 0.244 0.232 0.006*SL 0.107 0.089 0.009*SL 0.077 0.064 0.006*SL 0.300 0.285 0.008*SL 0.254 0.241 0.006*SL 0.107 0.089 0.009*SL 0.078 0.064 0.007*SL 0.302 0.287 0.008*SL 0.262 0.250 0.006*SL *Group1 *Group2 *Group3
Samsung ASIC
3-21
STDL130
AD5_LP/AD5D2_LP/AD5D4_LP
5-Input with 1X/2X/4XDrive Logic Symbol
Truth Table
Cell Data
AD5_LP AD5_LP 3.00 Input Load (SL) AD5D2_LP Gate Count AD5D2_LP 3.33 AD5D4_LP AD5D4_LP 5.00
Switching Characteristics
AD5_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.099 0.057*SL 0.054 0.019*SL 0.198 0.028*SL 0.203 0.011*SL 0.099 0.057*SL 0.056 0.019*SL 0.201 0.028*SL 0.216 0.011*SL 0.099 0.057*SL 0.059 0.019*SL 0.201 0.028*SL 0.229 0.012*SL 0.092 0.057*SL 0.064 0.019*SL 0.186 0.028*SL 0.196 0.011*SL 0.092 0.057*SL 0.065 0.019*SL 0.183 0.028*SL 0.209 0.011*SL
Parameter
Delay [ns]
Group3*
0.090 0.057*SL 0.045 0.020*SL 0.201 0.028*SL 0.212 0.011*SL 0.090 0.057*SL 0.046 0.020*SL 0.204 0.028*SL 0.226 0.011*SL 0.090 0.057*SL 0.047 0.020*SL 0.204 0.028*SL 0.239 0.011*SL 0.089 0.057*SL 0.053 0.020*SL 0.188 0.028*SL 0.202 0.011*SL 0.089 0.057*SL 0.054 0.020*SL 0.185 0.028*SL 0.215 0.011*SL
0.216 0.106 0.055*SL 0.092 0.054 0.019*SL 0.252 0.193 0.029*SL 0.220 0.191 0.014*SL 0.216 0.106 0.055*SL 0.094 0.055 0.019*SL 0.255 0.196 0.029*SL 0.233 0.204 0.014*SL 0.216 0.106 0.055*SL 0.097 0.060 0.019*SL 0.254 0.196 0.029*SL 0.245 0.216 0.015*SL 0.208 0.094 0.057*SL 0.103 0.065 0.019*SL 0.241 0.184 0.029*SL 0.214 0.188 0.013*SL 0.208 0.095 0.057*SL 0.104 0.067 0.019*SL 0.237 0.180 0.029*SL 0.228 0.201 0.013*SL *Group3 *Group1 *Group2
STDL130
3-22
Samsung ASIC
AD5_LP/AD5D2_LP/AD5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.100 0.028*SL 0.057 0.010*SL 0.215 0.014*SL 0.202 0.007*SL 0.100 0.028*SL 0.058 0.010*SL 0.218 0.014*SL 0.213 0.007*SL 0.101 0.028*SL 0.060 0.010*SL 0.217 0.014*SL 0.223 0.007*SL 0.088 0.029*SL 0.071 0.010*SL 0.208 0.014*SL 0.209 0.006*SL 0.088 0.029*SL 0.069 0.010*SL 0.203 0.014*SL 0.220 0.006*SL
Group3*
0.090 0.029*SL 0.053 0.010*SL 0.220 0.014*SL 0.215 0.006*SL 0.090 0.029*SL 0.053 0.010*SL 0.223 0.014*SL 0.227 0.006*SL 0.090 0.029*SL 0.056 0.010*SL 0.222 0.014*SL 0.237 0.006*SL 0.084 0.029*SL 0.064 0.010*SL 0.211 0.014*SL 0.219 0.006*SL 0.084 0.029*SL 0.066 0.010*SL 0.207 0.014*SL 0.231 0.006*SL
0.157 0.103 0.027*SL 0.075 0.054 0.010*SL 0.240 0.207 0.016*SL 0.210 0.192 0.009*SL 0.157 0.103 0.027*SL 0.075 0.054 0.011*SL 0.243 0.210 0.016*SL 0.221 0.203 0.009*SL 0.158 0.103 0.027*SL 0.078 0.057 0.010*SL 0.242 0.209 0.016*SL 0.231 0.213 0.009*SL 0.145 0.089 0.028*SL 0.089 0.068 0.010*SL 0.233 0.203 0.015*SL 0.218 0.202 0.008*SL 0.145 0.089 0.028*SL 0.089 0.069 0.010*SL 0.229 0.198 0.015*SL 0.230 0.214 0.008*SL *Group1 *Group2 *Group3
Samsung ASIC
3-23
STDL130
AD5_LP/AD5D2_LP/AD5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.056 0.006*SL 0.053 0.005*SL 0.417 0.004*SL 0.329 0.003*SL 0.057 0.006*SL 0.049 0.005*SL 0.419 0.004*SL 0.337 0.003*SL 0.055 0.007*SL 0.051 0.005*SL 0.418 0.004*SL 0.344 0.003*SL 0.057 0.006*SL 0.053 0.005*SL 0.393 0.004*SL 0.327 0.003*SL 0.057 0.006*SL 0.053 0.005*SL 0.388 0.004*SL 0.337 0.003*SL
Parameter
Delay [ns]
Group3*
0.043 0.007*SL 0.048 0.005*SL 0.425 0.003*SL 0.345 0.003*SL 0.043 0.007*SL 0.049 0.005*SL 0.428 0.003*SL 0.353 0.003*SL 0.044 0.007*SL 0.047 0.005*SL 0.427 0.003*SL 0.360 0.003*SL 0.043 0.007*SL 0.049 0.005*SL 0.402 0.003*SL 0.343 0.003*SL 0.043 0.007*SL 0.048 0.005*SL 0.397 0.003*SL 0.353 0.003*SL
0.070 0.058 0.006*SL 0.060 0.048 0.006*SL 0.421 0.410 0.005*SL 0.332 0.322 0.005*SL 0.069 0.055 0.007*SL 0.059 0.048 0.005*SL 0.423 0.413 0.005*SL 0.340 0.330 0.005*SL 0.069 0.057 0.006*SL 0.059 0.049 0.005*SL 0.422 0.412 0.005*SL 0.348 0.338 0.005*SL 0.069 0.056 0.007*SL 0.060 0.048 0.006*SL 0.397 0.387 0.005*SL 0.331 0.320 0.005*SL 0.068 0.054 0.007*SL 0.060 0.048 0.006*SL 0.393 0.382 0.005*SL 0.341 0.331 0.005*SL *Group1 *Group2 *Group3
STDL130
3-24
Samsung ASIC
2-Input NAND with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
ND2_LP Input Load (SL) ND2D2_LP ND2D4_LP ND2D8_LP ND2_LP 1.00 Gate Count ND2D2_LP ND2D4_LP ND2D8_LP 1.67 3.00 4.33
Switching Characteristics
ND2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.068 0.027*SL 0.068 0.026*SL 0.088 0.014*SL 0.076 0.015*SL 0.076 0.028*SL 0.059 0.027*SL 0.095 0.014*SL 0.072 0.015*SL
Parameter
Delay [ns]
Group3*
0.045 0.029*SL 0.045 0.028*SL 0.088 0.014*SL 0.077 0.015*SL 0.054 0.029*SL 0.045 0.028*SL 0.096 0.014*SL 0.073 0.015*SL
0.131 0.084 0.024*SL 0.127 0.080 0.024*SL 0.111 0.080 0.015*SL 0.101 0.067 0.017*SL 0.137 0.088 0.024*SL 0.116 0.066 0.025*SL 0.120 0.091 0.015*SL 0.097 0.064 0.017*SL *Group3 *Group1 *Group2
ND2D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.076 0.013*SL 0.074 0.012*SL 0.084 0.007*SL 0.071 0.008*SL 0.084 0.013*SL 0.063 0.013*SL 0.093 0.007*SL 0.067 0.008*SL
Group3*
0.057 0.014*SL 0.058 0.014*SL 0.087 0.007*SL 0.076 0.007*SL 0.065 0.014*SL 0.051 0.014*SL 0.094 0.007*SL 0.071 0.007*SL
0.106 0.084 0.011*SL 0.101 0.077 0.012*SL 0.093 0.074 0.010*SL 0.081 0.061 0.010*SL 0.112 0.089 0.012*SL 0.090 0.065 0.013*SL 0.103 0.086 0.009*SL 0.078 0.060 0.009*SL *Group1 *Group2 *Group3
Samsung ASIC
3-25
STDL130
2-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
ND2D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.082 0.006*SL 0.078 0.006*SL 0.079 0.004*SL 0.067 0.004*SL 0.086 0.006*SL 0.064 0.006*SL 0.091 0.004*SL 0.064 0.004*SL
Parameter
Delay [ns]
Group3*
0.061 0.007*SL 0.060 0.007*SL 0.087 0.003*SL 0.076 0.004*SL 0.068 0.007*SL 0.054 0.007*SL 0.095 0.003*SL 0.072 0.004*SL
0.096 0.085 0.006*SL 0.088 0.075 0.007*SL 0.083 0.072 0.005*SL 0.071 0.060 0.006*SL 0.100 0.089 0.006*SL 0.078 0.066 0.006*SL 0.095 0.085 0.005*SL 0.069 0.059 0.005*SL *Group1 *Group2 *Group3
ND2D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.051 0.003*SL 0.048 0.002*SL 0.248 0.002*SL 0.255 0.002*SL 0.053 0.003*SL 0.049 0.002*SL 0.257 0.002*SL 0.250 0.002*SL
Group3*
0.040 0.004*SL 0.046 0.003*SL 0.259 0.002*SL 0.273 0.001*SL 0.039 0.004*SL 0.046 0.003*SL 0.268 0.002*SL 0.267 0.001*SL
0.057 0.051 0.003*SL 0.053 0.048 0.002*SL 0.250 0.245 0.003*SL 0.256 0.251 0.003*SL 0.057 0.049 0.004*SL 0.053 0.047 0.003*SL 0.259 0.254 0.003*SL 0.251 0.246 0.003*SL *Group1 *Group2 *Group3
STDL130
3-26
Samsung ASIC
2-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
ND2B_LP Input Load (SL) Gate Count ND2BD2_LP ND2BD4_LP ND2BD8_LP ND2B_LP ND2BD2_LP ND2BD4_LP ND2BD8_LP 1.67 2.33 3.33 5.00
Switching Characteristics
ND2B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.054 0.028*SL 0.055 0.028*SL 0.142 0.013*SL 0.152 0.015*SL 0.079 0.027*SL 0.064 0.027*SL 0.097 0.013*SL 0.075 0.015*SL
Parameter
Delay [ns]
Group3*
0.048 0.028*SL 0.049 0.028*SL 0.143 0.013*SL 0.154 0.015*SL 0.058 0.028*SL 0.051 0.028*SL 0.097 0.013*SL 0.077 0.015*SL
0.117 0.067 0.025*SL 0.112 0.059 0.027*SL 0.168 0.140 0.014*SL 0.180 0.149 0.016*SL 0.139 0.090 0.024*SL 0.122 0.071 0.025*SL 0.121 0.093 0.014*SL 0.101 0.068 0.017*SL *Group1 *Group2 *Group3
Samsung ASIC
3-27
STDL130
2-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND2BD2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.056 0.014*SL 0.059 0.014*SL 0.153 0.007*SL 0.168 0.008*SL 0.085 0.013*SL 0.065 0.014*SL 0.093 0.007*SL 0.069 0.008*SL
Parameter
Delay [ns]
Group3*
0.049 0.014*SL 0.052 0.014*SL 0.156 0.007*SL 0.172 0.008*SL 0.066 0.014*SL 0.056 0.014*SL 0.094 0.007*SL 0.075 0.008*SL
0.085 0.059 0.013*SL 0.086 0.057 0.014*SL 0.165 0.150 0.008*SL 0.181 0.164 0.009*SL 0.113 0.090 0.011*SL 0.093 0.065 0.014*SL 0.103 0.085 0.009*SL 0.082 0.062 0.010*SL *Group1 *Group2 *Group3
ND2BD4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.072 0.007*SL 0.071 0.007*SL 0.187 0.004*SL 0.204 0.004*SL 0.088 0.006*SL 0.067 0.007*SL 0.090 0.004*SL 0.065 0.004*SL
Group3*
0.061 0.007*SL 0.064 0.007*SL 0.195 0.003*SL 0.215 0.004*SL 0.069 0.007*SL 0.061 0.007*SL 0.094 0.003*SL 0.075 0.004*SL
0.086 0.073 0.007*SL 0.084 0.071 0.007*SL 0.192 0.183 0.005*SL 0.210 0.200 0.005*SL 0.102 0.091 0.005*SL 0.081 0.067 0.007*SL 0.094 0.084 0.005*SL 0.071 0.060 0.005*SL *Group1 *Group2 *Group3
ND2BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.052 0.003*SL 0.048 0.002*SL 0.300 0.002*SL 0.330 0.002*SL 0.053 0.003*SL 0.048 0.002*SL 0.259 0.002*SL 0.252 0.002*SL
Group3*
0.040 0.004*SL 0.046 0.002*SL 0.311 0.002*SL 0.347 0.001*SL 0.040 0.004*SL 0.046 0.002*SL 0.269 0.002*SL 0.270 0.001*SL
0.059 0.053 0.003*SL 0.053 0.048 0.003*SL 0.302 0.297 0.003*SL 0.331 0.325 0.003*SL 0.058 0.051 0.004*SL 0.053 0.047 0.003*SL 0.261 0.255 0.003*SL 0.253 0.248 0.003*SL *Group1 *Group2 *Group3
STDL130
3-28
Samsung ASIC
3-Input NAND with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
ND3_LP ND3_LP 1.33 Input Load (SL) ND3D2_LP ND3D4_LP Gate Count ND3D2_LP ND3D4_LP 2.33 3.00 ND3D8_LP ND3D8_LP 4.67
Samsung ASIC
3-29
STDL130
3-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
ND3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.085 0.035*SL 0.093 0.039*SL 0.099 0.017*SL 0.089 0.021*SL 0.094 0.035*SL 0.089 0.040*SL 0.109 0.017*SL 0.092 0.021*SL 0.104 0.035*SL 0.085 0.040*SL 0.117 0.017*SL 0.092 0.021*SL
Parameter
Delay [ns]
Group3*
0.066 0.036*SL 0.077 0.040*SL 0.100 0.017*SL 0.090 0.021*SL 0.077 0.036*SL 0.077 0.040*SL 0.110 0.017*SL 0.094 0.021*SL 0.088 0.036*SL 0.078 0.040*SL 0.119 0.017*SL 0.094 0.021*SL
0.163 0.100 0.032*SL 0.179 0.106 0.036*SL 0.132 0.097 0.018*SL 0.130 0.087 0.021*SL 0.171 0.106 0.032*SL 0.173 0.098 0.037*SL 0.143 0.108 0.017*SL 0.132 0.089 0.022*SL 0.180 0.115 0.033*SL 0.168 0.091 0.038*SL 0.151 0.116 0.017*SL 0.133 0.090 0.021*SL *Group3 *Group1 *Group2
ND3D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.087 0.017*SL 0.094 0.018*SL 0.095 0.009*SL 0.084 0.010*SL 0.094 0.017*SL 0.086 0.019*SL 0.105 0.009*SL 0.086 0.010*SL 0.104 0.017*SL 0.080 0.019*SL 0.112 0.009*SL 0.085 0.010*SL
Group3*
0.069 0.018*SL 0.076 0.019*SL 0.096 0.009*SL 0.084 0.010*SL 0.079 0.018*SL 0.075 0.020*SL 0.106 0.009*SL 0.087 0.010*SL 0.089 0.018*SL 0.073 0.020*SL 0.114 0.009*SL 0.086 0.010*SL
0.124 0.094 0.015*SL 0.134 0.101 0.017*SL 0.109 0.089 0.010*SL 0.101 0.077 0.012*SL 0.132 0.103 0.015*SL 0.126 0.091 0.018*SL 0.121 0.102 0.009*SL 0.103 0.080 0.012*SL 0.142 0.111 0.015*SL 0.120 0.083 0.018*SL 0.129 0.111 0.009*SL 0.103 0.081 0.011*SL *Group1 *Group2 *Group3
STDL130
3-30
Samsung ASIC
3-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
ND3D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.048 0.007*SL 0.062 0.005*SL 0.267 0.004*SL 0.281 0.004*SL 0.047 0.007*SL 0.062 0.005*SL 0.286 0.004*SL 0.284 0.004*SL 0.049 0.007*SL 0.062 0.005*SL 0.302 0.004*SL 0.284 0.004*SL
Parameter
Delay [ns]
Group3*
0.037 0.007*SL 0.060 0.005*SL 0.273 0.003*SL 0.302 0.003*SL 0.036 0.007*SL 0.059 0.005*SL 0.292 0.003*SL 0.306 0.003*SL 0.037 0.007*SL 0.060 0.005*SL 0.309 0.003*SL 0.305 0.003*SL
0.062 0.048 0.007*SL 0.069 0.056 0.006*SL 0.272 0.262 0.005*SL 0.284 0.272 0.006*SL 0.063 0.052 0.006*SL 0.069 0.057 0.006*SL 0.290 0.281 0.005*SL 0.288 0.276 0.006*SL 0.062 0.049 0.007*SL 0.069 0.056 0.006*SL 0.307 0.297 0.005*SL 0.287 0.275 0.006*SL *Group3 *Group1 *Group2
ND3D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.053 0.003*SL 0.052 0.002*SL 0.278 0.002*SL 0.298 0.002*SL 0.054 0.003*SL 0.052 0.002*SL 0.289 0.002*SL 0.301 0.002*SL 0.052 0.003*SL 0.052 0.002*SL 0.299 0.002*SL 0.300 0.002*SL
Group3*
0.041 0.004*SL 0.048 0.003*SL 0.288 0.002*SL 0.316 0.001*SL 0.041 0.004*SL 0.048 0.002*SL 0.300 0.002*SL 0.319 0.001*SL 0.041 0.004*SL 0.048 0.003*SL 0.309 0.002*SL 0.318 0.001*SL
0.060 0.054 0.003*SL 0.055 0.049 0.003*SL 0.280 0.274 0.003*SL 0.299 0.294 0.003*SL 0.061 0.054 0.003*SL 0.055 0.048 0.003*SL 0.291 0.285 0.003*SL 0.302 0.297 0.003*SL 0.059 0.052 0.003*SL 0.055 0.049 0.003*SL 0.301 0.295 0.003*SL 0.301 0.295 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-31
STDL130
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Other Stares
Cell Data
ND3B_LP ND3B_LP 2.00 Input Load (SL) ND3BD2_LP ND3BD4_LP Gate Count ND3BD2_LP ND3BD4_LP 2.67 3.67 ND3BD8_LP ND3BD8_LP 5.33
STDL130
3-32
Samsung ASIC
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND3B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay [ns] Delay Equations [ns] Group1* Group2*
0.073 0.036*SL 0.083 0.039*SL 0.149 0.017*SL 0.152 0.020*SL 0.098 0.035*SL 0.092 0.039*SL 0.111 0.017*SL 0.095 0.020*SL 0.109 0.035*SL 0.089 0.039*SL 0.120 0.017*SL 0.095 0.020*SL
Parameter
Group3*
0.071 0.036*SL 0.081 0.039*SL 0.150 0.017*SL 0.153 0.020*SL 0.081 0.036*SL 0.081 0.039*SL 0.112 0.017*SL 0.097 0.020*SL 0.093 0.036*SL 0.081 0.039*SL 0.121 0.017*SL 0.097 0.020*SL
0.149 0.078 0.035*SL 0.163 0.086 0.039*SL 0.183 0.148 0.017*SL 0.192 0.150 0.021*SL 0.175 0.111 0.032*SL 0.174 0.101 0.037*SL 0.145 0.110 0.017*SL 0.134 0.092 0.021*SL 0.185 0.119 0.033*SL 0.169 0.093 0.038*SL 0.153 0.118 0.017*SL 0.135 0.093 0.021*SL *Group1 *Group2 *Group3
ND3BD2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.075 0.018*SL 0.078 0.019*SL 0.171 0.009*SL 0.167 0.010*SL 0.097 0.017*SL 0.088 0.019*SL 0.105 0.009*SL 0.088 0.010*SL 0.105 0.017*SL 0.082 0.019*SL 0.113 0.009*SL 0.087 0.010*SL
Group3*
0.066 0.018*SL 0.074 0.020*SL 0.173 0.009*SL 0.169 0.010*SL 0.080 0.018*SL 0.079 0.020*SL 0.106 0.009*SL 0.090 0.010*SL 0.090 0.018*SL 0.076 0.020*SL 0.115 0.009*SL 0.090 0.010*SL
0.112 0.078 0.017*SL 0.118 0.080 0.019*SL 0.187 0.168 0.009*SL 0.187 0.165 0.011*SL 0.133 0.102 0.016*SL 0.128 0.093 0.018*SL 0.121 0.103 0.009*SL 0.106 0.082 0.012*SL 0.143 0.113 0.015*SL 0.122 0.085 0.019*SL 0.130 0.112 0.009*SL 0.106 0.083 0.011*SL *Group1 *Group2 *Group3
Samsung ASIC
3-33
STDL130
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND3BD4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.045 0.007*SL 0.062 0.005*SL 0.300 0.004*SL 0.332 0.004*SL 0.048 0.007*SL 0.062 0.005*SL 0.277 0.004*SL 0.280 0.004*SL 0.048 0.007*SL 0.062 0.005*SL 0.293 0.004*SL 0.279 0.004*SL
Parameter
Delay [ns]
Group3*
0.035 0.007*SL 0.061 0.005*SL 0.306 0.003*SL 0.353 0.003*SL 0.036 0.007*SL 0.060 0.005*SL 0.283 0.003*SL 0.301 0.003*SL 0.036 0.007*SL 0.060 0.005*SL 0.300 0.003*SL 0.300 0.003*SL
0.060 0.047 0.006*SL 0.069 0.058 0.006*SL 0.305 0.295 0.005*SL 0.335 0.323 0.006*SL 0.060 0.046 0.007*SL 0.069 0.056 0.006*SL 0.281 0.272 0.005*SL 0.283 0.271 0.006*SL 0.061 0.047 0.007*SL 0.069 0.056 0.006*SL 0.298 0.288 0.005*SL 0.282 0.271 0.006*SL *Group3 *Group1 *Group2
ND3BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.053 0.003*SL 0.052 0.002*SL 0.341 0.002*SL 0.370 0.002*SL 0.054 0.003*SL 0.052 0.002*SL 0.294 0.002*SL 0.306 0.002*SL 0.054 0.003*SL 0.051 0.002*SL 0.304 0.002*SL 0.306 0.002*SL
Group3*
0.042 0.004*SL 0.048 0.002*SL 0.352 0.002*SL 0.388 0.001*SL 0.042 0.004*SL 0.048 0.002*SL 0.304 0.002*SL 0.324 0.001*SL 0.040 0.004*SL 0.049 0.002*SL 0.315 0.002*SL 0.324 0.001*SL
0.060 0.053 0.003*SL 0.055 0.049 0.003*SL 0.343 0.337 0.003*SL 0.372 0.366 0.003*SL 0.061 0.055 0.003*SL 0.056 0.049 0.003*SL 0.296 0.290 0.003*SL 0.307 0.302 0.003*SL 0.060 0.052 0.004*SL 0.055 0.049 0.003*SL 0.306 0.300 0.003*SL 0.307 0.302 0.003*SL *Group1 *Group2 *Group3
STDL130
3-34
Samsung ASIC
ND4_LP/ND4D2_LP/ND4D4_LP
4-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
ND4_LP ND4_LP 1.67 Input Load (SL) ND4D2_LP Gate Count ND4D2_LP 3.00 ND4D4_LP ND4D4_LP 3.33
Switching Characteristics
ND4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.093 0.046*SL 0.111 0.051*SL 0.107 0.022*SL 0.091 0.026*SL 0.107 0.046*SL 0.109 0.051*SL 0.121 0.022*SL 0.102 0.026*SL 0.121 0.046*SL 0.107 0.051*SL 0.133 0.022*SL 0.108 0.026*SL 0.135 0.046*SL 0.105 0.051*SL 0.142 0.022*SL 0.111 0.026*SL
Parameter
Delay [ns]
Group3*
0.081 0.047*SL 0.101 0.051*SL 0.108 0.022*SL 0.092 0.026*SL 0.096 0.047*SL 0.101 0.051*SL 0.122 0.022*SL 0.103 0.026*SL 0.111 0.047*SL 0.101 0.051*SL 0.135 0.022*SL 0.110 0.026*SL 0.126 0.047*SL 0.101 0.051*SL 0.146 0.022*SL 0.113 0.026*SL
0.193 0.107 0.043*SL 0.219 0.123 0.048*SL 0.151 0.106 0.022*SL 0.143 0.091 0.026*SL 0.206 0.119 0.043*SL 0.215 0.118 0.049*SL 0.164 0.120 0.022*SL 0.153 0.100 0.027*SL 0.219 0.132 0.044*SL 0.212 0.113 0.049*SL 0.176 0.131 0.023*SL 0.160 0.107 0.027*SL 0.232 0.144 0.044*SL 0.209 0.109 0.050*SL 0.185 0.139 0.023*SL 0.163 0.110 0.027*SL *Group1 *Group2 *Group3
Samsung ASIC
3-35
STDL130
ND4_LP/ND4D2_LP/ND4D4_LP
4-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND4D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.100 0.022*SL 0.117 0.025*SL 0.105 0.011*SL 0.089 0.013*SL 0.113 0.022*SL 0.111 0.025*SL 0.119 0.011*SL 0.100 0.013*SL 0.125 0.023*SL 0.107 0.025*SL 0.130 0.011*SL 0.106 0.013*SL 0.139 0.023*SL 0.104 0.025*SL 0.138 0.011*SL 0.109 0.013*SL
Parameter
Delay [ns]
Group3*
0.083 0.023*SL 0.101 0.026*SL 0.106 0.011*SL 0.090 0.013*SL 0.097 0.023*SL 0.102 0.026*SL 0.120 0.011*SL 0.101 0.013*SL 0.112 0.023*SL 0.101 0.026*SL 0.132 0.011*SL 0.107 0.013*SL 0.126 0.023*SL 0.100 0.026*SL 0.142 0.011*SL 0.110 0.013*SL
0.149 0.109 0.020*SL 0.169 0.123 0.023*SL 0.126 0.103 0.012*SL 0.115 0.088 0.013*SL 0.161 0.119 0.021*SL 0.164 0.116 0.024*SL 0.141 0.118 0.011*SL 0.125 0.097 0.014*SL 0.173 0.131 0.021*SL 0.159 0.110 0.024*SL 0.151 0.129 0.011*SL 0.131 0.104 0.014*SL 0.187 0.144 0.021*SL 0.156 0.107 0.025*SL 0.160 0.136 0.012*SL 0.134 0.107 0.014*SL *Group3 *Group1 *Group2
ND4D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.050 0.007*SL 0.059 0.005*SL 0.281 0.004*SL 0.302 0.004*SL 0.050 0.007*SL 0.060 0.005*SL 0.301 0.004*SL 0.312 0.004*SL 0.050 0.007*SL 0.059 0.005*SL 0.317 0.004*SL 0.317 0.004*SL 0.049 0.007*SL 0.059 0.005*SL 0.332 0.004*SL 0.320 0.004*SL
Group3*
0.037 0.007*SL 0.056 0.005*SL 0.288 0.003*SL 0.321 0.003*SL 0.037 0.007*SL 0.056 0.005*SL 0.307 0.003*SL 0.331 0.003*SL 0.038 0.007*SL 0.056 0.005*SL 0.324 0.003*SL 0.337 0.003*SL 0.038 0.007*SL 0.056 0.005*SL 0.339 0.003*SL 0.339 0.003*SL
0.062 0.048 0.007*SL 0.067 0.054 0.006*SL 0.285 0.275 0.005*SL 0.305 0.294 0.006*SL 0.063 0.048 0.007*SL 0.066 0.053 0.006*SL 0.305 0.295 0.005*SL 0.315 0.304 0.006*SL 0.064 0.050 0.007*SL 0.067 0.055 0.006*SL 0.322 0.312 0.005*SL 0.321 0.310 0.006*SL 0.065 0.053 0.006*SL 0.067 0.055 0.006*SL 0.336 0.326 0.005*SL 0.323 0.312 0.006*SL *Group3 *Group1 *Group2
STDL130
3-36
Samsung ASIC
ND5_LP/ND5D2_LP/ND5D4_LP
5-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
ND5_LP ND5_LP 3.33 Input Load (SL) ND5D2_LP Gate Count ND5D2_LP 3.67 ND5D4_LP ND5D4_LP 4.33
Switching Characteristics
ND5_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.037 0.028*SL 0.056 0.020*SL 0.240 0.013*SL 0.259 0.012*SL 0.038 0.028*SL 0.056 0.020*SL 0.258 0.013*SL 0.262 0.012*SL 0.038 0.028*SL 0.057 0.020*SL 0.275 0.013*SL 0.264 0.012*SL 0.039 0.028*SL 0.055 0.020*SL 0.257 0.013*SL 0.284 0.012*SL 0.039 0.028*SL 0.057 0.020*SL 0.271 0.013*SL 0.280 0.012*SL
Parameter
Delay [ns]
Group3*
0.034 0.028*SL 0.046 0.020*SL 0.241 0.013*SL 0.270 0.011*SL 0.034 0.028*SL 0.046 0.020*SL 0.259 0.013*SL 0.273 0.011*SL 0.034 0.028*SL 0.046 0.020*SL 0.276 0.013*SL 0.275 0.011*SL 0.035 0.028*SL 0.046 0.020*SL 0.259 0.013*SL 0.295 0.011*SL 0.035 0.028*SL 0.046 0.020*SL 0.273 0.013*SL 0.291 0.011*SL
0.096 0.043 0.027*SL 0.094 0.053 0.020*SL 0.265 0.237 0.014*SL 0.276 0.246 0.015*SL 0.096 0.042 0.027*SL 0.095 0.055 0.020*SL 0.284 0.256 0.014*SL 0.280 0.249 0.015*SL 0.097 0.043 0.027*SL 0.096 0.055 0.020*SL 0.300 0.272 0.014*SL 0.281 0.251 0.015*SL 0.099 0.045 0.027*SL 0.095 0.056 0.020*SL 0.283 0.255 0.014*SL 0.301 0.271 0.015*SL 0.099 0.045 0.027*SL 0.095 0.055 0.020*SL 0.297 0.269 0.014*SL 0.297 0.267 0.015*SL *Group1 *Group2 *Group3
Samsung ASIC
3-37
STDL130
ND5_LP/ND5D2_LP/ND5D4_LP
5-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND5D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.039 0.014*SL 0.061 0.010*SL 0.261 0.007*SL 0.280 0.007*SL 0.041 0.014*SL 0.063 0.010*SL 0.280 0.007*SL 0.284 0.007*SL 0.040 0.014*SL 0.063 0.010*SL 0.297 0.007*SL 0.285 0.007*SL 0.042 0.014*SL 0.062 0.010*SL 0.279 0.007*SL 0.305 0.007*SL 0.042 0.014*SL 0.062 0.010*SL 0.293 0.007*SL 0.302 0.007*SL
Parameter
Delay [ns]
Group3*
0.032 0.014*SL 0.062 0.010*SL 0.264 0.007*SL 0.299 0.006*SL 0.032 0.014*SL 0.061 0.010*SL 0.283 0.007*SL 0.303 0.006*SL 0.033 0.014*SL 0.061 0.010*SL 0.300 0.007*SL 0.304 0.006*SL 0.033 0.014*SL 0.062 0.010*SL 0.282 0.007*SL 0.324 0.006*SL 0.033 0.014*SL 0.062 0.010*SL 0.296 0.007*SL 0.320 0.006*SL
0.069 0.044 0.013*SL 0.079 0.056 0.011*SL 0.273 0.257 0.008*SL 0.289 0.269 0.010*SL 0.069 0.042 0.013*SL 0.078 0.054 0.012*SL 0.291 0.275 0.008*SL 0.292 0.273 0.010*SL 0.070 0.046 0.012*SL 0.078 0.054 0.012*SL 0.308 0.292 0.008*SL 0.293 0.273 0.010*SL 0.072 0.048 0.012*SL 0.079 0.057 0.011*SL 0.290 0.274 0.008*SL 0.314 0.294 0.010*SL 0.071 0.045 0.013*SL 0.079 0.057 0.011*SL 0.304 0.288 0.008*SL 0.310 0.290 0.010*SL *Group1 *Group2 *Group3
STDL130
3-38
Samsung ASIC
ND5_LP/ND5D2_LP/ND5D4_LP
5-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND5D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.060 0.007*SL 0.084 0.005*SL 0.301 0.004*SL 0.340 0.004*SL 0.060 0.007*SL 0.084 0.005*SL 0.320 0.004*SL 0.343 0.004*SL 0.060 0.007*SL 0.082 0.005*SL 0.337 0.004*SL 0.344 0.004*SL 0.061 0.006*SL 0.083 0.005*SL 0.321 0.004*SL 0.366 0.004*SL 0.062 0.006*SL 0.083 0.005*SL 0.335 0.004*SL 0.363 0.004*SL
Parameter
Delay [ns]
Group3*
0.045 0.007*SL 0.092 0.005*SL 0.312 0.003*SL 0.372 0.003*SL 0.046 0.007*SL 0.092 0.005*SL 0.331 0.003*SL 0.376 0.003*SL 0.046 0.007*SL 0.092 0.005*SL 0.348 0.003*SL 0.376 0.003*SL 0.047 0.007*SL 0.092 0.005*SL 0.332 0.003*SL 0.399 0.003*SL 0.047 0.007*SL 0.092 0.005*SL 0.347 0.003*SL 0.395 0.003*SL
0.071 0.056 0.007*SL 0.089 0.075 0.007*SL 0.305 0.294 0.005*SL 0.343 0.329 0.007*SL 0.073 0.059 0.007*SL 0.090 0.075 0.007*SL 0.324 0.313 0.005*SL 0.347 0.333 0.007*SL 0.072 0.057 0.007*SL 0.089 0.076 0.007*SL 0.341 0.330 0.006*SL 0.346 0.332 0.007*SL 0.072 0.058 0.007*SL 0.090 0.075 0.007*SL 0.325 0.314 0.006*SL 0.370 0.356 0.007*SL 0.073 0.058 0.007*SL 0.090 0.076 0.007*SL 0.339 0.328 0.006*SL 0.366 0.352 0.007*SL *Group1 *Group2 *Group3
Samsung ASIC
3-39
STDL130
ND6_LP/ND6D2_LP/ND6D4_LP
6-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
ND6_LP ND6_LP 3.67 Input Load (SL) ND6D2_LP Gate Count ND6D2_LP 4.00 ND6D4_LP ND6D4_LP 4.67
STDL130
3-40
Samsung ASIC
ND6_LP/ND6D2_LP/ND6D4_LP
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND6_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.037 0.028*SL 0.056 0.020*SL 0.240 0.013*SL 0.259 0.012*SL 0.038 0.028*SL 0.056 0.020*SL 0.259 0.013*SL 0.263 0.012*SL 0.038 0.028*SL 0.057 0.020*SL 0.275 0.013*SL 0.264 0.012*SL 0.040 0.028*SL 0.057 0.020*SL 0.261 0.013*SL 0.289 0.012*SL 0.040 0.028*SL 0.056 0.020*SL 0.280 0.013*SL 0.293 0.012*SL 0.040 0.028*SL 0.056 0.020*SL 0.297 0.013*SL 0.293 0.012*SL
Parameter
Delay [ns]
Group3*
0.034 0.028*SL 0.046 0.020*SL 0.241 0.013*SL 0.270 0.011*SL 0.034 0.028*SL 0.046 0.020*SL 0.260 0.013*SL 0.274 0.011*SL 0.034 0.028*SL 0.047 0.020*SL 0.276 0.013*SL 0.275 0.011*SL 0.035 0.028*SL 0.047 0.020*SL 0.262 0.013*SL 0.300 0.011*SL 0.034 0.028*SL 0.046 0.020*SL 0.281 0.013*SL 0.304 0.011*SL 0.035 0.028*SL 0.046 0.020*SL 0.298 0.013*SL 0.304 0.011*SL
0.096 0.042 0.027*SL 0.094 0.054 0.020*SL 0.266 0.238 0.014*SL 0.277 0.246 0.015*SL 0.096 0.042 0.027*SL 0.095 0.055 0.020*SL 0.284 0.256 0.014*SL 0.280 0.250 0.015*SL 0.097 0.043 0.027*SL 0.096 0.055 0.020*SL 0.300 0.273 0.014*SL 0.281 0.251 0.015*SL 0.099 0.045 0.027*SL 0.095 0.055 0.020*SL 0.286 0.258 0.014*SL 0.306 0.276 0.015*SL 0.099 0.045 0.027*SL 0.095 0.055 0.020*SL 0.305 0.277 0.014*SL 0.310 0.280 0.015*SL 0.099 0.046 0.027*SL 0.094 0.052 0.021*SL 0.322 0.294 0.014*SL 0.310 0.280 0.015*SL *Group1 *Group2 *Group3
Samsung ASIC
3-41
STDL130
ND6_LP/ND6D2_LP/ND6D4_LP
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND6D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.039 0.014*SL 0.061 0.010*SL 0.260 0.007*SL 0.281 0.007*SL 0.040 0.014*SL 0.063 0.010*SL 0.279 0.007*SL 0.284 0.007*SL 0.040 0.014*SL 0.063 0.010*SL 0.296 0.007*SL 0.285 0.007*SL 0.042 0.014*SL 0.063 0.010*SL 0.281 0.007*SL 0.310 0.007*SL 0.042 0.014*SL 0.063 0.010*SL 0.301 0.007*SL 0.314 0.007*SL 0.042 0.014*SL 0.062 0.010*SL 0.318 0.007*SL 0.314 0.007*SL
Parameter
Delay [ns]
Group3*
0.032 0.014*SL 0.062 0.010*SL 0.263 0.007*SL 0.299 0.006*SL 0.032 0.014*SL 0.061 0.010*SL 0.282 0.007*SL 0.303 0.006*SL 0.033 0.014*SL 0.061 0.010*SL 0.298 0.007*SL 0.304 0.006*SL 0.033 0.014*SL 0.061 0.010*SL 0.284 0.007*SL 0.329 0.006*SL 0.034 0.014*SL 0.061 0.010*SL 0.304 0.007*SL 0.333 0.006*SL 0.033 0.014*SL 0.062 0.010*SL 0.321 0.007*SL 0.333 0.006*SL
0.070 0.045 0.012*SL 0.079 0.056 0.011*SL 0.272 0.256 0.008*SL 0.289 0.269 0.010*SL 0.069 0.043 0.013*SL 0.079 0.055 0.012*SL 0.290 0.274 0.008*SL 0.292 0.272 0.010*SL 0.071 0.046 0.012*SL 0.078 0.054 0.012*SL 0.307 0.291 0.008*SL 0.294 0.274 0.010*SL 0.072 0.048 0.012*SL 0.079 0.056 0.012*SL 0.293 0.276 0.008*SL 0.319 0.298 0.010*SL 0.072 0.048 0.012*SL 0.078 0.054 0.012*SL 0.312 0.296 0.008*SL 0.322 0.302 0.010*SL 0.073 0.048 0.012*SL 0.079 0.057 0.011*SL 0.329 0.313 0.008*SL 0.322 0.302 0.010*SL *Group1 *Group2 *Group3
STDL130
3-42
Samsung ASIC
ND6_LP/ND6D2_LP/ND6D4_LP
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND6D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.060 0.007*SL 0.084 0.005*SL 0.301 0.004*SL 0.340 0.004*SL 0.060 0.007*SL 0.084 0.005*SL 0.320 0.004*SL 0.343 0.004*SL 0.060 0.007*SL 0.082 0.005*SL 0.337 0.004*SL 0.344 0.004*SL 0.061 0.007*SL 0.084 0.005*SL 0.324 0.004*SL 0.371 0.004*SL 0.059 0.007*SL 0.084 0.005*SL 0.344 0.004*SL 0.375 0.004*SL 0.061 0.007*SL 0.084 0.005*SL 0.361 0.004*SL 0.375 0.004*SL
Parameter
Delay [ns]
Group3*
0.045 0.007*SL 0.092 0.005*SL 0.312 0.003*SL 0.372 0.003*SL 0.046 0.007*SL 0.091 0.005*SL 0.331 0.003*SL 0.376 0.003*SL 0.046 0.007*SL 0.092 0.005*SL 0.348 0.003*SL 0.376 0.003*SL 0.047 0.007*SL 0.091 0.005*SL 0.335 0.003*SL 0.403 0.003*SL 0.048 0.007*SL 0.092 0.005*SL 0.355 0.003*SL 0.407 0.003*SL 0.047 0.007*SL 0.091 0.005*SL 0.373 0.003*SL 0.407 0.003*SL
0.071 0.056 0.007*SL 0.089 0.075 0.007*SL 0.305 0.294 0.005*SL 0.343 0.329 0.007*SL 0.072 0.059 0.007*SL 0.090 0.075 0.007*SL 0.324 0.313 0.005*SL 0.347 0.333 0.007*SL 0.072 0.057 0.007*SL 0.089 0.076 0.007*SL 0.341 0.330 0.006*SL 0.346 0.332 0.007*SL 0.074 0.061 0.007*SL 0.090 0.075 0.007*SL 0.328 0.317 0.006*SL 0.374 0.360 0.007*SL 0.074 0.061 0.006*SL 0.090 0.075 0.007*SL 0.348 0.337 0.006*SL 0.378 0.364 0.007*SL 0.074 0.061 0.007*SL 0.090 0.075 0.007*SL 0.365 0.354 0.006*SL 0.378 0.364 0.007*SL *Group1 *Group2 *Group3
Samsung ASIC
3-43
STDL130
ND8_LP/ND8D2_LP/ND8D4_LP
8-Input NAND with 1X/2X/4X Drive Logic Symbol Truth Table
Other States
Cell Data
Input Load (SL) ND8_LP ND8D2_LP ND8D4_LP Gate Count ND8_LP 4.33 ND8D2_LP 4.67 ND8D4_LP 5.33
STDL130
3-44
Samsung ASIC
ND8_LP/ND8D2_LP/ND8D4_LP
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND8_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.039 0.029*SL 0.057 0.020*SL 0.248 0.014*SL 0.287 0.012*SL 0.039 0.029*SL 0.058 0.020*SL 0.267 0.014*SL 0.296 0.012*SL 0.039 0.029*SL 0.058 0.020*SL 0.283 0.014*SL 0.302 0.012*SL 0.039 0.029*SL 0.058 0.020*SL 0.297 0.014*SL 0.305 0.012*SL 0.040 0.029*SL 0.058 0.020*SL 0.271 0.014*SL 0.319 0.012*SL 0.040 0.029*SL 0.058 0.020*SL 0.290 0.014*SL 0.328 0.012*SL 0.040 0.029*SL 0.058 0.020*SL 0.307 0.014*SL 0.334 0.012*SL 0.041 0.029*SL 0.058 0.020*SL 0.322 0.014*SL 0.337 0.012*SL
Parameter
Delay [ns]
Group3*
0.034 0.029*SL 0.047 0.020*SL 0.249 0.014*SL 0.299 0.011*SL 0.034 0.029*SL 0.047 0.020*SL 0.268 0.014*SL 0.308 0.011*SL 0.034 0.029*SL 0.048 0.020*SL 0.284 0.014*SL 0.313 0.011*SL 0.034 0.029*SL 0.047 0.020*SL 0.299 0.014*SL 0.316 0.011*SL 0.035 0.029*SL 0.048 0.020*SL 0.273 0.014*SL 0.330 0.011*SL 0.035 0.029*SL 0.048 0.020*SL 0.292 0.014*SL 0.340 0.011*SL 0.035 0.029*SL 0.047 0.020*SL 0.309 0.014*SL 0.345 0.011*SL 0.035 0.029*SL 0.048 0.020*SL 0.323 0.014*SL 0.349 0.011*SL
0.098 0.043 0.027*SL 0.096 0.055 0.020*SL 0.274 0.246 0.014*SL 0.304 0.274 0.015*SL 0.099 0.044 0.027*SL 0.096 0.056 0.020*SL 0.293 0.265 0.014*SL 0.313 0.283 0.015*SL 0.099 0.044 0.027*SL 0.097 0.057 0.020*SL 0.309 0.281 0.014*SL 0.319 0.288 0.015*SL 0.099 0.045 0.027*SL 0.095 0.054 0.021*SL 0.323 0.295 0.014*SL 0.322 0.291 0.015*SL 0.100 0.046 0.027*SL 0.096 0.056 0.020*SL 0.297 0.268 0.014*SL 0.336 0.305 0.015*SL 0.100 0.045 0.027*SL 0.097 0.057 0.020*SL 0.316 0.288 0.014*SL 0.345 0.314 0.015*SL 0.100 0.045 0.027*SL 0.096 0.055 0.020*SL 0.333 0.304 0.014*SL 0.351 0.320 0.015*SL 0.101 0.047 0.027*SL 0.097 0.057 0.020*SL 0.348 0.319 0.014*SL 0.354 0.323 0.015*SL *Group3 *Group1 *Group2
Samsung ASIC
3-45
STDL130
ND8_LP/ND8D2_LP/ND8D4_LP
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND8D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.041 0.014*SL 0.063 0.010*SL 0.268 0.007*SL 0.309 0.007*SL 0.041 0.014*SL 0.064 0.010*SL 0.287 0.007*SL 0.318 0.007*SL 0.041 0.014*SL 0.063 0.010*SL 0.304 0.007*SL 0.323 0.007*SL 0.041 0.014*SL 0.064 0.010*SL 0.318 0.007*SL 0.326 0.007*SL 0.043 0.014*SL 0.063 0.010*SL 0.292 0.007*SL 0.340 0.007*SL 0.043 0.014*SL 0.064 0.010*SL 0.311 0.007*SL 0.350 0.007*SL 0.042 0.014*SL 0.063 0.010*SL 0.328 0.007*SL 0.355 0.007*SL 0.042 0.014*SL 0.064 0.010*SL 0.343 0.007*SL 0.359 0.007*SL
Parameter
Delay [ns]
Group3*
0.031 0.014*SL 0.062 0.010*SL 0.271 0.007*SL 0.327 0.006*SL 0.032 0.014*SL 0.062 0.010*SL 0.290 0.007*SL 0.336 0.006*SL 0.032 0.014*SL 0.063 0.010*SL 0.306 0.007*SL 0.342 0.006*SL 0.033 0.014*SL 0.062 0.010*SL 0.321 0.007*SL 0.345 0.006*SL 0.033 0.014*SL 0.063 0.010*SL 0.294 0.007*SL 0.359 0.006*SL 0.033 0.014*SL 0.063 0.010*SL 0.314 0.007*SL 0.369 0.006*SL 0.034 0.014*SL 0.062 0.010*SL 0.331 0.007*SL 0.374 0.006*SL 0.034 0.014*SL 0.062 0.010*SL 0.346 0.007*SL 0.377 0.006*SL
0.071 0.046 0.013*SL 0.079 0.056 0.012*SL 0.279 0.263 0.008*SL 0.317 0.296 0.010*SL 0.070 0.043 0.013*SL 0.079 0.056 0.012*SL 0.298 0.282 0.008*SL 0.326 0.305 0.010*SL 0.070 0.043 0.013*SL 0.080 0.058 0.011*SL 0.315 0.299 0.008*SL 0.331 0.311 0.010*SL 0.072 0.047 0.012*SL 0.079 0.055 0.012*SL 0.330 0.313 0.008*SL 0.334 0.314 0.010*SL 0.071 0.045 0.013*SL 0.080 0.058 0.011*SL 0.303 0.286 0.008*SL 0.348 0.328 0.010*SL 0.072 0.046 0.013*SL 0.080 0.057 0.011*SL 0.322 0.306 0.008*SL 0.358 0.338 0.010*SL 0.072 0.047 0.013*SL 0.080 0.057 0.011*SL 0.339 0.323 0.008*SL 0.363 0.343 0.010*SL 0.073 0.049 0.012*SL 0.080 0.056 0.012*SL 0.355 0.338 0.008*SL 0.367 0.346 0.010*SL *Group3 *Group1 *Group2
STDL130
3-46
Samsung ASIC
ND8_LP/ND8D2_LP/ND8D4_LP
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND8D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.064 0.007*SL 0.084 0.005*SL 0.324 0.004*SL 0.367 0.004*SL 0.064 0.007*SL 0.084 0.005*SL 0.342 0.004*SL 0.375 0.004*SL 0.065 0.007*SL 0.082 0.005*SL 0.360 0.004*SL 0.382 0.004*SL 0.065 0.006*SL 0.085 0.005*SL 0.375 0.004*SL 0.384 0.004*SL 0.065 0.007*SL 0.084 0.005*SL 0.352 0.004*SL 0.400 0.004*SL 0.065 0.007*SL 0.083 0.005*SL 0.371 0.004*SL 0.410 0.004*SL 0.066 0.007*SL 0.085 0.005*SL 0.389 0.004*SL 0.415 0.004*SL 0.065 0.007*SL 0.083 0.005*SL 0.405 0.004*SL 0.418 0.004*SL
Parameter
Delay [ns]
Group3*
0.050 0.007*SL 0.092 0.005*SL 0.337 0.003*SL 0.399 0.003*SL 0.051 0.007*SL 0.092 0.005*SL 0.356 0.003*SL 0.408 0.003*SL 0.051 0.007*SL 0.093 0.005*SL 0.374 0.003*SL 0.414 0.003*SL 0.050 0.007*SL 0.091 0.005*SL 0.389 0.003*SL 0.417 0.003*SL 0.053 0.007*SL 0.093 0.005*SL 0.366 0.003*SL 0.433 0.003*SL 0.053 0.007*SL 0.093 0.005*SL 0.386 0.003*SL 0.442 0.003*SL 0.054 0.007*SL 0.092 0.005*SL 0.403 0.003*SL 0.448 0.003*SL 0.054 0.007*SL 0.093 0.005*SL 0.419 0.003*SL 0.451 0.003*SL
0.075 0.060 0.008*SL 0.090 0.075 0.007*SL 0.327 0.316 0.006*SL 0.370 0.356 0.007*SL 0.076 0.063 0.007*SL 0.090 0.076 0.007*SL 0.346 0.334 0.006*SL 0.378 0.364 0.007*SL 0.076 0.061 0.008*SL 0.089 0.075 0.007*SL 0.364 0.352 0.006*SL 0.385 0.371 0.007*SL 0.077 0.063 0.007*SL 0.090 0.075 0.007*SL 0.379 0.367 0.006*SL 0.387 0.373 0.007*SL 0.078 0.065 0.007*SL 0.090 0.075 0.007*SL 0.356 0.344 0.006*SL 0.403 0.389 0.007*SL 0.079 0.066 0.006*SL 0.089 0.076 0.007*SL 0.375 0.364 0.006*SL 0.413 0.399 0.007*SL 0.079 0.066 0.007*SL 0.090 0.075 0.007*SL 0.393 0.381 0.006*SL 0.418 0.404 0.007*SL 0.079 0.066 0.006*SL 0.089 0.076 0.007*SL 0.409 0.397 0.006*SL 0.422 0.407 0.007*SL *Group3 *Group1 *Group2
Samsung ASIC
3-47
STDL130
2-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
NR2_LP NR2A_LP NR2A_LP 1.67 Input Load (SL) NR2D2_LP Gate Count NR2D2_LP 1.67 NR2D4_LP NR2D4_LP 3.00 NR2D8_LP NR2D8_LP 4.33
NR2_LP 1.33
Switching Characteristics
NR2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.100 0.057*SL 0.058 0.018*SL 0.096 0.028*SL 0.073 0.011*SL 0.094 0.057*SL 0.071 0.019*SL 0.120 0.028*SL 0.085 0.011*SL
Parameter
Delay [ns]
Group3*
0.089 0.057*SL 0.035 0.020*SL 0.097 0.028*SL 0.075 0.011*SL 0.089 0.057*SL 0.052 0.020*SL 0.121 0.028*SL 0.087 0.011*SL
0.222 0.117 0.053*SL 0.099 0.067 0.016*SL 0.152 0.097 0.028*SL 0.087 0.058 0.015*SL 0.212 0.101 0.055*SL 0.112 0.079 0.017*SL 0.176 0.120 0.028*SL 0.103 0.077 0.013*SL *Group3 *Group1 *Group2
NR2A_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.087 0.027*SL 0.059 0.022*SL 0.083 0.014*SL 0.085 0.013*SL 0.071 0.028*SL 0.089 0.022*SL 0.103 0.014*SL 0.112 0.013*SL
Group3*
0.065 0.029*SL 0.040 0.023*SL 0.083 0.014*SL 0.088 0.013*SL 0.063 0.029*SL 0.074 0.023*SL 0.103 0.014*SL 0.116 0.013*SL
0.148 0.100 0.024*SL 0.108 0.069 0.020*SL 0.107 0.075 0.016*SL 0.106 0.076 0.015*SL 0.131 0.078 0.027*SL 0.137 0.096 0.021*SL 0.129 0.099 0.015*SL 0.136 0.109 0.014*SL *Group1 *Group2 *Group3
STDL130
3-48
Samsung ASIC
2-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Switching Characteristics
NR2D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.097 0.028*SL 0.061 0.009*SL 0.091 0.014*SL 0.062 0.006*SL 0.084 0.029*SL 0.073 0.009*SL 0.112 0.014*SL 0.078 0.006*SL
Parameter
Delay [ns]
Group3*
0.078 0.029*SL 0.045 0.010*SL 0.091 0.014*SL 0.072 0.006*SL 0.076 0.029*SL 0.060 0.010*SL 0.112 0.014*SL 0.083 0.006*SL
0.158 0.107 0.025*SL 0.076 0.057 0.010*SL 0.117 0.087 0.015*SL 0.068 0.048 0.010*SL 0.143 0.088 0.028*SL 0.091 0.074 0.009*SL 0.139 0.110 0.015*SL 0.085 0.069 0.008*SL *Group1 *Group2 *Group3
NR2D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.057 0.007*SL 0.051 0.005*SL 0.309 0.004*SL 0.228 0.003*SL 0.057 0.007*SL 0.050 0.005*SL 0.333 0.004*SL 0.244 0.003*SL
Group3*
0.043 0.007*SL 0.047 0.005*SL 0.318 0.003*SL 0.244 0.003*SL 0.043 0.007*SL 0.047 0.005*SL 0.342 0.003*SL 0.260 0.003*SL
0.070 0.057 0.007*SL 0.059 0.047 0.006*SL 0.313 0.303 0.005*SL 0.231 0.221 0.005*SL 0.071 0.058 0.006*SL 0.059 0.048 0.005*SL 0.337 0.327 0.005*SL 0.247 0.237 0.005*SL *Group1 *Group2 *Group3
NR2D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.058 0.003*SL 0.047 0.002*SL 0.313 0.002*SL 0.230 0.002*SL 0.057 0.003*SL 0.047 0.002*SL 0.333 0.002*SL 0.246 0.002*SL
Group3*
0.043 0.004*SL 0.045 0.003*SL 0.325 0.002*SL 0.247 0.001*SL 0.044 0.004*SL 0.046 0.002*SL 0.345 0.002*SL 0.263 0.001*SL
0.063 0.054 0.004*SL 0.052 0.048 0.002*SL 0.315 0.309 0.003*SL 0.231 0.225 0.003*SL 0.064 0.058 0.003*SL 0.052 0.047 0.002*SL 0.335 0.329 0.003*SL 0.247 0.241 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-49
STDL130
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
NR2B_LP NR2B_LP 1.67 Input Load (SL) NR2BD2_LP NR2BD4_LP Gate Count NR2BD2_LP NR2BD4_LP 2.00 3.33 NR2BD8_LP NR2BD8_LP 5.00
Switching Characteristics
NR2B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.091 0.057*SL 0.045 0.019*SL 0.124 0.028*SL 0.174 0.011*SL 0.095 0.057*SL 0.071 0.019*SL 0.122 0.028*SL 0.085 0.011*SL
Parameter
Delay [ns]
Group3*
0.091 0.057*SL 0.037 0.020*SL 0.127 0.028*SL 0.178 0.011*SL 0.091 0.057*SL 0.052 0.020*SL 0.123 0.028*SL 0.087 0.011*SL
0.206 0.092 0.057*SL 0.087 0.051 0.018*SL 0.179 0.123 0.028*SL 0.192 0.166 0.013*SL 0.213 0.102 0.055*SL 0.112 0.079 0.017*SL 0.177 0.121 0.028*SL 0.103 0.076 0.013*SL *Group3 *Group1 *Group2
NR2BD2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.079 0.029*SL 0.051 0.010*SL 0.129 0.014*SL 0.183 0.006*SL 0.085 0.028*SL 0.074 0.009*SL 0.113 0.014*SL 0.077 0.006*SL
Group3*
0.076 0.029*SL 0.045 0.010*SL 0.131 0.014*SL 0.192 0.006*SL 0.078 0.029*SL 0.061 0.010*SL 0.114 0.014*SL 0.083 0.006*SL
0.138 0.081 0.028*SL 0.069 0.049 0.010*SL 0.156 0.127 0.014*SL 0.191 0.175 0.008*SL 0.145 0.090 0.027*SL 0.093 0.075 0.009*SL 0.140 0.110 0.015*SL 0.085 0.068 0.008*SL *Group1 *Group2 *Group3
STDL130
3-50
Samsung ASIC
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
NR2BD4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.058 0.007*SL 0.049 0.005*SL 0.334 0.004*SL 0.316 0.003*SL 0.056 0.007*SL 0.048 0.005*SL 0.336 0.004*SL 0.242 0.003*SL
Parameter
Delay [ns]
Group3*
0.043 0.007*SL 0.048 0.005*SL 0.343 0.003*SL 0.332 0.003*SL 0.044 0.007*SL 0.046 0.005*SL 0.345 0.003*SL 0.258 0.003*SL
0.071 0.058 0.006*SL 0.059 0.049 0.005*SL 0.338 0.328 0.005*SL 0.319 0.309 0.005*SL 0.071 0.059 0.006*SL 0.058 0.048 0.005*SL 0.340 0.330 0.005*SL 0.245 0.235 0.005*SL *Group1 *Group2 *Group3
NR2BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.057 0.003*SL 0.047 0.002*SL 0.339 0.002*SL 0.329 0.002*SL 0.057 0.003*SL 0.048 0.002*SL 0.334 0.002*SL 0.242 0.002*SL
Group3*
0.043 0.004*SL 0.045 0.003*SL 0.351 0.002*SL 0.346 0.001*SL 0.044 0.004*SL 0.046 0.003*SL 0.345 0.002*SL 0.260 0.001*SL
0.063 0.056 0.003*SL 0.052 0.046 0.003*SL 0.340 0.335 0.003*SL 0.330 0.325 0.003*SL 0.063 0.057 0.003*SL 0.052 0.046 0.003*SL 0.336 0.330 0.003*SL 0.244 0.238 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-51
STDL130
3-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Logic Symbol
Truth Table
Other States
Cell Data
NR3_LP NR3_LP 1.67 NR3A_LP Input Load (SL) NR3D2_LP Gate Count NR3A_LP NR3D2_LP 2.00 2.67 NR3D4_LP NR3D4_LP 3.33
STDL130
3-52
Samsung ASIC
3-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Switching Characteristics
NR3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.159 0.086*SL 0.061 0.030*SL 0.102 0.042*SL 0.086 0.017*SL 0.165 0.086*SL 0.083 0.030*SL 0.159 0.042*SL 0.107 0.017*SL 0.164 0.086*SL 0.107 0.030*SL 0.182 0.042*SL 0.116 0.018*SL
Parameter
Delay [ns]
Group3*
0.163 0.086*SL 0.041 0.031*SL 0.104 0.042*SL 0.088 0.017*SL 0.163 0.086*SL 0.068 0.031*SL 0.160 0.042*SL 0.110 0.017*SL 0.163 0.086*SL 0.094 0.031*SL 0.184 0.042*SL 0.125 0.017*SL
0.339 0.173 0.083*SL 0.128 0.074 0.027*SL 0.187 0.103 0.042*SL 0.117 0.080 0.018*SL 0.340 0.171 0.085*SL 0.149 0.094 0.028*SL 0.243 0.158 0.043*SL 0.139 0.103 0.018*SL 0.339 0.169 0.085*SL 0.170 0.112 0.029*SL 0.267 0.182 0.042*SL 0.148 0.111 0.019*SL *Group1 *Group2 *Group3
NR3A_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.128 0.043*SL 0.066 0.032*SL 0.085 0.022*SL 0.099 0.018*SL 0.126 0.043*SL 0.110 0.032*SL 0.134 0.022*SL 0.141 0.018*SL 0.123 0.044*SL 0.153 0.032*SL 0.154 0.022*SL 0.166 0.019*SL
Group3*
0.114 0.044*SL 0.053 0.032*SL 0.086 0.022*SL 0.104 0.018*SL 0.120 0.044*SL 0.101 0.033*SL 0.135 0.021*SL 0.147 0.018*SL 0.119 0.044*SL 0.151 0.032*SL 0.155 0.021*SL 0.178 0.018*SL
0.219 0.138 0.041*SL 0.137 0.080 0.028*SL 0.129 0.087 0.021*SL 0.134 0.096 0.019*SL 0.216 0.132 0.042*SL 0.177 0.116 0.030*SL 0.177 0.133 0.022*SL 0.175 0.137 0.019*SL 0.214 0.129 0.042*SL 0.218 0.154 0.032*SL 0.196 0.153 0.022*SL 0.199 0.159 0.020*SL *Group3 *Group1 *Group2
Samsung ASIC
3-53
STDL130
3-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Switching Characteristics
NR3D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.144 0.043*SL 0.062 0.014*SL 0.091 0.021*SL 0.079 0.009*SL 0.144 0.043*SL 0.082 0.014*SL 0.146 0.021*SL 0.099 0.009*SL 0.142 0.043*SL 0.102 0.015*SL 0.169 0.021*SL 0.106 0.009*SL
Parameter
Delay [ns]
Group3*
0.131 0.043*SL 0.045 0.015*SL 0.092 0.021*SL 0.082 0.008*SL 0.138 0.043*SL 0.068 0.015*SL 0.147 0.021*SL 0.102 0.009*SL 0.138 0.043*SL 0.093 0.015*SL 0.170 0.021*SL 0.113 0.009*SL
0.233 0.152 0.041*SL 0.094 0.069 0.013*SL 0.136 0.096 0.020*SL 0.090 0.066 0.012*SL 0.232 0.149 0.042*SL 0.114 0.088 0.013*SL 0.188 0.145 0.022*SL 0.114 0.094 0.010*SL 0.230 0.145 0.042*SL 0.132 0.102 0.015*SL 0.211 0.168 0.021*SL 0.122 0.103 0.010*SL *Group1 *Group2 *Group3
NR3D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.063 0.006*SL 0.053 0.005*SL 0.361 0.004*SL 0.250 0.003*SL 0.062 0.007*SL 0.051 0.005*SL 0.418 0.004*SL 0.272 0.003*SL 0.062 0.007*SL 0.052 0.005*SL 0.442 0.004*SL 0.285 0.004*SL
Group3*
0.047 0.007*SL 0.046 0.005*SL 0.372 0.003*SL 0.267 0.003*SL 0.047 0.007*SL 0.048 0.005*SL 0.429 0.003*SL 0.288 0.003*SL 0.048 0.007*SL 0.049 0.005*SL 0.453 0.003*SL 0.301 0.003*SL
0.076 0.062 0.007*SL 0.059 0.047 0.006*SL 0.365 0.354 0.006*SL 0.254 0.243 0.005*SL 0.076 0.063 0.006*SL 0.060 0.049 0.005*SL 0.422 0.411 0.006*SL 0.275 0.265 0.005*SL 0.075 0.063 0.006*SL 0.060 0.050 0.005*SL 0.446 0.435 0.006*SL 0.288 0.277 0.005*SL *Group3 *Group1 *Group2
STDL130
3-54
Samsung ASIC
NR4_LP/NR4D2_LP/NR4D4_LP
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
NR4_LP NR4_LP 3.33 Input Load (SL) NR4D2_LP Gate Count NR4D2_LP 3.67 NR4D4_LP NR4D4_LP 4.33
Switching Characteristics
NR4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.041 0.028*SL 0.046 0.019*SL 0.242 0.014*SL 0.210 0.011*SL 0.040 0.029*SL 0.047 0.019*SL 0.262 0.014*SL 0.225 0.011*SL 0.041 0.029*SL 0.046 0.019*SL 0.243 0.014*SL 0.229 0.011*SL 0.041 0.029*SL 0.047 0.019*SL 0.263 0.014*SL 0.243 0.011*SL
Parameter
Delay [ns]
Group3*
0.034 0.029*SL 0.035 0.020*SL 0.244 0.014*SL 0.216 0.011*SL 0.034 0.029*SL 0.035 0.020*SL 0.264 0.014*SL 0.231 0.011*SL 0.034 0.029*SL 0.036 0.020*SL 0.245 0.014*SL 0.235 0.011*SL 0.034 0.029*SL 0.036 0.020*SL 0.264 0.014*SL 0.250 0.011*SL
0.101 0.047 0.027*SL 0.085 0.048 0.019*SL 0.268 0.238 0.015*SL 0.227 0.200 0.014*SL 0.100 0.046 0.027*SL 0.083 0.044 0.020*SL 0.287 0.258 0.015*SL 0.242 0.215 0.014*SL 0.100 0.046 0.027*SL 0.086 0.050 0.018*SL 0.268 0.239 0.015*SL 0.245 0.218 0.014*SL 0.100 0.046 0.027*SL 0.087 0.050 0.018*SL 0.288 0.259 0.015*SL 0.260 0.232 0.014*SL *Group3 *Group1 *Group2
Samsung ASIC
3-55
STDL130
NR4_LP/NR4D2_LP/NR4D4_LP
4-Input with 1X/2X/4X Drive Switching Characteristics
NR4D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.049 0.014*SL 0.050 0.009*SL 0.276 0.007*SL 0.219 0.006*SL 0.050 0.014*SL 0.051 0.009*SL 0.295 0.007*SL 0.234 0.006*SL 0.048 0.014*SL 0.053 0.009*SL 0.275 0.007*SL 0.233 0.006*SL 0.049 0.014*SL 0.053 0.009*SL 0.294 0.007*SL 0.247 0.006*SL
Parameter
Delay [ns]
Group3*
0.039 0.014*SL 0.044 0.010*SL 0.281 0.007*SL 0.232 0.006*SL 0.039 0.014*SL 0.045 0.010*SL 0.301 0.007*SL 0.246 0.006*SL 0.040 0.014*SL 0.047 0.010*SL 0.281 0.007*SL 0.245 0.006*SL 0.039 0.014*SL 0.047 0.010*SL 0.300 0.007*SL 0.260 0.006*SL
0.077 0.050 0.013*SL 0.066 0.045 0.011*SL 0.286 0.268 0.009*SL 0.227 0.209 0.009*SL 0.076 0.048 0.014*SL 0.067 0.046 0.011*SL 0.306 0.288 0.009*SL 0.242 0.224 0.009*SL 0.077 0.052 0.013*SL 0.070 0.050 0.010*SL 0.285 0.267 0.009*SL 0.240 0.223 0.009*SL 0.076 0.049 0.014*SL 0.070 0.049 0.010*SL 0.305 0.287 0.009*SL 0.255 0.237 0.009*SL *Group3 *Group1 *Group2
NR4D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.068 0.007*SL 0.052 0.005*SL 0.343 0.004*SL 0.231 0.004*SL 0.069 0.007*SL 0.054 0.005*SL 0.362 0.004*SL 0.245 0.004*SL 0.067 0.007*SL 0.054 0.005*SL 0.339 0.004*SL 0.239 0.004*SL 0.068 0.007*SL 0.056 0.005*SL 0.358 0.004*SL 0.253 0.004*SL
Group3*
0.060 0.007*SL 0.051 0.005*SL 0.361 0.003*SL 0.249 0.003*SL 0.059 0.007*SL 0.049 0.005*SL 0.380 0.003*SL 0.263 0.003*SL 0.060 0.007*SL 0.052 0.005*SL 0.357 0.003*SL 0.258 0.003*SL 0.059 0.007*SL 0.051 0.005*SL 0.376 0.003*SL 0.272 0.003*SL
0.080 0.065 0.008*SL 0.061 0.050 0.005*SL 0.347 0.334 0.006*SL 0.235 0.224 0.005*SL 0.081 0.067 0.007*SL 0.060 0.048 0.006*SL 0.366 0.354 0.006*SL 0.248 0.238 0.005*SL 0.080 0.066 0.007*SL 0.062 0.051 0.006*SL 0.343 0.330 0.006*SL 0.243 0.232 0.005*SL 0.080 0.066 0.007*SL 0.062 0.050 0.006*SL 0.362 0.350 0.006*SL 0.257 0.246 0.005*SL *Group1 *Group2 *Group3
STDL130
3-56
Samsung ASIC
NR5_LP/NR5D2_LP/NR5D4_LP
5-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
NR5_LP NR5_LP 3.67 Input Load (SL) NR5D2_LP Gate Count NR5D2_LP 4.00 NR5D4_LP NR5D4_LP 4.67
Samsung ASIC
3-57
STDL130
NR5_LP/NR5D2_LP/NR5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
NR5_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.043 0.028*SL 0.045 0.020*SL 0.265 0.014*SL 0.230 0.012*SL 0.043 0.028*SL 0.046 0.020*SL 0.321 0.014*SL 0.252 0.012*SL 0.043 0.028*SL 0.047 0.020*SL 0.341 0.014*SL 0.263 0.012*SL 0.041 0.028*SL 0.049 0.020*SL 0.250 0.014*SL 0.232 0.012*SL 0.041 0.028*SL 0.046 0.020*SL 0.274 0.014*SL 0.248 0.012*SL
Parameter
Delay [ns]
Group3*
0.035 0.029*SL 0.035 0.021*SL 0.267 0.013*SL 0.235 0.011*SL 0.035 0.029*SL 0.035 0.020*SL 0.323 0.013*SL 0.258 0.011*SL 0.035 0.029*SL 0.036 0.020*SL 0.343 0.013*SL 0.268 0.011*SL 0.035 0.029*SL 0.036 0.020*SL 0.251 0.013*SL 0.238 0.011*SL 0.035 0.029*SL 0.037 0.020*SL 0.276 0.013*SL 0.254 0.011*SL
0.103 0.050 0.027*SL 0.087 0.049 0.019*SL 0.290 0.261 0.015*SL 0.248 0.220 0.014*SL 0.103 0.050 0.027*SL 0.085 0.045 0.020*SL 0.346 0.317 0.015*SL 0.270 0.242 0.014*SL 0.103 0.050 0.027*SL 0.086 0.046 0.020*SL 0.366 0.336 0.015*SL 0.281 0.253 0.014*SL 0.100 0.046 0.027*SL 0.088 0.049 0.020*SL 0.275 0.246 0.015*SL 0.250 0.221 0.014*SL 0.100 0.046 0.027*SL 0.088 0.050 0.019*SL 0.299 0.270 0.015*SL 0.266 0.238 0.014*SL *Group1 *Group2 *Group3
STDL130
3-58
Samsung ASIC
NR5_LP/NR5D2_LP/NR5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
NR5D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.051 0.014*SL 0.051 0.010*SL 0.301 0.007*SL 0.238 0.006*SL 0.052 0.013*SL 0.049 0.010*SL 0.358 0.007*SL 0.260 0.006*SL 0.052 0.013*SL 0.051 0.010*SL 0.378 0.007*SL 0.271 0.006*SL 0.047 0.014*SL 0.051 0.010*SL 0.282 0.007*SL 0.236 0.007*SL 0.047 0.014*SL 0.051 0.010*SL 0.306 0.007*SL 0.252 0.007*SL
Group3*
0.040 0.014*SL 0.045 0.010*SL 0.307 0.007*SL 0.250 0.006*SL 0.040 0.014*SL 0.045 0.010*SL 0.364 0.007*SL 0.272 0.006*SL 0.040 0.014*SL 0.045 0.010*SL 0.384 0.007*SL 0.283 0.006*SL 0.039 0.014*SL 0.046 0.010*SL 0.288 0.007*SL 0.248 0.006*SL 0.039 0.014*SL 0.044 0.010*SL 0.312 0.007*SL 0.264 0.006*SL
0.079 0.054 0.013*SL 0.067 0.044 0.011*SL 0.312 0.294 0.009*SL 0.246 0.228 0.009*SL 0.080 0.053 0.013*SL 0.067 0.045 0.011*SL 0.368 0.350 0.009*SL 0.268 0.251 0.009*SL 0.079 0.053 0.013*SL 0.068 0.047 0.011*SL 0.388 0.370 0.009*SL 0.279 0.261 0.009*SL 0.076 0.051 0.013*SL 0.070 0.050 0.010*SL 0.292 0.274 0.009*SL 0.244 0.226 0.009*SL 0.077 0.052 0.013*SL 0.069 0.048 0.010*SL 0.316 0.298 0.009*SL 0.260 0.242 0.009*SL *Group1 *Group2 *Group3
Samsung ASIC
3-59
STDL130
NR5_LP/NR5D2_LP/NR5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
NR5D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.073 0.007*SL 0.051 0.005*SL 0.382 0.004*SL 0.252 0.004*SL 0.072 0.007*SL 0.052 0.005*SL 0.439 0.004*SL 0.274 0.004*SL 0.072 0.007*SL 0.055 0.005*SL 0.458 0.004*SL 0.285 0.004*SL 0.069 0.007*SL 0.054 0.005*SL 0.347 0.004*SL 0.243 0.004*SL 0.068 0.007*SL 0.053 0.005*SL 0.372 0.004*SL 0.258 0.004*SL
Parameter
Delay [ns]
Group3*
0.063 0.007*SL 0.051 0.005*SL 0.401 0.003*SL 0.270 0.003*SL 0.063 0.007*SL 0.051 0.005*SL 0.458 0.003*SL 0.292 0.003*SL 0.063 0.007*SL 0.052 0.005*SL 0.478 0.003*SL 0.303 0.003*SL 0.060 0.007*SL 0.051 0.005*SL 0.366 0.003*SL 0.261 0.003*SL 0.060 0.007*SL 0.052 0.005*SL 0.390 0.003*SL 0.276 0.003*SL
0.082 0.066 0.008*SL 0.060 0.049 0.005*SL 0.386 0.373 0.006*SL 0.255 0.245 0.005*SL 0.082 0.067 0.008*SL 0.061 0.051 0.005*SL 0.443 0.430 0.006*SL 0.277 0.266 0.005*SL 0.082 0.066 0.008*SL 0.061 0.048 0.006*SL 0.462 0.449 0.006*SL 0.289 0.278 0.005*SL 0.081 0.067 0.007*SL 0.062 0.051 0.006*SL 0.351 0.339 0.006*SL 0.246 0.236 0.005*SL 0.080 0.065 0.007*SL 0.061 0.050 0.006*SL 0.375 0.363 0.006*SL 0.262 0.251 0.005*SL *Group1 *Group2 *Group3
STDL130
3-60
Samsung ASIC
NR6_LP/NR6D2_LP/NR6D4_LP
6-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
NR6_LP NR6_LP 4.00 Input Load (SL) NR6D2_LP Gate Count NR6D2_LP 4.67 NR6D4_LP NR6D4_LP 5.00
Samsung ASIC
3-61
STDL130
NR6_LP/NR6D2_LP/NR6D4_LP
6-Input with 1X/2X/4X Drive Switching Characteristics
NR6_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.043 0.028*SL 0.044 0.020*SL 0.265 0.014*SL 0.229 0.012*SL 0.043 0.028*SL 0.047 0.020*SL 0.317 0.014*SL 0.251 0.012*SL 0.043 0.028*SL 0.047 0.020*SL 0.338 0.014*SL 0.261 0.012*SL 0.043 0.028*SL 0.049 0.020*SL 0.276 0.014*SL 0.254 0.012*SL 0.043 0.028*SL 0.046 0.020*SL 0.332 0.014*SL 0.276 0.012*SL 0.043 0.028*SL 0.049 0.020*SL 0.356 0.014*SL 0.288 0.012*SL
Parameter
Delay [ns]
Group3*
0.035 0.029*SL 0.035 0.020*SL 0.266 0.013*SL 0.235 0.011*SL 0.035 0.029*SL 0.035 0.021*SL 0.319 0.013*SL 0.256 0.011*SL 0.035 0.029*SL 0.035 0.021*SL 0.339 0.013*SL 0.267 0.011*SL 0.035 0.029*SL 0.036 0.020*SL 0.278 0.013*SL 0.260 0.011*SL 0.036 0.029*SL 0.037 0.020*SL 0.334 0.013*SL 0.282 0.011*SL 0.035 0.029*SL 0.037 0.020*SL 0.357 0.013*SL 0.295 0.011*SL
0.103 0.050 0.027*SL 0.085 0.047 0.019*SL 0.290 0.260 0.015*SL 0.247 0.219 0.014*SL 0.103 0.049 0.027*SL 0.085 0.045 0.020*SL 0.342 0.313 0.015*SL 0.269 0.241 0.014*SL 0.103 0.049 0.027*SL 0.086 0.046 0.020*SL 0.363 0.333 0.015*SL 0.279 0.252 0.014*SL 0.103 0.050 0.027*SL 0.088 0.048 0.020*SL 0.301 0.271 0.015*SL 0.272 0.244 0.014*SL 0.102 0.048 0.027*SL 0.088 0.050 0.019*SL 0.357 0.328 0.015*SL 0.294 0.266 0.014*SL 0.103 0.050 0.027*SL 0.090 0.052 0.019*SL 0.380 0.351 0.015*SL 0.306 0.278 0.014*SL *Group1 *Group2 *Group3
STDL130
3-62
Samsung ASIC
NR6_LP/NR6D2_LP/NR6D4_LP
6-Input with 1X/2X/4X Drive Switching Characteristics
NR6D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.053 0.013*SL 0.049 0.010*SL 0.305 0.007*SL 0.240 0.006*SL 0.052 0.013*SL 0.050 0.010*SL 0.359 0.007*SL 0.262 0.007*SL 0.052 0.013*SL 0.051 0.010*SL 0.379 0.007*SL 0.273 0.007*SL 0.049 0.014*SL 0.052 0.010*SL 0.311 0.007*SL 0.258 0.007*SL 0.049 0.014*SL 0.053 0.010*SL 0.367 0.007*SL 0.280 0.007*SL 0.049 0.014*SL 0.053 0.010*SL 0.391 0.007*SL 0.293 0.007*SL
Parameter
Delay [ns]
Group3*
0.040 0.014*SL 0.043 0.010*SL 0.311 0.007*SL 0.252 0.006*SL 0.040 0.014*SL 0.045 0.010*SL 0.365 0.007*SL 0.274 0.006*SL 0.040 0.014*SL 0.045 0.010*SL 0.385 0.007*SL 0.285 0.006*SL 0.041 0.014*SL 0.047 0.010*SL 0.317 0.007*SL 0.271 0.006*SL 0.041 0.014*SL 0.046 0.010*SL 0.374 0.007*SL 0.293 0.006*SL 0.041 0.014*SL 0.047 0.010*SL 0.397 0.007*SL 0.306 0.006*SL
0.080 0.053 0.013*SL 0.067 0.046 0.010*SL 0.315 0.297 0.009*SL 0.248 0.230 0.009*SL 0.080 0.054 0.013*SL 0.067 0.045 0.011*SL 0.369 0.351 0.009*SL 0.270 0.252 0.009*SL 0.080 0.054 0.013*SL 0.068 0.047 0.011*SL 0.389 0.371 0.009*SL 0.280 0.262 0.009*SL 0.079 0.054 0.013*SL 0.069 0.048 0.011*SL 0.321 0.303 0.009*SL 0.266 0.249 0.009*SL 0.079 0.054 0.013*SL 0.070 0.048 0.011*SL 0.377 0.359 0.009*SL 0.288 0.270 0.009*SL 0.079 0.054 0.013*SL 0.071 0.050 0.010*SL 0.401 0.383 0.009*SL 0.301 0.283 0.009*SL *Group1 *Group2 *Group3
Samsung ASIC
3-63
STDL130
NR6_LP/NR6D2_LP/NR6D4_LP
6-Input with 1X/2X/4X Drive Switching Characteristics
NR6D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.073 0.007*SL 0.054 0.005*SL 0.391 0.004*SL 0.258 0.004*SL 0.072 0.007*SL 0.055 0.005*SL 0.448 0.004*SL 0.279 0.004*SL 0.072 0.007*SL 0.055 0.005*SL 0.471 0.004*SL 0.292 0.004*SL 0.070 0.007*SL 0.056 0.005*SL 0.372 0.004*SL 0.261 0.004*SL 0.070 0.007*SL 0.056 0.005*SL 0.425 0.004*SL 0.282 0.004*SL 0.070 0.007*SL 0.056 0.005*SL 0.447 0.004*SL 0.295 0.004*SL
Parameter
Delay [ns]
Group3*
0.063 0.007*SL 0.051 0.005*SL 0.410 0.003*SL 0.276 0.003*SL 0.063 0.007*SL 0.050 0.005*SL 0.467 0.003*SL 0.297 0.003*SL 0.063 0.007*SL 0.052 0.005*SL 0.490 0.003*SL 0.310 0.003*SL 0.062 0.007*SL 0.051 0.005*SL 0.391 0.003*SL 0.280 0.003*SL 0.062 0.007*SL 0.051 0.005*SL 0.444 0.003*SL 0.300 0.003*SL 0.062 0.007*SL 0.052 0.005*SL 0.466 0.003*SL 0.313 0.003*SL
0.085 0.070 0.007*SL 0.061 0.049 0.006*SL 0.395 0.382 0.006*SL 0.261 0.251 0.005*SL 0.085 0.071 0.007*SL 0.061 0.049 0.006*SL 0.451 0.439 0.006*SL 0.283 0.272 0.005*SL 0.085 0.071 0.007*SL 0.062 0.050 0.006*SL 0.475 0.462 0.006*SL 0.296 0.285 0.005*SL 0.083 0.068 0.007*SL 0.063 0.050 0.006*SL 0.376 0.363 0.006*SL 0.265 0.254 0.005*SL 0.082 0.068 0.007*SL 0.063 0.051 0.006*SL 0.429 0.417 0.006*SL 0.285 0.275 0.005*SL 0.082 0.068 0.007*SL 0.064 0.052 0.006*SL 0.451 0.439 0.006*SL 0.298 0.287 0.005*SL *Group1 *Group2 *Group3
STDL130
3-64
Samsung ASIC
NR8_LP/NR8D2_LP/NR8D4_LP
8-Input with 1X/2X/4X Drive Logic Symbol Truth Table
Other States
Cell Data
Input Load (SL) NR8_LP NR8D2_LP NR8D4_LP Gate Count NR8_LP 5.33 NR8D2_LP 5.67 NR8D4_LP 6.33
Samsung ASIC
3-65
STDL130
NR8_LP/NR8D2_LP/NR8D4_LP
8-Input with 1X/2X/4X Drive Switching Characteristics
NR8_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.056 0.028*SL 0.054 0.019*SL 0.318 0.014*SL 0.254 0.011*SL 0.056 0.028*SL 0.052 0.019*SL 0.372 0.014*SL 0.275 0.011*SL 0.056 0.028*SL 0.055 0.019*SL 0.392 0.014*SL 0.286 0.011*SL 0.056 0.028*SL 0.055 0.019*SL 0.320 0.014*SL 0.270 0.011*SL 0.057 0.027*SL 0.055 0.019*SL 0.369 0.014*SL 0.290 0.011*SL 0.057 0.027*SL 0.057 0.019*SL 0.392 0.014*SL 0.303 0.011*SL 0.055 0.028*SL 0.058 0.019*SL 0.294 0.014*SL 0.266 0.012*SL 0.055 0.028*SL 0.058 0.019*SL 0.315 0.014*SL 0.281 0.012*SL
Parameter
Delay [ns]
Group3*
0.045 0.028*SL 0.042 0.020*SL 0.322 0.013*SL 0.262 0.011*SL 0.045 0.028*SL 0.042 0.020*SL 0.376 0.013*SL 0.284 0.011*SL 0.045 0.028*SL 0.043 0.020*SL 0.397 0.013*SL 0.295 0.011*SL 0.045 0.028*SL 0.043 0.020*SL 0.324 0.013*SL 0.280 0.011*SL 0.045 0.028*SL 0.044 0.020*SL 0.373 0.013*SL 0.300 0.011*SL 0.045 0.028*SL 0.044 0.020*SL 0.396 0.013*SL 0.312 0.011*SL 0.044 0.028*SL 0.046 0.020*SL 0.298 0.013*SL 0.277 0.011*SL 0.044 0.028*SL 0.046 0.020*SL 0.319 0.013*SL 0.291 0.011*SL
0.115 0.063 0.026*SL 0.090 0.051 0.020*SL 0.341 0.309 0.016*SL 0.270 0.242 0.014*SL 0.115 0.063 0.026*SL 0.090 0.052 0.019*SL 0.394 0.363 0.016*SL 0.292 0.263 0.014*SL 0.115 0.063 0.026*SL 0.093 0.055 0.019*SL 0.415 0.384 0.016*SL 0.303 0.274 0.014*SL 0.115 0.063 0.026*SL 0.093 0.055 0.019*SL 0.342 0.311 0.016*SL 0.287 0.258 0.014*SL 0.115 0.062 0.026*SL 0.094 0.056 0.019*SL 0.391 0.359 0.016*SL 0.307 0.278 0.014*SL 0.115 0.062 0.026*SL 0.094 0.056 0.019*SL 0.414 0.383 0.016*SL 0.320 0.291 0.014*SL 0.113 0.061 0.026*SL 0.095 0.058 0.019*SL 0.316 0.285 0.016*SL 0.283 0.253 0.015*SL 0.113 0.061 0.026*SL 0.096 0.058 0.019*SL 0.337 0.306 0.016*SL 0.297 0.268 0.015*SL *Group3 *Group1 *Group2
STDL130
3-66
Samsung ASIC
NR8_LP/NR8D2_LP/NR8D4_LP
8-Input with 1X/2X/4X Drive Switching Characteristics
NR8D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.072 0.013*SL 0.058 0.010*SL 0.364 0.008*SL 0.262 0.007*SL 0.072 0.013*SL 0.057 0.010*SL 0.418 0.008*SL 0.283 0.007*SL 0.072 0.013*SL 0.059 0.010*SL 0.439 0.008*SL 0.294 0.007*SL 0.069 0.014*SL 0.059 0.010*SL 0.354 0.008*SL 0.270 0.007*SL 0.071 0.013*SL 0.060 0.010*SL 0.403 0.008*SL 0.290 0.007*SL 0.072 0.013*SL 0.060 0.010*SL 0.426 0.008*SL 0.303 0.007*SL 0.070 0.013*SL 0.062 0.010*SL 0.335 0.008*SL 0.267 0.007*SL 0.070 0.013*SL 0.061 0.010*SL 0.355 0.008*SL 0.281 0.007*SL
Parameter
Delay [ns]
Group3*
0.062 0.014*SL 0.053 0.010*SL 0.377 0.007*SL 0.276 0.006*SL 0.062 0.014*SL 0.053 0.010*SL 0.431 0.007*SL 0.297 0.006*SL 0.062 0.014*SL 0.053 0.010*SL 0.452 0.007*SL 0.309 0.006*SL 0.062 0.014*SL 0.055 0.010*SL 0.368 0.007*SL 0.285 0.006*SL 0.062 0.014*SL 0.055 0.010*SL 0.416 0.007*SL 0.305 0.006*SL 0.062 0.014*SL 0.055 0.010*SL 0.439 0.007*SL 0.318 0.006*SL 0.060 0.014*SL 0.057 0.010*SL 0.348 0.007*SL 0.282 0.006*SL 0.060 0.014*SL 0.058 0.010*SL 0.368 0.007*SL 0.296 0.006*SL
0.097 0.069 0.014*SL 0.075 0.054 0.011*SL 0.374 0.353 0.010*SL 0.270 0.252 0.009*SL 0.097 0.069 0.014*SL 0.074 0.052 0.011*SL 0.428 0.407 0.010*SL 0.291 0.273 0.009*SL 0.097 0.069 0.014*SL 0.076 0.055 0.011*SL 0.449 0.428 0.010*SL 0.303 0.285 0.009*SL 0.097 0.071 0.013*SL 0.076 0.055 0.011*SL 0.364 0.343 0.010*SL 0.279 0.260 0.009*SL 0.097 0.070 0.014*SL 0.076 0.053 0.011*SL 0.413 0.392 0.010*SL 0.299 0.280 0.009*SL 0.098 0.070 0.014*SL 0.077 0.056 0.011*SL 0.436 0.416 0.010*SL 0.311 0.293 0.009*SL 0.095 0.066 0.014*SL 0.079 0.058 0.011*SL 0.345 0.325 0.010*SL 0.275 0.256 0.009*SL 0.095 0.066 0.014*SL 0.079 0.058 0.011*SL 0.365 0.344 0.010*SL 0.289 0.270 0.009*SL *Group3 *Group1 *Group2
Samsung ASIC
3-67
STDL130
NR8_LP/NR8D2_LP/NR8D4_LP
8-Input with 1X/2X/4X Drive Switching Characteristics
NR8D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.091 0.007*SL 0.058 0.005*SL 0.471 0.005*SL 0.276 0.004*SL 0.092 0.007*SL 0.059 0.005*SL 0.528 0.005*SL 0.298 0.004*SL 0.092 0.007*SL 0.059 0.005*SL 0.548 0.005*SL 0.310 0.004*SL 0.091 0.007*SL 0.059 0.005*SL 0.446 0.005*SL 0.275 0.004*SL 0.090 0.007*SL 0.058 0.005*SL 0.499 0.005*SL 0.296 0.004*SL 0.089 0.007*SL 0.059 0.005*SL 0.522 0.005*SL 0.309 0.004*SL 0.090 0.007*SL 0.060 0.005*SL 0.420 0.005*SL 0.265 0.004*SL 0.089 0.007*SL 0.060 0.005*SL 0.440 0.005*SL 0.279 0.004*SL
Parameter
Delay [ns]
Group3*
0.093 0.007*SL 0.057 0.005*SL 0.501 0.004*SL 0.296 0.003*SL 0.093 0.007*SL 0.057 0.005*SL 0.558 0.004*SL 0.318 0.003*SL 0.093 0.007*SL 0.058 0.005*SL 0.579 0.004*SL 0.330 0.003*SL 0.093 0.007*SL 0.058 0.005*SL 0.476 0.004*SL 0.296 0.003*SL 0.093 0.007*SL 0.058 0.005*SL 0.529 0.004*SL 0.316 0.003*SL 0.092 0.007*SL 0.058 0.005*SL 0.552 0.004*SL 0.330 0.003*SL 0.091 0.007*SL 0.060 0.005*SL 0.450 0.004*SL 0.286 0.003*SL 0.090 0.007*SL 0.059 0.005*SL 0.470 0.004*SL 0.300 0.003*SL
0.101 0.084 0.009*SL 0.066 0.053 0.006*SL 0.475 0.460 0.007*SL 0.280 0.269 0.005*SL 0.101 0.084 0.009*SL 0.066 0.053 0.006*SL 0.532 0.518 0.007*SL 0.301 0.290 0.005*SL 0.102 0.084 0.009*SL 0.066 0.053 0.006*SL 0.553 0.538 0.007*SL 0.313 0.302 0.006*SL 0.100 0.082 0.009*SL 0.067 0.056 0.006*SL 0.450 0.436 0.007*SL 0.279 0.268 0.006*SL 0.100 0.083 0.009*SL 0.067 0.057 0.005*SL 0.503 0.488 0.007*SL 0.300 0.289 0.006*SL 0.100 0.083 0.009*SL 0.068 0.057 0.005*SL 0.526 0.511 0.007*SL 0.313 0.302 0.006*SL 0.100 0.083 0.009*SL 0.069 0.057 0.006*SL 0.425 0.410 0.007*SL 0.269 0.258 0.006*SL 0.100 0.084 0.008*SL 0.069 0.058 0.005*SL 0.444 0.430 0.007*SL 0.283 0.271 0.006*SL *Group3 *Group1 *Group2
STDL130
3-68
Samsung ASIC
2-Input with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
OR2_LP Input Load (SL) OR2D2_LP OR2D4_LP OR2D8_LP OR2_LP 1.67 Gate Count OR2D2_LP OR2D4_LP OR2D8_LP 1.67 2.33 4.33
Switching Characteristics
OR2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.042 0.028*SL 0.064 0.019*SL 0.124 0.013*SL 0.209 0.012*SL 0.043 0.028*SL 0.063 0.019*SL 0.140 0.013*SL 0.234 0.012*SL
Parameter
Delay [ns]
Group3*
0.037 0.028*SL 0.054 0.020*SL 0.125 0.013*SL 0.223 0.011*SL 0.038 0.028*SL 0.054 0.020*SL 0.142 0.013*SL 0.247 0.011*SL
0.101 0.048 0.027*SL 0.101 0.062 0.020*SL 0.149 0.122 0.014*SL 0.226 0.195 0.015*SL 0.106 0.056 0.025*SL 0.100 0.060 0.020*SL 0.166 0.138 0.014*SL 0.250 0.219 0.015*SL *Group1 *Group2 *Group3
OR2D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.037 0.014*SL 0.061 0.010*SL 0.130 0.007*SL 0.209 0.007*SL 0.038 0.014*SL 0.062 0.010*SL 0.145 0.007*SL 0.231 0.007*SL
Group3*
0.031 0.014*SL 0.061 0.010*SL 0.132 0.007*SL 0.228 0.006*SL 0.032 0.014*SL 0.061 0.010*SL 0.148 0.007*SL 0.249 0.006*SL
0.068 0.044 0.012*SL 0.078 0.056 0.011*SL 0.142 0.126 0.008*SL 0.217 0.197 0.010*SL 0.067 0.041 0.013*SL 0.077 0.053 0.012*SL 0.157 0.141 0.008*SL 0.238 0.218 0.010*SL *Group3 *Group1 *Group2
Samsung ASIC
3-69
STDL130
2-Input with 1X/2X/4X/8X Drive Switching Characteristics
OR2D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.053 0.007*SL 0.084 0.005*SL 0.162 0.004*SL 0.273 0.004*SL 0.054 0.007*SL 0.082 0.005*SL 0.176 0.004*SL 0.295 0.004*SL
Parameter
Delay [ns]
Group3*
0.041 0.007*SL 0.093 0.005*SL 0.170 0.003*SL 0.306 0.003*SL 0.042 0.007*SL 0.093 0.005*SL 0.185 0.003*SL 0.327 0.003*SL
0.066 0.052 0.007*SL 0.090 0.075 0.007*SL 0.166 0.156 0.005*SL 0.276 0.262 0.007*SL 0.068 0.055 0.006*SL 0.089 0.076 0.007*SL 0.180 0.170 0.005*SL 0.298 0.283 0.007*SL *Group1 *Group2 *Group3
OR2D8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.052 0.003*SL 0.078 0.003*SL 0.156 0.002*SL 0.262 0.002*SL 0.054 0.003*SL 0.078 0.003*SL 0.170 0.002*SL 0.284 0.002*SL
Group3*
0.041 0.004*SL 0.090 0.002*SL 0.166 0.002*SL 0.298 0.002*SL 0.041 0.004*SL 0.090 0.002*SL 0.181 0.002*SL 0.319 0.002*SL
0.057 0.049 0.004*SL 0.080 0.073 0.004*SL 0.157 0.152 0.003*SL 0.264 0.256 0.004*SL 0.058 0.049 0.004*SL 0.081 0.074 0.004*SL 0.172 0.166 0.003*SL 0.285 0.277 0.004*SL *Group3 *Group1 *Group2
STDL130
3-70
Samsung ASIC
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) Gate Count OR2B_LP OR2BD2_LP OR2BD4_LP OR2BD8_LP OR2B_LP OR2BD2_LP OR2BD4_LP OR2BD8_LP 2.00 2.33 3.00 4.67
Switching Characteristics
OR2B_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.037 0.029*SL 0.060 0.019*SL 0.213 0.014*SL 0.226 0.012*SL 0.037 0.029*SL 0.060 0.019*SL 0.135 0.014*SL 0.226 0.012*SL
Parameter
Delay [ns]
Group3*
0.032 0.029*SL 0.049 0.020*SL 0.214 0.014*SL 0.240 0.011*SL 0.033 0.029*SL 0.050 0.020*SL 0.136 0.014*SL 0.240 0.011*SL
0.096 0.040 0.028*SL 0.096 0.057 0.020*SL 0.239 0.211 0.014*SL 0.242 0.211 0.015*SL 0.098 0.044 0.027*SL 0.096 0.057 0.020*SL 0.161 0.132 0.014*SL 0.242 0.211 0.015*SL *Group1 *Group2 *Group3
OR2BD2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.039 0.014*SL 0.063 0.010*SL 0.235 0.007*SL 0.240 0.007*SL 0.040 0.014*SL 0.063 0.010*SL 0.147 0.007*SL 0.236 0.007*SL
Group3*
0.032 0.014*SL 0.062 0.010*SL 0.238 0.007*SL 0.259 0.006*SL 0.033 0.014*SL 0.063 0.010*SL 0.149 0.007*SL 0.256 0.006*SL
0.069 0.044 0.012*SL 0.079 0.057 0.011*SL 0.247 0.231 0.008*SL 0.248 0.228 0.010*SL 0.070 0.045 0.013*SL 0.080 0.057 0.011*SL 0.158 0.143 0.008*SL 0.245 0.225 0.010*SL *Group3 *Group1 *Group2
Samsung ASIC
3-71
STDL130
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
OR2BD4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.054 0.007*SL 0.084 0.005*SL 0.267 0.004*SL 0.305 0.004*SL 0.054 0.007*SL 0.083 0.005*SL 0.176 0.004*SL 0.300 0.004*SL
Parameter
Delay [ns]
Group3*
0.041 0.007*SL 0.094 0.005*SL 0.276 0.003*SL 0.338 0.003*SL 0.043 0.007*SL 0.094 0.005*SL 0.185 0.003*SL 0.333 0.003*SL
0.068 0.056 0.006*SL 0.091 0.077 0.007*SL 0.271 0.261 0.005*SL 0.308 0.294 0.007*SL 0.068 0.055 0.006*SL 0.090 0.076 0.007*SL 0.181 0.170 0.005*SL 0.304 0.290 0.007*SL *Group1 *Group2 *Group3
OR2BD8_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.055 0.003*SL 0.078 0.003*SL 0.280 0.002*SL 0.302 0.002*SL 0.054 0.003*SL 0.078 0.003*SL 0.171 0.002*SL 0.284 0.002*SL
Group3*
0.043 0.004*SL 0.089 0.002*SL 0.292 0.002*SL 0.338 0.002*SL 0.041 0.004*SL 0.090 0.002*SL 0.182 0.002*SL 0.320 0.002*SL
0.062 0.055 0.003*SL 0.080 0.072 0.004*SL 0.282 0.276 0.003*SL 0.304 0.296 0.004*SL 0.059 0.051 0.004*SL 0.081 0.073 0.004*SL 0.173 0.167 0.003*SL 0.286 0.278 0.004*SL *Group3 *Group1 *Group2
STDL130
3-72
Samsung ASIC
OR3_LP/OR3D2_LP/OR3D4_LP
3-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
OR3_LP Input Load (SL) OR3D2_LP OR3D4_LP OR3_LP 2.00 Gate Count OR3D2_LP 2.33 OR3D4_LP 3.00
Switching Characteristics
OR3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.040 0.028*SL 0.078 0.019*SL 0.136 0.013*SL 0.229 0.013*SL 0.043 0.028*SL 0.078 0.019*SL 0.158 0.013*SL 0.286 0.013*SL 0.048 0.028*SL 0.079 0.019*SL 0.169 0.014*SL 0.309 0.013*SL
Parameter
Delay [ns]
Group3*
0.034 0.028*SL 0.077 0.019*SL 0.138 0.013*SL 0.256 0.011*SL 0.036 0.028*SL 0.078 0.019*SL 0.160 0.013*SL 0.313 0.011*SL 0.041 0.028*SL 0.078 0.019*SL 0.173 0.013*SL 0.336 0.011*SL
0.100 0.047 0.026*SL 0.112 0.069 0.021*SL 0.162 0.134 0.014*SL 0.245 0.210 0.018*SL 0.101 0.047 0.027*SL 0.113 0.070 0.021*SL 0.183 0.155 0.014*SL 0.301 0.266 0.018*SL 0.107 0.055 0.026*SL 0.113 0.070 0.021*SL 0.193 0.164 0.015*SL 0.325 0.289 0.018*SL *Group3 *Group1 *Group2
Samsung ASIC
3-73
STDL130
OR3_LP/OR3D2_LP/OR3D4_LP
3-Input with 1X/2X/4X Drive Switching Characteristics
OR3D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.045 0.014*SL 0.085 0.010*SL 0.156 0.007*SL 0.260 0.008*SL 0.047 0.014*SL 0.085 0.010*SL 0.178 0.007*SL 0.317 0.008*SL 0.054 0.013*SL 0.085 0.010*SL 0.189 0.007*SL 0.340 0.008*SL
Parameter
Delay [ns]
Group3*
0.036 0.014*SL 0.096 0.010*SL 0.160 0.007*SL 0.290 0.006*SL 0.039 0.014*SL 0.096 0.010*SL 0.182 0.007*SL 0.347 0.006*SL 0.042 0.014*SL 0.097 0.010*SL 0.196 0.007*SL 0.370 0.006*SL
0.074 0.047 0.013*SL 0.100 0.074 0.013*SL 0.167 0.150 0.008*SL 0.269 0.245 0.012*SL 0.076 0.052 0.012*SL 0.100 0.074 0.013*SL 0.188 0.171 0.009*SL 0.325 0.301 0.012*SL 0.080 0.053 0.014*SL 0.100 0.073 0.013*SL 0.199 0.181 0.009*SL 0.349 0.325 0.012*SL *Group1 *Group2 *Group3
OR3D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.063 0.007*SL 0.112 0.006*SL 0.193 0.004*SL 0.353 0.005*SL 0.066 0.007*SL 0.112 0.006*SL 0.214 0.004*SL 0.410 0.005*SL 0.069 0.007*SL 0.112 0.006*SL 0.226 0.004*SL 0.433 0.005*SL
Group3*
0.051 0.007*SL 0.137 0.005*SL 0.206 0.003*SL 0.398 0.004*SL 0.053 0.007*SL 0.137 0.005*SL 0.228 0.003*SL 0.455 0.004*SL 0.059 0.007*SL 0.136 0.005*SL 0.243 0.003*SL 0.478 0.004*SL
0.076 0.062 0.007*SL 0.119 0.102 0.008*SL 0.197 0.185 0.006*SL 0.357 0.341 0.008*SL 0.079 0.065 0.007*SL 0.119 0.102 0.008*SL 0.218 0.206 0.006*SL 0.414 0.398 0.008*SL 0.082 0.068 0.007*SL 0.119 0.104 0.008*SL 0.230 0.218 0.006*SL 0.437 0.421 0.008*SL *Group1 *Group2 *Group3
STDL130
3-74
Samsung ASIC
OR4_LP/OR4D2_LP/OR4D4_LP
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
OR4_LP Input Load (SL) OR4D2_LP Gate Count OR4D2_LP 3.00 OR4D4_LP
OR4_LP 2.67
OR4D4_LP 4.33
Switching Characteristics
OR4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.048 0.029*SL 0.078 0.027*SL 0.132 0.014*SL 0.225 0.016*SL 0.050 0.029*SL 0.077 0.027*SL 0.147 0.014*SL 0.244 0.016*SL 0.058 0.029*SL 0.067 0.028*SL 0.138 0.014*SL 0.219 0.015*SL 0.059 0.029*SL 0.067 0.028*SL 0.152 0.014*SL 0.239 0.015*SL
Parameter
Delay [ns]
Group3*
0.044 0.029*SL 0.067 0.028*SL 0.134 0.014*SL 0.234 0.015*SL 0.046 0.029*SL 0.067 0.028*SL 0.148 0.014*SL 0.254 0.015*SL 0.054 0.029*SL 0.060 0.028*SL 0.139 0.014*SL 0.227 0.015*SL 0.055 0.029*SL 0.060 0.028*SL 0.154 0.014*SL 0.247 0.015*SL
0.108 0.053 0.028*SL 0.133 0.078 0.027*SL 0.158 0.130 0.014*SL 0.249 0.212 0.018*SL 0.109 0.054 0.028*SL 0.132 0.077 0.027*SL 0.173 0.144 0.014*SL 0.269 0.232 0.018*SL 0.118 0.063 0.028*SL 0.123 0.068 0.027*SL 0.164 0.136 0.014*SL 0.245 0.210 0.018*SL 0.119 0.064 0.028*SL 0.122 0.066 0.028*SL 0.178 0.150 0.014*SL 0.265 0.230 0.018*SL *Group1 *Group2 *Group3
Samsung ASIC
3-75
STDL130
OR4_LP/OR4D2_LP/OR4D4_LP
4-Input with 1X/2X/4X Drive Switching Characteristics
OR4D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.052 0.014*SL 0.081 0.014*SL 0.137 0.007*SL 0.232 0.009*SL 0.053 0.014*SL 0.081 0.014*SL 0.151 0.007*SL 0.252 0.009*SL 0.060 0.014*SL 0.072 0.014*SL 0.146 0.007*SL 0.232 0.008*SL 0.061 0.014*SL 0.072 0.014*SL 0.159 0.007*SL 0.252 0.008*SL
Parameter
Delay [ns]
Group3*
0.046 0.014*SL 0.078 0.014*SL 0.139 0.007*SL 0.247 0.008*SL 0.046 0.014*SL 0.078 0.014*SL 0.153 0.007*SL 0.267 0.008*SL 0.055 0.014*SL 0.068 0.014*SL 0.147 0.007*SL 0.244 0.008*SL 0.056 0.014*SL 0.068 0.014*SL 0.161 0.007*SL 0.263 0.008*SL
0.082 0.056 0.013*SL 0.108 0.079 0.014*SL 0.150 0.135 0.008*SL 0.245 0.224 0.011*SL 0.081 0.053 0.014*SL 0.107 0.079 0.014*SL 0.163 0.148 0.008*SL 0.265 0.243 0.011*SL 0.094 0.071 0.011*SL 0.097 0.068 0.015*SL 0.159 0.144 0.007*SL 0.246 0.226 0.010*SL 0.090 0.062 0.014*SL 0.097 0.068 0.015*SL 0.172 0.157 0.007*SL 0.265 0.245 0.010*SL *Group1 *Group2 *Group3
OR4D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.055 0.007*SL 0.049 0.005*SL 0.315 0.004*SL 0.356 0.003*SL 0.054 0.007*SL 0.051 0.005*SL 0.331 0.004*SL 0.376 0.003*SL 0.053 0.007*SL 0.052 0.005*SL 0.328 0.004*SL 0.357 0.003*SL 0.055 0.007*SL 0.051 0.005*SL 0.344 0.004*SL 0.377 0.003*SL
Group3*
0.042 0.007*SL 0.048 0.005*SL 0.324 0.003*SL 0.373 0.003*SL 0.042 0.007*SL 0.047 0.005*SL 0.340 0.003*SL 0.392 0.003*SL 0.042 0.007*SL 0.048 0.005*SL 0.337 0.003*SL 0.374 0.003*SL 0.042 0.007*SL 0.048 0.005*SL 0.353 0.003*SL 0.393 0.003*SL
0.068 0.054 0.007*SL 0.058 0.048 0.005*SL 0.320 0.309 0.005*SL 0.360 0.350 0.005*SL 0.067 0.054 0.007*SL 0.059 0.049 0.005*SL 0.335 0.325 0.005*SL 0.379 0.369 0.005*SL 0.067 0.055 0.006*SL 0.059 0.048 0.006*SL 0.332 0.322 0.005*SL 0.361 0.351 0.005*SL 0.067 0.053 0.007*SL 0.059 0.048 0.006*SL 0.348 0.338 0.005*SL 0.380 0.370 0.005*SL *Group1 *Group2 *Group3
STDL130
3-76
Samsung ASIC
OR5_LP/OR5D2_LP/OR5D4_LP
5-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
OR5_LP OR5_LP 3.00 Input Load (SL) OR5D2_LP Gate Count OR5D2_LP 3.67 OR5D4_LP OR5D4_LP 5.00
Switching Characteristics
OR5_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.051 0.029*SL 0.094 0.027*SL 0.145 0.014*SL 0.249 0.016*SL 0.052 0.029*SL 0.094 0.027*SL 0.165 0.014*SL 0.298 0.016*SL 0.058 0.028*SL 0.094 0.027*SL 0.176 0.014*SL 0.322 0.016*SL 0.058 0.029*SL 0.066 0.027*SL 0.136 0.014*SL 0.216 0.015*SL 0.059 0.029*SL 0.066 0.027*SL 0.152 0.014*SL 0.236 0.015*SL
Parameter
Delay [ns]
Group3*
0.045 0.029*SL 0.087 0.027*SL 0.147 0.014*SL 0.271 0.015*SL 0.046 0.029*SL 0.087 0.027*SL 0.167 0.014*SL 0.319 0.015*SL 0.051 0.029*SL 0.087 0.027*SL 0.180 0.014*SL 0.343 0.015*SL 0.053 0.029*SL 0.060 0.028*SL 0.137 0.013*SL 0.224 0.015*SL 0.054 0.029*SL 0.059 0.028*SL 0.153 0.013*SL 0.244 0.015*SL
0.111 0.056 0.027*SL 0.145 0.089 0.028*SL 0.171 0.143 0.014*SL 0.273 0.232 0.020*SL 0.111 0.056 0.028*SL 0.145 0.088 0.028*SL 0.190 0.162 0.014*SL 0.321 0.280 0.020*SL 0.117 0.062 0.027*SL 0.145 0.088 0.028*SL 0.202 0.172 0.015*SL 0.345 0.304 0.020*SL 0.117 0.062 0.028*SL 0.121 0.067 0.027*SL 0.163 0.135 0.014*SL 0.242 0.207 0.017*SL 0.118 0.063 0.028*SL 0.121 0.066 0.027*SL 0.178 0.149 0.014*SL 0.262 0.227 0.017*SL *Group3 *Group1 *Group2
Samsung ASIC
3-77
STDL130
OR5_LP/OR5D2_LP/OR5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
OR5D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.061 0.014*SL 0.106 0.014*SL 0.169 0.007*SL 0.290 0.010*SL 0.064 0.014*SL 0.106 0.014*SL 0.189 0.007*SL 0.339 0.010*SL 0.066 0.014*SL 0.106 0.014*SL 0.201 0.007*SL 0.363 0.010*SL 0.060 0.014*SL 0.072 0.014*SL 0.143 0.007*SL 0.232 0.008*SL 0.062 0.014*SL 0.072 0.014*SL 0.156 0.007*SL 0.252 0.008*SL
Parameter
Delay [ns]
Group3*
0.052 0.014*SL 0.111 0.014*SL 0.173 0.007*SL 0.315 0.008*SL 0.054 0.014*SL 0.111 0.014*SL 0.193 0.007*SL 0.364 0.008*SL 0.059 0.014*SL 0.111 0.014*SL 0.207 0.007*SL 0.388 0.008*SL 0.055 0.014*SL 0.070 0.014*SL 0.145 0.007*SL 0.244 0.008*SL 0.056 0.014*SL 0.070 0.014*SL 0.158 0.007*SL 0.263 0.008*SL
0.090 0.064 0.013*SL 0.130 0.099 0.016*SL 0.181 0.165 0.008*SL 0.303 0.278 0.013*SL 0.092 0.065 0.013*SL 0.130 0.099 0.016*SL 0.201 0.184 0.008*SL 0.352 0.327 0.013*SL 0.096 0.071 0.013*SL 0.130 0.099 0.016*SL 0.213 0.196 0.009*SL 0.376 0.351 0.013*SL 0.090 0.063 0.013*SL 0.098 0.068 0.015*SL 0.156 0.141 0.007*SL 0.246 0.226 0.010*SL 0.091 0.064 0.013*SL 0.098 0.069 0.014*SL 0.169 0.155 0.007*SL 0.265 0.245 0.010*SL *Group1 *Group2 *Group3
STDL130
3-78
Samsung ASIC
OR5_LP/OR5D2_LP/OR5D4_LP
5-Input with 1X/2X/4X Drive Switching Characteristics
OR5D4_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.054 0.007*SL 0.052 0.005*SL 0.330 0.004*SL 0.387 0.003*SL 0.052 0.007*SL 0.052 0.005*SL 0.352 0.004*SL 0.443 0.003*SL 0.054 0.007*SL 0.050 0.005*SL 0.364 0.004*SL 0.466 0.003*SL 0.053 0.007*SL 0.049 0.005*SL 0.334 0.004*SL 0.361 0.003*SL 0.054 0.007*SL 0.052 0.005*SL 0.351 0.004*SL 0.385 0.003*SL
Parameter
Delay [ns]
Group3*
0.041 0.007*SL 0.047 0.005*SL 0.339 0.003*SL 0.403 0.003*SL 0.042 0.007*SL 0.046 0.005*SL 0.361 0.003*SL 0.459 0.003*SL 0.041 0.007*SL 0.046 0.005*SL 0.373 0.003*SL 0.482 0.003*SL 0.042 0.007*SL 0.048 0.005*SL 0.343 0.003*SL 0.377 0.003*SL 0.041 0.007*SL 0.046 0.005*SL 0.360 0.003*SL 0.401 0.003*SL
0.068 0.055 0.006*SL 0.059 0.047 0.006*SL 0.334 0.324 0.005*SL 0.390 0.380 0.005*SL 0.067 0.054 0.006*SL 0.059 0.047 0.006*SL 0.357 0.347 0.005*SL 0.446 0.436 0.005*SL 0.066 0.052 0.007*SL 0.059 0.048 0.005*SL 0.368 0.358 0.005*SL 0.470 0.459 0.005*SL 0.067 0.056 0.006*SL 0.059 0.049 0.005*SL 0.339 0.328 0.005*SL 0.364 0.354 0.005*SL 0.068 0.056 0.006*SL 0.059 0.047 0.006*SL 0.356 0.345 0.005*SL 0.389 0.378 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-79
STDL130
XN2_LP/XN2D2_LP/XN2D4_LP
2-Input Exclusive-NOR with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
XN2_LP Input Load (SL) XN2D2_LP XN2D4_LP XN2_LP 3.00 Gate Count XN2D2_LP 3.33 XN2D4_LP 4.00
Switching Characteristics
XN2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.058 0.027*SL 0.088 0.019*SL 0.258 0.013*SL 0.310 0.012*SL 0.056 0.027*SL 0.083 0.019*SL 0.231 0.013*SL 0.232 0.013*SL
Group3*
0.045 0.028*SL 0.081 0.019*SL 0.260 0.013*SL 0.326 0.011*SL 0.045 0.028*SL 0.078 0.019*SL 0.234 0.013*SL 0.259 0.011*SL
0.115 0.062 0.026*SL 0.123 0.083 0.020*SL 0.282 0.252 0.015*SL 0.326 0.295 0.016*SL 0.113 0.060 0.027*SL 0.116 0.074 0.021*SL 0.256 0.226 0.015*SL 0.247 0.212 0.018*SL *Group1 *Group2 *Group3
STDL130
3-80
Samsung ASIC
XN2_LP/XN2D2_LP/XN2D4_LP
2-Input Exclusive-NOR with 1X/2X/4X Drive Switching Characteristics
XN2D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.068 0.013*SL 0.100 0.010*SL 0.275 0.007*SL 0.341 0.008*SL 0.067 0.013*SL 0.096 0.010*SL 0.248 0.007*SL 0.255 0.009*SL
Parameter
Delay [ns]
Group3*
0.060 0.014*SL 0.109 0.010*SL 0.282 0.007*SL 0.365 0.006*SL 0.059 0.014*SL 0.106 0.010*SL 0.256 0.007*SL 0.287 0.006*SL
0.093 0.066 0.014*SL 0.114 0.088 0.013*SL 0.285 0.266 0.009*SL 0.349 0.327 0.011*SL 0.093 0.065 0.014*SL 0.111 0.085 0.013*SL 0.258 0.240 0.009*SL 0.263 0.237 0.013*SL *Group1 *Group2 *Group3
XN2D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.086 0.007*SL 0.128 0.006*SL 0.313 0.004*SL 0.419 0.005*SL 0.087 0.007*SL 0.126 0.006*SL 0.285 0.004*SL 0.320 0.006*SL
Group3*
0.089 0.007*SL 0.156 0.005*SL 0.333 0.003*SL 0.458 0.003*SL 0.088 0.007*SL 0.154 0.005*SL 0.304 0.003*SL 0.372 0.004*SL
0.098 0.082 0.008*SL 0.135 0.118 0.008*SL 0.317 0.305 0.006*SL 0.422 0.407 0.008*SL 0.098 0.082 0.008*SL 0.134 0.119 0.008*SL 0.289 0.277 0.006*SL 0.325 0.307 0.009*SL *Group1 *Group2 *Group3
Samsung ASIC
3-81
STDL130
XN3_LP/XN3D2_LP/XN3D4_LP
3-Input Exclusive-NOR with 1X/2X/4X Drive Logic Symbol Truth Table
Cell Data
XN3_LP Input Load (SL) XN3D2_LP XN3D4_LP XN3_LP 5.00 Gate Count XN3D2_LP 5.33 XN3D4_LP 6.00
Switching Characteristics
XN3_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.082 0.028*SL 0.111 0.022*SL 0.277 0.015*SL 0.277 0.016*SL 0.089 0.027*SL 0.130 0.020*SL 0.430 0.014*SL 0.518 0.015*SL 0.088 0.027*SL 0.068 0.020*SL 0.354 0.014*SL 0.434 0.012*SL
Parameter
Delay [ns]
Group3*
0.072 0.028*SL 0.136 0.020*SL 0.297 0.014*SL 0.327 0.013*SL 0.076 0.028*SL 0.130 0.020*SL 0.433 0.014*SL 0.564 0.012*SL 0.076 0.028*SL 0.058 0.020*SL 0.365 0.014*SL 0.451 0.011*SL
0.134 0.076 0.029*SL 0.144 0.091 0.027*SL 0.298 0.259 0.019*SL 0.295 0.250 0.022*SL 0.140 0.082 0.029*SL 0.164 0.120 0.022*SL 0.454 0.423 0.015*SL 0.533 0.488 0.022*SL 0.140 0.082 0.029*SL 0.106 0.065 0.020*SL 0.375 0.340 0.018*SL 0.451 0.418 0.017*SL *Group1 *Group2 *Group3
STDL130
3-82
Samsung ASIC
XN3_LP/XN3D2_LP/XN3D4_LP
3-Input Exclusive-NOR with 1X/2X/4X Drive Switching Characteristics
XN3D2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.086 0.014*SL 0.129 0.012*SL 0.293 0.009*SL 0.319 0.011*SL 0.090 0.014*SL 0.140 0.011*SL 0.447 0.007*SL 0.548 0.010*SL 0.090 0.014*SL 0.077 0.010*SL 0.371 0.008*SL 0.463 0.008*SL
Parameter
Delay [ns]
Group3*
0.092 0.014*SL 0.161 0.010*SL 0.321 0.007*SL 0.367 0.008*SL 0.096 0.014*SL 0.156 0.010*SL 0.455 0.007*SL 0.592 0.007*SL 0.096 0.014*SL 0.080 0.010*SL 0.392 0.007*SL 0.488 0.006*SL
0.110 0.078 0.016*SL 0.145 0.111 0.017*SL 0.304 0.278 0.013*SL 0.329 0.296 0.016*SL 0.114 0.081 0.016*SL 0.153 0.124 0.015*SL 0.457 0.438 0.010*SL 0.556 0.525 0.016*SL 0.114 0.082 0.016*SL 0.093 0.069 0.012*SL 0.381 0.358 0.012*SL 0.471 0.448 0.011*SL *Group1 *Group2 *Group3
XN3D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.108 0.008*SL 0.194 0.007*SL 0.352 0.006*SL 0.438 0.007*SL 0.109 0.008*SL 0.170 0.006*SL 0.486 0.004*SL 0.642 0.006*SL 0.095 0.007*SL 0.214 0.007*SL 0.422 0.005*SL 0.568 0.007*SL
Group3*
0.130 0.007*SL 0.240 0.005*SL 0.396 0.004*SL 0.509 0.005*SL 0.131 0.007*SL 0.208 0.005*SL 0.507 0.003*SL 0.705 0.004*SL 0.103 0.007*SL 0.258 0.005*SL 0.457 0.004*SL 0.639 0.005*SL
0.119 0.099 0.010*SL 0.202 0.182 0.010*SL 0.357 0.340 0.008*SL 0.443 0.421 0.011*SL 0.120 0.100 0.010*SL 0.177 0.159 0.009*SL 0.490 0.477 0.006*SL 0.647 0.626 0.010*SL 0.105 0.087 0.009*SL 0.221 0.201 0.010*SL 0.427 0.411 0.008*SL 0.573 0.551 0.011*SL *Group1 *Group2 *Group3
Samsung ASIC
3-83
STDL130
XO2_LP/XO2D2_LP/XO2D4_LP
2-Input Exclusive-OR with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
XO2_LP Input Load (SL) XO2D2_LP XO2D4_LP XO2_LP 3.00 Gate Count XO2D2_LP 3.33 XO2D4_LP 4.00
STDL130
3-84
Samsung ASIC
XO2_LP/XO2D2_LP/XO2D4_LP
2-Input Exclusive-OR with 1X/2X/4X Drive Switching Characteristics
XO2_LP
Path
(Typical process, 25°C, 1.8V, tR/tF 0.20ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.059 0.027*SL 0.088 0.019*SL 0.298 0.014*SL 0.304 0.012*SL 0.058 0.027*SL 0.079 0.019*SL 0.243 0.014*SL 0.257 0.012*SL
Parameter
Delay [ns]
Group3*
0.045 0.028*SL 0.081 0.019*SL 0.302 0.013*SL 0.320 0.011*SL 0.045 0.028*SL 0.075 0.019*SL 0.248 0.013*SL 0.273 0.011*SL
0.115 0.062 0.026*SL 0.123 0.083 0.020*SL 0.320 0.289 0.016*SL 0.320 0.288 0.016*SL 0.115 0.062 0.026*SL 0.112 0.069 0.021*SL 0.265 0.233 0.016*SL 0.272 0.241 0.016*SL *Group1 *Group2 *Group3
XO2D2_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.069 0.013*SL 0.100 0.010*SL 0.322 0.008*SL 0.334 0.008*SL 0.069 0.013*SL 0.093 0.010*SL 0.261 0.008*SL 0.287 0.008*SL
Group3*
0.058 0.014*SL 0.109 0.010*SL 0.335 0.007*SL 0.359 0.006*SL 0.058 0.014*SL 0.103 0.010*SL 0.275 0.007*SL 0.311 0.006*SL
0.095 0.067 0.014*SL 0.115 0.089 0.013*SL 0.331 0.310 0.010*SL 0.343 0.321 0.011*SL 0.093 0.064 0.014*SL 0.107 0.081 0.013*SL 0.270 0.249 0.011*SL 0.295 0.273 0.011*SL *Group1 *Group2 *Group3
XO2D4_LP
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.088 0.007*SL 0.127 0.

Cell Names Function Descriptions Cell Name AD2_LP AD2D2_LP AD2D4_

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