Cell Names Function Descriptions Cell Name AD2D2 AD2D4 AD2D8 AD2B
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LOGIC CELLS
Cell Names Function Descriptions
Cell Name AD2D2 AD2D4 AD2D8 AD2B AD2BD2 AD2BD4 AD2BD8 AD3D2 AD3D4 AD4D2 AD4D4 AD5D2 AD5D4 ND2D2 ND2D4 ND2D8 ND2B ND2BD2 ND2BD4 ND2BD8 ND3D2 ND3D4 ND3D8 ND3B ND3BD2 ND3BD4 ND3BD8 ND4D2 ND4D4 ND5D2 ND5D4 ND6D2 Function Description 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 2-Input NAND with Inverted Input, Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 3-Input NAND with Inverted Input, Drive 4-Input NAND with Drive 4-Input NAND with Drive 4-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 5-Input NAND with Drive 6-Input NAND with Drive 6-Input NAND with Drive
Samsung ASIC
STDH150
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name ND6D4 ND8D2 ND8D4 NR2A NR2D2 NR2D4 NR2D8 NR2B NR2BD2 NR2BD4 NR2BD8 NR3A NR3D2 NR3D4 NR4D2 NR4D4 NR5D2 NR5D4 NR6D2 NR6D4 NR8D2 NR8D4 OR2D2 OR2D4 OR2D8 OR2B OR2BD2 OR2BD4 OR2BD8 OR3D2 OR3D4 Function Description 6-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 8-Input NAND with Drive 2-Input with Drive 2-Input with P-Transistor, N-Transistor 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with P-Transistor, N-Transistor 3-Input with Drive 3-Input with Drive 4-Input with Drive 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 6-Input with Drive 6-Input with Drive 6-Input with Drive 8-Input with Drive 8-Input with Drive 8-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 2-Input with Inverted Input, Drive 3-Input with Drive 3-Input with Drive 3-Input with Drive 4-Input with Drive
STDH150
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OR4D2 OR4D4 OR5D2 OR5D4 XN2D2 XN2D4 XN2D8 XN3D2 XN3D4 XO2D2 XO2D4 XO2D8 XO3D2 XO3D4 AO21 AO21D2 AO21D4 AO211 AO211D2 AO211D4 AO2111 AO2111D2 AO22 AO22D2 AO22D4 AO22A AO22D2A AO221 AO221D2 AO221D4 AO222 AO222D2 AO222D4 AO222A AO222D2A AO2222 Function Description 4-Input with Drive 4-Input with Drive 5-Input with Drive 5-Input with Drive 5-Input with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 2-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 3-Input Exclusive-NOR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 2-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 3-Input Exclusive-OR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 2-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 3-NOR with Drive 2-AND into 4-NOR with Drive 2-AND into 4-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-ANDs into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-AND 2-NOR into 2-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Three 2-ANDs into 3-NOR with Drive Inverting 2-of-3 Majority with Drive Inverting 2-of-3 Majority with Drive Four 2-ANDs into 4-NOR with Drive
Samsung ASIC
STDH150
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name AO2222D2 AO2222D4 AO31 AO31D2 AO31D4 AO311 AO311D2 AO3111 AO3111D2 AO32 AO32D2 AO321 AO321D2 AO322 AO322D2 AO33 AO33D2 AO331 AO331D2 AO332 AO332D2 OA21 OA21D2 OA21D4 OA211 OA211D2 OA211D4 OA2111 OA2111D2 OA22 OA22D2 OA22D4 OA22A OA22D2A OA22D4A OA221 OA221D2 OA221D4 OA222 OA222D2 OA222D4 Function Description Four 2-ANDs into 4-NOR with Drive Four 2-ANDs into 4-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 2-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 3-NOR with Drive 3-AND into 4-NOR with Drive 3-AND into 4-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 2-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-AND into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-AND 2-ANDs into 3-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 2-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 3-ANDs 2-AND into 3-NOR with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 2-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 3-NAND with Drive 2-OR into 4-NAND with Drive 2-OR into 4-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-ORs into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-OR 2-NAND into 2-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive Three 2-ORs into 3-NAND with Drive
STDH150
3-10
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name OA2222 OA2222D2 OA2222D4 OA31 OA31D2 OA31D4 OA311 OA311D2 OA3111 OA3111D2 OA32 OA32D2 OA321 OA321D2 OA322 OA322D2 OA33 OA33D2 SCG1 SCG1D2 SCG2 SCG2D2 SCG2D4 SCG3 SCG3D2 SCG3D4 SCG4 SCG4D2 Function Description Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive Four 2-ORs into 4-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 2-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 3-NAND with Drive 3-OR into 4-NAND with Drive 3-OR into 4-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 2-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-OR into 3-NAND with Drive 3-OR 2-ORs into 3-NAND with Drive 3-OR 2-ORs into 3-NAND Drive 3-ORs into 2-NAND with Drive 3-ORs into 2-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-NAND (2-AND into 2-NOR)s into 3-NAND with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-ANDs into 2-OR with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive 2-NANDs into 3-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive (two 2-ANDs into 2-NOR)s into 2-NAND with Drive
Samsung ASIC
3-11
STDH150
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name SCG4D4 SCG5 SCG5D2 SCG5D4 SCG6 SCG6D2 SCG6D4 SCG7 SCG7D2 SCG7D4 SCG8 SCG8D2 SCG9 SCG9D2 SCG9D4 SCG10 SCG10D2 SCG10D4 SCG11 SCG11D2 SCG12 SCG12D2 SCG12D4 SCG13 SCG13D2 SCG13D4 SCG14 SCG14D2 SCG14D4 SCG15 SCG15D2 SCG15D4 SCG16 SCG16D2 SCG16D4 SCG17 SCG17D2 SCG17D4 Function Description (two 2-ANDs into 2-NOR)s into 2-NAND with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive Three 2-ANDs into 3-OR with Drive 2-AND into 2-OR with Drive 2-AND into 2-OR with Drive 2-AND into 2-OR with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-NAND (2-AND into 2-NOR) into 2-NAND with Drive 2-AND into 3-OR with Drive 2-AND into 3-OR with Drive 2-OR into 2-AND with Drive 2-OR into 2-AND with Drive 2-OR into 2-AND with Drive 2-ORs into 2-AND with Drive 2-ORs into 2-AND with Drive 2-ORs into 2-AND with Drive 2-NORs into 3-NOR with Drive 2-NORs into 3-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NAND into 2-NOR with Drive 2-NOR into 2-NAND with Drive 2-NOR into 2-NAND with Drive 2-NOR into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 2-NAND with Drive 2-NAND into 3-NAND with Drive 2-NAND into 3-NAND with Drive 2-NAND into 3-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-OR with inverted input into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive 2-AND into 2-NOR into 2-NAND with Drive
STDH150
3-12
Samsung ASIC
LOGIC CELLS
Cell Names Function Descriptions (Continued)
Cell Name SCG18 SCG18D2 SCG18D4 SCG19 SCG19D2 SCG20 SCG20D2 SCG20D4 SCG21 SCG21D2 SCG22 SCG22D2 SCG22D4 DL1D2 DL2D2 DL5D2 DL10D2 IVD2 IVD3 IVD4 IVD6 IVD8 IVD16 IVD24 IVTD2 IVTD4 IVTD8 IVTD16 NID2 NID3 NID4 NID6 NID8 NID16 NID24 Function Description 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-NOR into 3-NAND with Drive 2-AND into 2-AND into 2-NOR with Drive 2-AND into 2-AND into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 2-NOR with Drive 2-NOR into 3-NOR with Drive 2-NOR into 3-NOR with Drive 2-NAND into 2-OR into 2-NAND with Drive 2-NAND into 2-OR into 2-NAND with Drive 2-NAND into 2-OR into 2-NAND with Drive Delay Cell with Drive Delay Cell with Drive Delay Cell with Drive 10ns Delay Cell with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverter with Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive Non-Inverting Buffer with Drive
Samsung ASIC
3-13
STDH150
LOGIC CELLS
Cell Names Function Descriptions (Continued)
NITD2 NITD4 NITD8 NITD16 Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive Non-Inverting Tri-State Buffer with Enable High, Drive
STDH150
3-14
Samsung ASIC
AD2/AD2D2/AD2D4/AD2D8
2-Input with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) AD2D2 AD2D4 AD2D8 1.67 Gate Count AD2D2 AD2D4 2.00 3.00 AD2D8 5.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.019 0.009*SL 0.018 0.007*SL 0.039 0.004*SL 0.044 0.004*SL 0.019 0.009*SL 0.018 0.007*SL 0.040 0.004*SL 0.047 0.004*SL
Parameter
Delay [ns]
Group3*
0.013 0.010*SL 0.013 0.007*SL 0.040 0.004*SL 0.045 0.004*SL 0.012 0.010*SL 0.013 0.007*SL 0.041 0.004*SL 0.049 0.004*SL
0.038 0.020 0.009*SL 0.032 0.017 0.007*SL 0.047 0.037 0.005*SL 0.050 0.041 0.005*SL 0.038 0.019 0.009*SL 0.032 0.017 0.007*SL 0.048 0.038 0.005*SL 0.054 0.045 0.005*SL *Group1 *Group2 *Group3
AD2D2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.020 0.005*SL 0.019 0.004*SL 0.045 0.002*SL 0.049 0.002*SL 0.027 0.004*SL 0.019 0.003*SL 0.046 0.002*SL 0.052 0.002*SL
Group3*
0.014 0.005*SL 0.015 0.004*SL 0.047 0.002*SL 0.053 0.002*SL 0.014 0.005*SL 0.014 0.004*SL 0.048 0.002*SL 0.056 0.002*SL
0.030 0.021 0.004*SL 0.026 0.019 0.003*SL 0.048 0.043 0.003*SL 0.052 0.046 0.003*SL 0.032 0.019 0.007*SL 0.027 0.021 0.003*SL 0.049 0.043 0.003*SL 0.055 0.049 0.003*SL *Group3 *Group1 *Group2
Samsung ASIC
3-15
STDH150
AD2/AD2D2/AD2D4/AD2D8
2-Input with 1X/2X/4X/8X Drive Switching Characteristics
AD2D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.028 0.002*SL 0.024 0.002*SL 0.056 0.001*SL 0.060 0.001*SL 0.033 0.002*SL 0.026 0.002*SL 0.056 0.001*SL 0.063 0.001*SL
Parameter
Delay [ns]
Group3*
0.020 0.002*SL 0.023 0.002*SL 0.062 0.001*SL 0.068 0.001*SL 0.020 0.002*SL 0.023 0.002*SL 0.063 0.001*SL 0.072 0.001*SL
0.031 0.025 0.003*SL 0.028 0.025 0.001*SL 0.058 0.054 0.002*SL 0.061 0.057 0.002*SL 0.035 0.028 0.003*SL 0.029 0.024 0.002*SL 0.058 0.054 0.002*SL 0.064 0.060 0.002*SL *Group1 *Group2 *Group3
AD2D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.027 0.001*SL 0.025 0.001*SL 0.055 0.001*SL 0.058 0.001*SL 0.030 0.001*SL 0.025 0.001*SL 0.055 0.001*SL 0.061 0.001*SL
Group3*
0.018 0.001*SL 0.023 0.001*SL 0.062 0.001*SL 0.068 0.000*SL 0.019 0.001*SL 0.024 0.001*SL 0.062 0.001*SL 0.071 0.000*SL
0.029 0.026 0.001*SL 0.026 0.024 0.001*SL 0.056 0.054 0.001*SL 0.058 0.057 0.001*SL 0.029 0.024 0.003*SL 0.026 0.023 0.001*SL 0.056 0.054 0.001*SL 0.061 0.060 0.001*SL *Group1 *Group2 *Group3
STDH150
3-16
Samsung ASIC
AD2B/AD2BD2/AD2BD4/AD2BD8
-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
AD2B Input Load (SL) AD2BD2 AD2BD4 AD2BD8 AD2B 2.33 Gate Count AD2BD2 AD2BD4 2.33 3.33 AD2BD8 5.67
Switching Characteristics
AD2B
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.019 0.009*SL 0.015 0.007*SL 0.073 0.004*SL 0.060 0.004*SL 0.016 0.010*SL 0.018 0.007*SL 0.041 0.004*SL 0.047 0.004*SL
Parameter
Delay [ns]
Group3*
0.012 0.010*SL 0.012 0.007*SL 0.074 0.004*SL 0.062 0.004*SL 0.013 0.010*SL 0.014 0.007*SL 0.042 0.004*SL 0.049 0.004*SL
0.038 0.020 0.009*SL 0.030 0.016 0.007*SL 0.081 0.071 0.005*SL 0.067 0.058 0.005*SL 0.037 0.020 0.008*SL 0.032 0.017 0.007*SL 0.049 0.039 0.005*SL 0.054 0.045 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-17
STDH150
AD2B/AD2BD2/AD2BD4/AD2BD8
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
AD2BD2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.021 0.005*SL 0.017 0.004*SL 0.079 0.002*SL 0.065 0.002*SL 0.022 0.005*SL 0.019 0.004*SL 0.046 0.002*SL 0.052 0.002*SL
Parameter
Delay [ns]
Group3*
0.013 0.005*SL 0.014 0.004*SL 0.082 0.002*SL 0.070 0.002*SL 0.014 0.005*SL 0.014 0.004*SL 0.049 0.002*SL 0.056 0.002*SL
0.030 0.021 0.005*SL 0.024 0.017 0.004*SL 0.082 0.076 0.003*SL 0.068 0.062 0.003*SL 0.031 0.021 0.005*SL 0.026 0.019 0.003*SL 0.049 0.044 0.003*SL 0.054 0.049 0.003*SL *Group1 *Group2 *Group3
AD2BD4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.028 0.002*SL 0.024 0.002*SL 0.090 0.001*SL 0.076 0.001*SL 0.032 0.002*SL 0.026 0.002*SL 0.057 0.001*SL 0.062 0.001*SL
Group3*
0.020 0.002*SL 0.022 0.002*SL 0.097 0.001*SL 0.085 0.001*SL 0.022 0.002*SL 0.023 0.002*SL 0.064 0.001*SL 0.071 0.001*SL
0.031 0.026 0.003*SL 0.027 0.023 0.002*SL 0.092 0.088 0.002*SL 0.077 0.073 0.002*SL 0.035 0.030 0.003*SL 0.028 0.023 0.003*SL 0.059 0.055 0.002*SL 0.063 0.059 0.002*SL *Group3 *Group1 *Group2
AD2BD8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.027 0.001*SL 0.023 0.001*SL 0.088 0.001*SL 0.077 0.001*SL 0.032 0.001*SL 0.025 0.001*SL 0.057 0.001*SL 0.061 0.001*SL
Group3*
0.020 0.001*SL 0.023 0.001*SL 0.096 0.001*SL 0.087 0.000*SL 0.023 0.001*SL 0.024 0.001*SL 0.064 0.001*SL 0.071 0.000*SL
0.029 0.027 0.001*SL 0.026 0.024 0.001*SL 0.089 0.087 0.001*SL 0.078 0.076 0.001*SL 0.033 0.030 0.001*SL 0.026 0.023 0.001*SL 0.057 0.055 0.001*SL 0.061 0.059 0.001*SL *Group3 *Group1 *Group2
STDH150
3-18
Samsung ASIC
AD3/AD3D2/AD3D4
3-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) AD3D2 AD3D4 2.00 Gate Count AD3D2 AD3D4 2.67 3.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.023 0.009*SL 0.018 0.007*SL 0.049 0.004*SL 0.052 0.004*SL 0.022 0.009*SL 0.021 0.007*SL 0.052 0.004*SL 0.057 0.004*SL 0.022 0.009*SL 0.024 0.007*SL 0.052 0.004*SL 0.060 0.004*SL
Parameter
Delay [ns]
Group3*
0.016 0.010*SL 0.014 0.007*SL 0.051 0.004*SL 0.055 0.004*SL 0.016 0.010*SL 0.015 0.007*SL 0.054 0.004*SL 0.059 0.004*SL 0.016 0.010*SL 0.017 0.007*SL 0.054 0.004*SL 0.063 0.004*SL
0.044 0.029 0.008*SL 0.032 0.018 0.007*SL 0.056 0.046 0.005*SL 0.059 0.049 0.005*SL 0.041 0.023 0.009*SL 0.034 0.019 0.007*SL 0.059 0.048 0.005*SL 0.063 0.053 0.005*SL 0.041 0.022 0.009*SL 0.037 0.022 0.007*SL 0.059 0.049 0.005*SL 0.066 0.055 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-19
STDH150
AD3/AD3D2/AD3D4
3-Input with 1X/2X/4X Drive Switching Characteristics
AD3D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.027 0.005*SL 0.022 0.004*SL 0.056 0.002*SL 0.058 0.002*SL 0.024 0.005*SL 0.025 0.003*SL 0.058 0.002*SL 0.062 0.002*SL 0.027 0.005*SL 0.026 0.003*SL 0.059 0.002*SL 0.066 0.002*SL
Parameter
Delay [ns]
Group3*
0.019 0.005*SL 0.021 0.004*SL 0.061 0.002*SL 0.064 0.002*SL 0.020 0.005*SL 0.019 0.004*SL 0.064 0.002*SL 0.069 0.002*SL 0.019 0.005*SL 0.022 0.004*SL 0.064 0.002*SL 0.073 0.002*SL
0.036 0.026 0.005*SL 0.029 0.021 0.004*SL 0.059 0.052 0.003*SL 0.060 0.054 0.003*SL 0.034 0.026 0.004*SL 0.030 0.021 0.004*SL 0.061 0.055 0.003*SL 0.065 0.058 0.003*SL 0.038 0.030 0.004*SL 0.032 0.023 0.004*SL 0.061 0.055 0.003*SL 0.068 0.061 0.003*SL *Group3 *Group1 *Group2
AD3D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.036 0.002*SL 0.031 0.002*SL 0.069 0.001*SL 0.071 0.001*SL 0.036 0.002*SL 0.031 0.002*SL 0.073 0.001*SL 0.075 0.001*SL 0.037 0.002*SL 0.032 0.002*SL 0.073 0.001*SL 0.078 0.001*SL
Group3*
0.029 0.002*SL 0.029 0.002*SL 0.081 0.001*SL 0.083 0.001*SL 0.029 0.002*SL 0.030 0.002*SL 0.084 0.001*SL 0.087 0.001*SL 0.030 0.002*SL 0.032 0.002*SL 0.084 0.001*SL 0.091 0.001*SL
0.039 0.034 0.003*SL 0.033 0.028 0.002*SL 0.071 0.067 0.002*SL 0.072 0.068 0.002*SL 0.038 0.030 0.004*SL 0.034 0.029 0.002*SL 0.074 0.070 0.002*SL 0.076 0.072 0.002*SL 0.039 0.033 0.003*SL 0.035 0.030 0.002*SL 0.074 0.070 0.002*SL 0.079 0.075 0.002*SL *Group3 *Group1 *Group2
STDH150
3-20
Samsung ASIC
AD4/AD4D2/AD4D4
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
2.33 Input Load (SL) AD4D2 Gate Count AD4D2 2.67 AD4D4 AD4D4 3.67
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.026 0.009*SL 0.024 0.007*SL 0.055 0.005*SL 0.062 0.004*SL 0.026 0.009*SL 0.024 0.007*SL 0.060 0.005*SL 0.067 0.004*SL 0.027 0.009*SL 0.027 0.007*SL 0.062 0.005*SL 0.072 0.004*SL 0.025 0.009*SL 0.029 0.007*SL 0.063 0.005*SL 0.076 0.004*SL
Parameter
Delay [ns]
Group3*
0.019 0.010*SL 0.017 0.007*SL 0.058 0.004*SL 0.066 0.004*SL 0.021 0.010*SL 0.020 0.007*SL 0.063 0.004*SL 0.072 0.004*SL 0.020 0.010*SL 0.022 0.007*SL 0.066 0.004*SL 0.077 0.004*SL 0.020 0.010*SL 0.022 0.007*SL 0.067 0.004*SL 0.082 0.004*SL
0.046 0.028 0.009*SL 0.036 0.020 0.008*SL 0.062 0.050 0.006*SL 0.068 0.058 0.005*SL 0.045 0.027 0.009*SL 0.038 0.025 0.007*SL 0.066 0.055 0.006*SL 0.073 0.062 0.005*SL 0.045 0.026 0.010*SL 0.040 0.025 0.008*SL 0.068 0.057 0.006*SL 0.078 0.067 0.006*SL 0.043 0.024 0.010*SL 0.040 0.025 0.008*SL 0.070 0.059 0.006*SL 0.082 0.071 0.006*SL *Group1 *Group2 *Group3
Samsung ASIC
3-21
STDH150
AD4/AD4D2/AD4D4
4-Input with 1X/2X/4X Drive Switching Characteristics
AD4D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.031 0.005*SL 0.027 0.004*SL 0.062 0.002*SL 0.069 0.002*SL 0.029 0.005*SL 0.029 0.004*SL 0.067 0.002*SL 0.075 0.002*SL 0.032 0.005*SL 0.031 0.003*SL 0.069 0.002*SL 0.079 0.002*SL 0.033 0.005*SL 0.034 0.003*SL 0.070 0.002*SL 0.083 0.002*SL
Parameter
Delay [ns]
Group3*
0.025 0.005*SL 0.026 0.004*SL 0.070 0.002*SL 0.078 0.002*SL 0.025 0.005*SL 0.026 0.004*SL 0.075 0.002*SL 0.084 0.002*SL 0.025 0.005*SL 0.029 0.004*SL 0.078 0.002*SL 0.090 0.002*SL 0.025 0.005*SL 0.029 0.004*SL 0.079 0.002*SL 0.094 0.002*SL
0.038 0.027 0.006*SL 0.033 0.025 0.004*SL 0.064 0.057 0.004*SL 0.071 0.064 0.003*SL 0.039 0.029 0.005*SL 0.035 0.027 0.004*SL 0.070 0.063 0.004*SL 0.077 0.070 0.004*SL 0.039 0.028 0.006*SL 0.036 0.026 0.005*SL 0.072 0.065 0.004*SL 0.082 0.074 0.004*SL 0.040 0.028 0.006*SL 0.038 0.029 0.005*SL 0.073 0.066 0.004*SL 0.085 0.078 0.004*SL *Group1 *Group2 *Group3
AD4D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.041 0.002*SL 0.039 0.002*SL 0.080 0.001*SL 0.086 0.001*SL 0.043 0.002*SL 0.041 0.002*SL 0.085 0.001*SL 0.092 0.001*SL 0.043 0.002*SL 0.042 0.002*SL 0.088 0.001*SL 0.097 0.001*SL 0.042 0.002*SL 0.044 0.002*SL 0.089 0.001*SL 0.101 0.001*SL
Group3*
0.039 0.002*SL 0.038 0.002*SL 0.094 0.001*SL 0.103 0.001*SL 0.039 0.002*SL 0.041 0.002*SL 0.100 0.001*SL 0.109 0.001*SL 0.038 0.002*SL 0.043 0.002*SL 0.103 0.001*SL 0.114 0.001*SL 0.038 0.002*SL 0.043 0.002*SL 0.104 0.001*SL 0.119 0.001*SL
0.045 0.040 0.003*SL 0.041 0.036 0.003*SL 0.081 0.077 0.002*SL 0.088 0.083 0.002*SL 0.045 0.039 0.003*SL 0.045 0.041 0.002*SL 0.086 0.082 0.002*SL 0.093 0.089 0.002*SL 0.047 0.042 0.003*SL 0.045 0.042 0.002*SL 0.089 0.085 0.002*SL 0.098 0.093 0.002*SL 0.047 0.042 0.002*SL 0.046 0.042 0.002*SL 0.090 0.086 0.002*SL 0.102 0.097 0.002*SL *Group1 *Group2 *Group3
STDH150
3-22
Samsung ASIC
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4XDrive Logic Symbol
Truth Table
Cell Data
3.33 Input Load (SL) AD5D2 Gate Count AD5D2 3.67 AD5D4 AD5D4 5.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.030 0.019*SL 0.021 0.007*SL 0.054 0.009*SL 0.055 0.004*SL 0.030 0.019*SL 0.023 0.007*SL 0.057 0.009*SL 0.059 0.004*SL 0.031 0.019*SL 0.025 0.006*SL 0.057 0.009*SL 0.063 0.004*SL 0.029 0.019*SL 0.020 0.007*SL 0.051 0.009*SL 0.047 0.004*SL 0.027 0.020*SL 0.023 0.007*SL 0.053 0.009*SL 0.050 0.004*SL
Parameter
Delay [ns]
Group3*
0.027 0.020*SL 0.015 0.007*SL 0.054 0.009*SL 0.057 0.004*SL 0.027 0.020*SL 0.017 0.007*SL 0.057 0.009*SL 0.062 0.004*SL 0.027 0.020*SL 0.017 0.007*SL 0.058 0.009*SL 0.066 0.004*SL 0.026 0.020*SL 0.018 0.007*SL 0.052 0.009*SL 0.048 0.004*SL 0.026 0.020*SL 0.017 0.007*SL 0.053 0.009*SL 0.052 0.004*SL
0.072 0.036 0.018*SL 0.033 0.020 0.007*SL 0.070 0.052 0.009*SL 0.060 0.051 0.005*SL 0.071 0.034 0.018*SL 0.035 0.022 0.007*SL 0.073 0.055 0.009*SL 0.064 0.054 0.005*SL 0.071 0.034 0.019*SL 0.035 0.020 0.008*SL 0.074 0.055 0.009*SL 0.068 0.058 0.005*SL 0.069 0.031 0.019*SL 0.034 0.022 0.006*SL 0.068 0.050 0.009*SL 0.053 0.045 0.004*SL 0.067 0.029 0.019*SL 0.037 0.024 0.006*SL 0.069 0.051 0.009*SL 0.057 0.048 0.004*SL *Group3 *Group1 *Group2
Samsung ASIC
3-23
STDH150
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.037 0.010*SL 0.024 0.003*SL 0.063 0.004*SL 0.060 0.002*SL 0.037 0.009*SL 0.026 0.003*SL 0.066 0.004*SL 0.064 0.002*SL 0.037 0.009*SL 0.027 0.003*SL 0.066 0.004*SL 0.067 0.002*SL 0.032 0.010*SL 0.024 0.003*SL 0.061 0.004*SL 0.055 0.002*SL 0.032 0.010*SL 0.026 0.003*SL 0.062 0.004*SL 0.058 0.002*SL
Group3*
0.029 0.010*SL 0.022 0.003*SL 0.065 0.004*SL 0.066 0.002*SL 0.029 0.010*SL 0.022 0.003*SL 0.067 0.004*SL 0.070 0.002*SL 0.029 0.010*SL 0.022 0.003*SL 0.068 0.004*SL 0.074 0.002*SL 0.028 0.010*SL 0.021 0.003*SL 0.063 0.004*SL 0.059 0.002*SL 0.028 0.010*SL 0.021 0.003*SL 0.064 0.004*SL 0.062 0.002*SL
0.057 0.039 0.009*SL 0.030 0.024 0.003*SL 0.070 0.060 0.005*SL 0.062 0.056 0.003*SL 0.057 0.039 0.009*SL 0.031 0.022 0.004*SL 0.073 0.063 0.005*SL 0.066 0.060 0.003*SL 0.057 0.039 0.009*SL 0.033 0.025 0.004*SL 0.073 0.063 0.005*SL 0.069 0.063 0.003*SL 0.052 0.034 0.009*SL 0.031 0.025 0.003*SL 0.069 0.059 0.005*SL 0.058 0.053 0.003*SL 0.051 0.032 0.010*SL 0.031 0.024 0.004*SL 0.070 0.060 0.005*SL 0.061 0.056 0.003*SL *Group1 *Group2 *Group3
STDH150
3-24
Samsung ASIC
AD5/AD5D2/AD5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
AD5D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.025 0.002*SL 0.021 0.002*SL 0.116 0.001*SL 0.098 0.001*SL 0.026 0.002*SL 0.022 0.002*SL 0.119 0.001*SL 0.101 0.001*SL 0.026 0.002*SL 0.023 0.002*SL 0.119 0.001*SL 0.104 0.001*SL 0.026 0.002*SL 0.021 0.002*SL 0.112 0.001*SL 0.092 0.001*SL 0.026 0.002*SL 0.021 0.002*SL 0.113 0.001*SL 0.094 0.001*SL
Parameter
Delay [ns]
Group3*
0.016 0.002*SL 0.020 0.002*SL 0.120 0.001*SL 0.106 0.001*SL 0.016 0.002*SL 0.020 0.002*SL 0.124 0.001*SL 0.108 0.001*SL 0.016 0.002*SL 0.020 0.002*SL 0.124 0.001*SL 0.111 0.001*SL 0.015 0.002*SL 0.020 0.002*SL 0.116 0.001*SL 0.099 0.001*SL 0.017 0.002*SL 0.020 0.002*SL 0.117 0.001*SL 0.101 0.001*SL
0.029 0.024 0.003*SL 0.024 0.020 0.002*SL 0.117 0.114 0.002*SL 0.099 0.096 0.002*SL 0.029 0.024 0.003*SL 0.025 0.021 0.002*SL 0.120 0.117 0.002*SL 0.102 0.098 0.002*SL 0.029 0.024 0.003*SL 0.026 0.021 0.002*SL 0.121 0.117 0.002*SL 0.105 0.101 0.002*SL 0.030 0.025 0.003*SL 0.024 0.021 0.002*SL 0.113 0.109 0.002*SL 0.093 0.089 0.002*SL 0.029 0.024 0.003*SL 0.025 0.022 0.002*SL 0.114 0.111 0.002*SL 0.095 0.092 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-25
STDH150
ND2/ND2D2/ND2D4/ND2D8
2-Input NAND with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) ND2D2 ND2D4 ND2D8 1.00 Gate Count ND2D2 ND2D4 2.00 3.67 ND2D8 5.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.032 0.010*SL 0.029 0.008*SL 0.027 0.005*SL 0.022 0.005*SL 0.033 0.010*SL 0.023 0.009*SL 0.029 0.005*SL 0.023 0.005*SL
Parameter
Delay [ns]
Group3*
0.020 0.010*SL 0.019 0.009*SL 0.026 0.005*SL 0.023 0.004*SL 0.023 0.010*SL 0.018 0.009*SL 0.029 0.005*SL 0.024 0.004*SL
0.052 0.034 0.009*SL 0.047 0.032 0.007*SL 0.033 0.022 0.006*SL 0.029 0.017 0.006*SL 0.054 0.037 0.009*SL 0.042 0.027 0.008*SL 0.037 0.026 0.005*SL 0.030 0.019 0.006*SL *Group3 *Group1 *Group2
ND2D2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.034 0.005*SL 0.033 0.004*SL 0.025 0.002*SL 0.021 0.002*SL 0.036 0.005*SL 0.027 0.004*SL 0.028 0.002*SL 0.022 0.002*SL
Group3*
0.021 0.005*SL 0.020 0.004*SL 0.027 0.002*SL 0.024 0.002*SL 0.025 0.005*SL 0.019 0.004*SL 0.029 0.002*SL 0.025 0.002*SL
0.044 0.035 0.004*SL 0.041 0.032 0.004*SL 0.028 0.021 0.003*SL 0.023 0.017 0.003*SL 0.047 0.038 0.004*SL 0.035 0.027 0.004*SL 0.031 0.025 0.003*SL 0.025 0.018 0.003*SL *Group1 *Group2 *Group3
STDH150
3-26
Samsung ASIC
ND2/ND2D2/ND2D4/ND2D8
2-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
ND2D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.034 0.002*SL 0.032 0.002*SL 0.023 0.001*SL 0.019 0.001*SL 0.037 0.002*SL 0.026 0.002*SL 0.027 0.001*SL 0.020 0.001*SL
Group3*
0.020 0.003*SL 0.020 0.002*SL 0.027 0.001*SL 0.023 0.001*SL 0.024 0.003*SL 0.019 0.002*SL 0.029 0.001*SL 0.025 0.001*SL
0.039 0.035 0.002*SL 0.036 0.031 0.002*SL 0.024 0.021 0.002*SL 0.020 0.016 0.002*SL 0.042 0.038 0.002*SL 0.031 0.026 0.002*SL 0.028 0.025 0.002*SL 0.022 0.018 0.002*SL *Group1 *Group2 *Group3
ND2D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.024 0.001*SL 0.023 0.001*SL 0.080 0.001*SL 0.077 0.001*SL 0.024 0.001*SL 0.022 0.001*SL 0.083 0.001*SL 0.078 0.001*SL
Group3*
0.017 0.001*SL 0.020 0.001*SL 0.085 0.001*SL 0.086 0.000*SL 0.017 0.001*SL 0.020 0.001*SL 0.088 0.001*SL 0.086 0.000*SL
0.026 0.023 0.001*SL 0.024 0.022 0.001*SL 0.080 0.079 0.001*SL 0.078 0.076 0.001*SL 0.026 0.023 0.001*SL 0.024 0.022 0.001*SL 0.084 0.082 0.001*SL 0.078 0.076 0.001*SL *Group1 *Group2 *Group3
Samsung ASIC
3-27
STDH150
ND2B/ND2BD2/ND2BD4/ND2BD8
2-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
ND2B Input Load (SL) ND2BD2 ND2BD4 ND2BD8 ND2B 1.67 Gate Count ND2BD2 ND2BD4 ND2BD8 2.67 4.00 5.67
Switching Characteristics
ND2B
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.022 0.010*SL 0.022 0.009*SL 0.046 0.004*SL 0.044 0.005*SL 0.034 0.010*SL 0.026 0.009*SL 0.030 0.004*SL 0.024 0.005*SL
Group3*
0.017 0.010*SL 0.017 0.009*SL 0.046 0.004*SL 0.044 0.004*SL 0.025 0.010*SL 0.019 0.009*SL 0.029 0.004*SL 0.026 0.004*SL
0.044 0.026 0.009*SL 0.039 0.022 0.009*SL 0.054 0.044 0.005*SL 0.052 0.042 0.005*SL 0.055 0.038 0.008*SL 0.044 0.027 0.008*SL 0.037 0.026 0.005*SL 0.031 0.020 0.006*SL *Group3 *Group1 *Group2
STDH150
3-28
Samsung ASIC
ND2B/ND2BD2/ND2BD4/ND2BD8
2-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND2BD2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.034 0.005*SL 0.023 0.004*SL 0.050 0.002*SL 0.048 0.002*SL 0.037 0.005*SL 0.028 0.004*SL 0.028 0.002*SL 0.022 0.002*SL
Group3*
0.017 0.005*SL 0.018 0.005*SL 0.050 0.002*SL 0.049 0.002*SL 0.025 0.005*SL 0.021 0.004*SL 0.029 0.002*SL 0.026 0.002*SL
0.037 0.022 0.008*SL 0.032 0.024 0.004*SL 0.053 0.048 0.003*SL 0.052 0.046 0.003*SL 0.047 0.039 0.004*SL 0.036 0.027 0.005*SL 0.031 0.025 0.003*SL 0.025 0.019 0.003*SL *Group1 *Group2 *Group3
ND2BD4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.038 0.002*SL 0.029 0.002*SL 0.059 0.001*SL 0.061 0.001*SL 0.038 0.002*SL 0.028 0.002*SL 0.026 0.001*SL 0.021 0.001*SL
Group3*
0.021 0.003*SL 0.027 0.002*SL 0.063 0.001*SL 0.067 0.001*SL 0.025 0.003*SL 0.024 0.002*SL 0.029 0.001*SL 0.027 0.001*SL
0.041 0.035 0.003*SL 0.033 0.030 0.002*SL 0.061 0.058 0.001*SL 0.063 0.060 0.002*SL 0.043 0.039 0.002*SL 0.032 0.028 0.002*SL 0.028 0.024 0.002*SL 0.022 0.019 0.002*SL *Group1 *Group2 *Group3
ND2BD8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.024 0.001*SL 0.023 0.001*SL 0.099 0.001*SL 0.098 0.001*SL 0.024 0.001*SL 0.023 0.001*SL 0.083 0.001*SL 0.078 0.001*SL
Group3*
0.016 0.001*SL 0.020 0.001*SL 0.104 0.001*SL 0.107 0.000*SL 0.016 0.001*SL 0.020 0.001*SL 0.088 0.001*SL 0.087 0.000*SL
0.026 0.023 0.001*SL 0.024 0.022 0.001*SL 0.099 0.098 0.001*SL 0.099 0.097 0.001*SL 0.026 0.023 0.001*SL 0.024 0.022 0.001*SL 0.084 0.082 0.001*SL 0.079 0.077 0.001*SL *Group1 *Group2 *Group3
Samsung ASIC
3-29
STDH150
ND3/ND3D2/ND3D4/ND3D8
3-Input NAND with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) 1.67 ND3D2 ND3D2 3.00 Gate Count ND3D4 ND3D4 3.67 ND3D8 ND3D8 5.67
STDH150
3-30
Samsung ASIC
ND3/ND3D2/ND3D4/ND3D8
3-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.035 0.015*SL 0.036 0.012*SL 0.032 0.007*SL 0.025 0.006*SL 0.041 0.015*SL 0.032 0.012*SL 0.036 0.007*SL 0.028 0.006*SL 0.047 0.015*SL 0.030 0.013*SL 0.039 0.007*SL 0.028 0.006*SL
Parameter
Delay [ns]
Group3*
0.025 0.015*SL 0.026 0.013*SL 0.032 0.007*SL 0.025 0.006*SL 0.031 0.015*SL 0.024 0.013*SL 0.036 0.007*SL 0.029 0.006*SL 0.037 0.016*SL 0.024 0.013*SL 0.039 0.007*SL 0.029 0.006*SL
0.068 0.042 0.013*SL 0.063 0.042 0.011*SL 0.045 0.031 0.007*SL 0.037 0.022 0.007*SL 0.073 0.045 0.014*SL 0.058 0.035 0.011*SL 0.049 0.035 0.007*SL 0.040 0.026 0.007*SL 0.079 0.053 0.013*SL 0.056 0.031 0.012*SL 0.052 0.039 0.007*SL 0.040 0.027 0.007*SL *Group3 *Group1 *Group2
ND3D2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.037 0.007*SL 0.035 0.006*SL 0.031 0.003*SL 0.023 0.003*SL 0.040 0.007*SL 0.031 0.006*SL 0.035 0.003*SL 0.026 0.003*SL 0.046 0.007*SL 0.027 0.006*SL 0.038 0.003*SL 0.026 0.003*SL
Group3*
0.023 0.008*SL 0.024 0.006*SL 0.030 0.003*SL 0.024 0.003*SL 0.029 0.008*SL 0.023 0.006*SL 0.034 0.003*SL 0.027 0.003*SL 0.034 0.008*SL 0.022 0.006*SL 0.038 0.003*SL 0.027 0.003*SL
0.052 0.038 0.007*SL 0.048 0.037 0.005*SL 0.036 0.027 0.004*SL 0.027 0.019 0.004*SL 0.056 0.043 0.006*SL 0.044 0.032 0.006*SL 0.040 0.033 0.004*SL 0.031 0.023 0.004*SL 0.060 0.045 0.007*SL 0.040 0.028 0.006*SL 0.044 0.036 0.004*SL 0.032 0.024 0.004*SL *Group1 *Group2 *Group3
Samsung ASIC
3-31
STDH150
ND3/ND3D2/ND3D4/ND3D8
3-Input NAND with 1X/2X/4X/8X Drive Switching Characteristics
ND3D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.024 0.002*SL 0.024 0.002*SL 0.086 0.001*SL 0.080 0.001*SL 0.024 0.002*SL 0.022 0.002*SL 0.091 0.001*SL 0.083 0.001*SL 0.025 0.002*SL 0.023 0.002*SL 0.096 0.001*SL 0.084 0.001*SL
Parameter
Delay [ns]
Group3*
0.016 0.002*SL 0.021 0.002*SL 0.091 0.001*SL 0.088 0.001*SL 0.014 0.002*SL 0.020 0.002*SL 0.095 0.001*SL 0.091 0.001*SL 0.016 0.002*SL 0.021 0.002*SL 0.100 0.001*SL 0.092 0.001*SL
0.028 0.023 0.003*SL 0.027 0.022 0.002*SL 0.088 0.084 0.002*SL 0.081 0.078 0.002*SL 0.028 0.024 0.002*SL 0.026 0.022 0.002*SL 0.093 0.089 0.002*SL 0.084 0.081 0.002*SL 0.029 0.024 0.003*SL 0.026 0.021 0.002*SL 0.097 0.094 0.002*SL 0.085 0.081 0.002*SL *Group3 *Group1 *Group2
ND3D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.026 0.001*SL 0.024 0.001*SL 0.095 0.001*SL 0.088 0.001*SL 0.026 0.001*SL 0.024 0.001*SL 0.100 0.001*SL 0.091 0.001*SL 0.027 0.001*SL 0.024 0.001*SL 0.104 0.001*SL 0.091 0.001*SL
Group3*
0.017 0.001*SL 0.021 0.001*SL 0.100 0.001*SL 0.097 0.000*SL 0.017 0.001*SL 0.021 0.001*SL 0.105 0.001*SL 0.100 0.000*SL 0.017 0.001*SL 0.021 0.001*SL 0.110 0.001*SL 0.100 0.000*SL
0.028 0.025 0.001*SL 0.025 0.022 0.001*SL 0.095 0.093 0.001*SL 0.088 0.086 0.001*SL 0.027 0.023 0.002*SL 0.025 0.022 0.001*SL 0.100 0.099 0.001*SL 0.091 0.089 0.001*SL 0.029 0.026 0.001*SL 0.025 0.022 0.001*SL 0.105 0.103 0.001*SL 0.092 0.090 0.001*SL *Group1 *Group2 *Group3
STDH150
3-32
Samsung ASIC
ND3B/ND3BD2/ND3BD4/ND3BD8
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Other Stares
Cell Data
Input Load (SL) ND3B ND3B 2.00 ND3BD2 ND3BD2 3.33 Gate Count ND3BD4 ND3BD4 4.33 ND3BD8 ND3BD8 6.33
Samsung ASIC
3-33
STDH150
ND3B/ND3BD2/ND3BD4/ND3BD8
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND3B
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay [ns] Delay Equations [ns] Group1* Group2*
0.028 0.015*SL 0.027 0.013*SL 0.048 0.007*SL 0.046 0.006*SL 0.041 0.015*SL 0.033 0.012*SL 0.036 0.007*SL 0.029 0.006*SL 0.047 0.015*SL 0.030 0.013*SL 0.039 0.007*SL 0.029 0.006*SL
Parameter
Group3*
0.025 0.015*SL 0.025 0.013*SL 0.048 0.007*SL 0.046 0.006*SL 0.031 0.015*SL 0.026 0.013*SL 0.035 0.007*SL 0.030 0.006*SL 0.037 0.015*SL 0.025 0.013*SL 0.039 0.007*SL 0.030 0.006*SL
0.059 0.029 0.015*SL 0.055 0.031 0.012*SL 0.061 0.047 0.007*SL 0.058 0.044 0.007*SL 0.072 0.045 0.014*SL 0.059 0.036 0.012*SL 0.049 0.035 0.007*SL 0.040 0.026 0.007*SL 0.079 0.053 0.013*SL 0.057 0.034 0.012*SL 0.052 0.039 0.007*SL 0.041 0.027 0.007*SL *Group3 *Group1 *Group2
ND3BD2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.030 0.008*SL 0.029 0.006*SL 0.053 0.003*SL 0.049 0.003*SL 0.041 0.007*SL 0.032 0.006*SL 0.035 0.003*SL 0.027 0.003*SL 0.049 0.007*SL 0.031 0.006*SL 0.039 0.003*SL 0.028 0.003*SL
Group3*
0.024 0.008*SL 0.024 0.006*SL 0.053 0.003*SL 0.050 0.003*SL 0.031 0.008*SL 0.027 0.006*SL 0.035 0.003*SL 0.030 0.003*SL 0.037 0.008*SL 0.024 0.006*SL 0.039 0.003*SL 0.030 0.003*SL
0.052 0.044 0.004*SL 0.043 0.032 0.006*SL 0.059 0.052 0.004*SL 0.055 0.048 0.003*SL 0.058 0.045 0.006*SL 0.047 0.037 0.005*SL 0.041 0.034 0.004*SL 0.032 0.024 0.004*SL 0.064 0.050 0.007*SL 0.043 0.029 0.007*SL 0.045 0.038 0.004*SL 0.034 0.026 0.004*SL *Group1 *Group2 *Group3
STDH150
3-34
Samsung ASIC
ND3B/ND3BD2/ND3BD4/ND3BD8
3-Input NAND with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
ND3BD4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.025 0.002*SL 0.023 0.002*SL 0.102 0.001*SL 0.101 0.001*SL 0.023 0.002*SL 0.023 0.002*SL 0.091 0.001*SL 0.083 0.001*SL 0.026 0.002*SL 0.024 0.002*SL 0.095 0.001*SL 0.084 0.001*SL
Parameter
Delay [ns]
Group3*
0.017 0.002*SL 0.020 0.002*SL 0.106 0.001*SL 0.109 0.001*SL 0.014 0.002*SL 0.021 0.002*SL 0.095 0.001*SL 0.091 0.001*SL 0.015 0.002*SL 0.021 0.002*SL 0.099 0.001*SL 0.091 0.001*SL
0.028 0.023 0.003*SL 0.026 0.023 0.002*SL 0.103 0.100 0.002*SL 0.102 0.098 0.002*SL 0.027 0.023 0.002*SL 0.026 0.022 0.002*SL 0.092 0.089 0.002*SL 0.084 0.081 0.002*SL 0.030 0.025 0.002*SL 0.027 0.022 0.002*SL 0.096 0.093 0.002*SL 0.085 0.081 0.002*SL *Group3 *Group1 *Group2
ND3BD8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.025 0.001*SL 0.024 0.001*SL 0.112 0.001*SL 0.109 0.001*SL 0.026 0.001*SL 0.023 0.001*SL 0.100 0.001*SL 0.092 0.001*SL 0.027 0.001*SL 0.024 0.001*SL 0.105 0.001*SL 0.092 0.001*SL
Group3*
0.017 0.001*SL 0.021 0.001*SL 0.117 0.001*SL 0.118 0.000*SL 0.017 0.001*SL 0.021 0.001*SL 0.105 0.001*SL 0.100 0.000*SL 0.017 0.001*SL 0.021 0.001*SL 0.110 0.001*SL 0.101 0.000*SL
0.026 0.023 0.002*SL 0.026 0.023 0.001*SL 0.112 0.110 0.001*SL 0.110 0.108 0.001*SL 0.027 0.023 0.002*SL 0.025 0.022 0.001*SL 0.101 0.099 0.001*SL 0.092 0.090 0.001*SL 0.029 0.026 0.001*SL 0.025 0.022 0.001*SL 0.105 0.103 0.001*SL 0.093 0.091 0.001*SL *Group1 *Group2 *Group3
Samsung ASIC
3-35
STDH150
ND4/ND4D2/ND4D4
4-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
2.00 Input Load (SL) ND4D2 Gate Count ND4D2 3.67 ND4D4 ND4D4 4.00
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.038 0.020*SL 0.041 0.016*SL 0.036 0.009*SL 0.026 0.008*SL 0.046 0.020*SL 0.038 0.016*SL 0.041 0.009*SL 0.032 0.008*SL 0.053 0.020*SL 0.037 0.016*SL 0.046 0.009*SL 0.034 0.008*SL 0.060 0.020*SL 0.035 0.017*SL 0.050 0.009*SL 0.035 0.008*SL
Group3*
0.032 0.020*SL 0.032 0.017*SL 0.036 0.009*SL 0.026 0.008*SL 0.039 0.020*SL 0.032 0.017*SL 0.041 0.009*SL 0.032 0.008*SL 0.047 0.020*SL 0.032 0.017*SL 0.046 0.009*SL 0.034 0.008*SL 0.055 0.020*SL 0.032 0.017*SL 0.050 0.009*SL 0.035 0.008*SL
0.082 0.047 0.018*SL 0.076 0.046 0.015*SL 0.054 0.036 0.009*SL 0.042 0.025 0.008*SL 0.088 0.051 0.019*SL 0.074 0.044 0.015*SL 0.059 0.041 0.009*SL 0.047 0.030 0.009*SL 0.095 0.058 0.019*SL 0.071 0.039 0.016*SL 0.063 0.045 0.009*SL 0.049 0.032 0.009*SL 0.103 0.066 0.019*SL 0.069 0.037 0.016*SL 0.067 0.049 0.009*SL 0.050 0.034 0.008*SL *Group1 *Group2 *Group3
STDH150
3-36
Samsung ASIC
ND4/ND4D2/ND4D4
4-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND4D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.042 0.010*SL 0.043 0.008*SL 0.036 0.004*SL 0.026 0.004*SL 0.048 0.010*SL 0.038 0.008*SL 0.041 0.004*SL 0.030 0.004*SL 0.056 0.010*SL 0.036 0.008*SL 0.046 0.004*SL 0.035 0.004*SL 0.064 0.010*SL 0.033 0.008*SL 0.050 0.004*SL 0.035 0.004*SL
Group3*
0.030 0.010*SL 0.033 0.008*SL 0.036 0.004*SL 0.026 0.004*SL 0.038 0.010*SL 0.031 0.008*SL 0.041 0.004*SL 0.031 0.004*SL 0.049 0.010*SL 0.031 0.008*SL 0.047 0.004*SL 0.035 0.004*SL 0.056 0.010*SL 0.031 0.008*SL 0.051 0.004*SL 0.036 0.004*SL
0.064 0.047 0.009*SL 0.061 0.048 0.007*SL 0.044 0.035 0.005*SL 0.033 0.023 0.005*SL 0.071 0.054 0.008*SL 0.056 0.042 0.007*SL 0.049 0.041 0.004*SL 0.037 0.028 0.005*SL 0.077 0.059 0.009*SL 0.054 0.039 0.007*SL 0.055 0.046 0.005*SL 0.042 0.033 0.004*SL 0.084 0.065 0.010*SL 0.052 0.037 0.007*SL 0.059 0.049 0.005*SL 0.043 0.035 0.004*SL *Group1 *Group2 *Group3
ND4D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.026 0.002*SL 0.023 0.002*SL 0.096 0.001*SL 0.087 0.001*SL 0.025 0.002*SL 0.025 0.002*SL 0.103 0.001*SL 0.092 0.001*SL 0.026 0.002*SL 0.025 0.002*SL 0.109 0.001*SL 0.095 0.001*SL 0.025 0.002*SL 0.025 0.002*SL 0.114 0.001*SL 0.096 0.001*SL
Group3*
0.016 0.002*SL 0.021 0.002*SL 0.101 0.001*SL 0.096 0.001*SL 0.016 0.002*SL 0.021 0.002*SL 0.108 0.001*SL 0.101 0.001*SL 0.017 0.002*SL 0.021 0.002*SL 0.113 0.001*SL 0.103 0.001*SL 0.016 0.002*SL 0.021 0.002*SL 0.119 0.001*SL 0.104 0.001*SL
0.030 0.025 0.003*SL 0.027 0.024 0.002*SL 0.097 0.094 0.002*SL 0.088 0.085 0.002*SL 0.029 0.025 0.002*SL 0.028 0.023 0.002*SL 0.104 0.101 0.002*SL 0.093 0.090 0.002*SL 0.030 0.024 0.003*SL 0.028 0.023 0.002*SL 0.110 0.107 0.002*SL 0.096 0.092 0.002*SL 0.030 0.026 0.002*SL 0.028 0.023 0.002*SL 0.115 0.112 0.002*SL 0.097 0.094 0.002*SL *Group3 *Group1 *Group2
Samsung ASIC
3-37
STDH150
ND5/ND5D2/ND5D4
5-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
4.00 Input Load (SL) ND5D2 Gate Count ND5D2 4.33 ND5D4 ND5D4 5.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.017 0.009*SL 0.025 0.007*SL 0.074 0.004*SL 0.079 0.004*SL 0.015 0.010*SL 0.022 0.007*SL 0.079 0.004*SL 0.082 0.004*SL 0.017 0.009*SL 0.023 0.007*SL 0.083 0.004*SL 0.083 0.004*SL 0.015 0.010*SL 0.022 0.007*SL 0.066 0.004*SL 0.078 0.004*SL 0.017 0.010*SL 0.024 0.007*SL 0.068 0.004*SL 0.079 0.004*SL
Group3*
0.010 0.010*SL 0.018 0.007*SL 0.074 0.004*SL 0.083 0.004*SL 0.012 0.010*SL 0.019 0.007*SL 0.079 0.004*SL 0.086 0.004*SL 0.011 0.010*SL 0.019 0.007*SL 0.083 0.004*SL 0.087 0.004*SL 0.012 0.010*SL 0.019 0.007*SL 0.066 0.004*SL 0.082 0.004*SL 0.014 0.010*SL 0.018 0.007*SL 0.069 0.004*SL 0.084 0.004*SL
0.036 0.018 0.009*SL 0.036 0.020 0.008*SL 0.082 0.073 0.005*SL 0.085 0.075 0.005*SL 0.036 0.018 0.009*SL 0.036 0.021 0.007*SL 0.087 0.077 0.005*SL 0.088 0.077 0.005*SL 0.037 0.019 0.009*SL 0.036 0.021 0.008*SL 0.091 0.081 0.005*SL 0.088 0.078 0.005*SL 0.037 0.020 0.008*SL 0.035 0.020 0.008*SL 0.073 0.064 0.005*SL 0.084 0.074 0.005*SL 0.041 0.027 0.007*SL 0.035 0.019 0.008*SL 0.076 0.066 0.005*SL 0.085 0.075 0.005*SL *Group1 *Group2 *Group3
STDH150
3-38
Samsung ASIC
ND5/ND5D2/ND5D4
5-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND5D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.019 0.005*SL 0.027 0.004*SL 0.081 0.002*SL 0.088 0.002*SL 0.021 0.005*SL 0.027 0.004*SL 0.085 0.002*SL 0.091 0.002*SL 0.021 0.005*SL 0.026 0.004*SL 0.090 0.002*SL 0.091 0.002*SL 0.020 0.005*SL 0.027 0.003*SL 0.072 0.002*SL 0.087 0.002*SL 0.028 0.004*SL 0.028 0.003*SL 0.074 0.002*SL 0.088 0.002*SL
Parameter
Delay [ns]
Group3*
0.012 0.005*SL 0.024 0.004*SL 0.082 0.002*SL 0.097 0.002*SL 0.011 0.005*SL 0.026 0.004*SL 0.087 0.002*SL 0.100 0.002*SL 0.013 0.005*SL 0.026 0.004*SL 0.092 0.002*SL 0.101 0.002*SL 0.013 0.005*SL 0.023 0.004*SL 0.074 0.002*SL 0.096 0.002*SL 0.016 0.005*SL 0.024 0.004*SL 0.076 0.002*SL 0.097 0.002*SL
0.028 0.020 0.004*SL 0.033 0.024 0.004*SL 0.084 0.078 0.003*SL 0.090 0.083 0.003*SL 0.029 0.020 0.005*SL 0.032 0.023 0.004*SL 0.089 0.083 0.003*SL 0.093 0.086 0.003*SL 0.030 0.020 0.005*SL 0.032 0.023 0.004*SL 0.093 0.087 0.003*SL 0.094 0.087 0.003*SL 0.029 0.020 0.005*SL 0.033 0.024 0.004*SL 0.075 0.069 0.003*SL 0.089 0.082 0.003*SL 0.034 0.022 0.006*SL 0.033 0.024 0.004*SL 0.077 0.072 0.003*SL 0.090 0.083 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-39
STDH150
ND5/ND5D2/ND5D4
5-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND5D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.023 0.002*SL 0.025 0.002*SL 0.091 0.001*SL 0.091 0.001*SL 0.023 0.002*SL 0.025 0.002*SL 0.096 0.001*SL 0.093 0.001*SL 0.022 0.002*SL 0.025 0.002*SL 0.100 0.001*SL 0.094 0.001*SL 0.023 0.002*SL 0.026 0.002*SL 0.080 0.001*SL 0.090 0.001*SL 0.023 0.002*SL 0.025 0.002*SL 0.084 0.001*SL 0.090 0.001*SL
Group3*
0.015 0.002*SL 0.023 0.002*SL 0.095 0.001*SL 0.101 0.001*SL 0.015 0.002*SL 0.025 0.002*SL 0.100 0.001*SL 0.104 0.001*SL 0.014 0.002*SL 0.025 0.002*SL 0.104 0.001*SL 0.104 0.001*SL 0.014 0.002*SL 0.024 0.002*SL 0.084 0.001*SL 0.100 0.001*SL 0.014 0.002*SL 0.025 0.002*SL 0.087 0.001*SL 0.101 0.001*SL
0.027 0.022 0.002*SL 0.028 0.024 0.002*SL 0.092 0.089 0.002*SL 0.092 0.088 0.002*SL 0.027 0.022 0.003*SL 0.028 0.023 0.002*SL 0.097 0.094 0.002*SL 0.095 0.091 0.002*SL 0.026 0.021 0.003*SL 0.028 0.023 0.002*SL 0.101 0.098 0.002*SL 0.095 0.091 0.002*SL 0.027 0.022 0.003*SL 0.028 0.023 0.003*SL 0.082 0.078 0.002*SL 0.091 0.087 0.002*SL 0.027 0.022 0.002*SL 0.028 0.023 0.002*SL 0.085 0.082 0.002*SL 0.091 0.088 0.002*SL *Group1 *Group2 *Group3
STDH150
3-40
Samsung ASIC
ND6/ND6D2/ND6D4
6-Input NAND with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
4.33 Input Load (SL) ND6D2 Gate Count ND6D2 4.67 ND6D4 ND6D4 6.00
Samsung ASIC
3-41
STDH150
ND6/ND6D2/ND6D4
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.031 0.009*SL 0.031 0.007*SL 0.077 0.005*SL 0.080 0.004*SL 0.031 0.009*SL 0.031 0.007*SL 0.102 0.005*SL 0.112 0.005*SL 0.032 0.009*SL 0.045 0.007*SL 0.076 0.005*SL 0.096 0.005*SL 0.017 0.010*SL 0.017 0.007*SL 0.098 0.004*SL 0.102 0.004*SL 0.016 0.010*SL 0.017 0.007*SL 0.130 0.004*SL 0.128 0.004*SL 0.020 0.009*SL 0.020 0.007*SL 0.115 0.004*SL 0.102 0.004*SL
Parameter
Delay [ns]
Group3*
0.024 0.010*SL 0.028 0.007*SL 0.083 0.004*SL 0.089 0.004*SL 0.025 0.010*SL 0.027 0.007*SL 0.109 0.004*SL 0.121 0.004*SL 0.025 0.010*SL 0.042 0.007*SL 0.082 0.004*SL 0.111 0.004*SL 0.012 0.010*SL 0.014 0.007*SL 0.098 0.004*SL 0.104 0.004*SL 0.012 0.010*SL 0.014 0.007*SL 0.130 0.004*SL 0.130 0.004*SL 0.013 0.010*SL 0.014 0.007*SL 0.115 0.004*SL 0.104 0.004*SL
0.048 0.028 0.010*SL 0.042 0.026 0.008*SL 0.083 0.071 0.006*SL 0.085 0.073 0.006*SL 0.049 0.030 0.009*SL 0.042 0.026 0.008*SL 0.109 0.096 0.006*SL 0.117 0.105 0.006*SL 0.049 0.029 0.010*SL 0.055 0.038 0.009*SL 0.083 0.070 0.006*SL 0.101 0.086 0.008*SL 0.038 0.021 0.009*SL 0.032 0.019 0.007*SL 0.105 0.096 0.005*SL 0.109 0.099 0.005*SL 0.038 0.021 0.008*SL 0.032 0.019 0.007*SL 0.137 0.128 0.005*SL 0.134 0.125 0.005*SL 0.041 0.025 0.008*SL 0.033 0.019 0.007*SL 0.122 0.112 0.005*SL 0.108 0.098 0.005*SL *Group1 *Group2 *Group3
STDH150
3-42
Samsung ASIC
ND6/ND6D2/ND6D4
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND6D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.019 0.005*SL 0.027 0.004*SL 0.080 0.002*SL 0.087 0.002*SL 0.020 0.005*SL 0.026 0.004*SL 0.085 0.002*SL 0.090 0.002*SL 0.020 0.005*SL 0.026 0.004*SL 0.089 0.002*SL 0.090 0.002*SL 0.021 0.005*SL 0.028 0.003*SL 0.084 0.002*SL 0.093 0.002*SL 0.022 0.005*SL 0.026 0.004*SL 0.089 0.002*SL 0.096 0.002*SL 0.022 0.005*SL 0.028 0.003*SL 0.094 0.002*SL 0.097 0.002*SL
Parameter
Delay [ns]
Group3*
0.012 0.005*SL 0.023 0.004*SL 0.081 0.002*SL 0.096 0.002*SL 0.011 0.005*SL 0.026 0.004*SL 0.087 0.002*SL 0.099 0.002*SL 0.013 0.005*SL 0.026 0.004*SL 0.091 0.002*SL 0.100 0.002*SL 0.013 0.005*SL 0.024 0.004*SL 0.086 0.002*SL 0.103 0.002*SL 0.013 0.005*SL 0.025 0.004*SL 0.091 0.002*SL 0.106 0.002*SL 0.013 0.005*SL 0.023 0.004*SL 0.096 0.002*SL 0.106 0.002*SL
0.029 0.020 0.004*SL 0.032 0.023 0.005*SL 0.083 0.077 0.003*SL 0.089 0.082 0.003*SL 0.029 0.020 0.005*SL 0.032 0.023 0.004*SL 0.088 0.082 0.003*SL 0.092 0.085 0.003*SL 0.030 0.020 0.005*SL 0.032 0.023 0.004*SL 0.092 0.086 0.003*SL 0.093 0.086 0.003*SL 0.030 0.021 0.005*SL 0.033 0.024 0.004*SL 0.087 0.082 0.003*SL 0.096 0.089 0.003*SL 0.031 0.021 0.005*SL 0.033 0.026 0.004*SL 0.092 0.086 0.003*SL 0.099 0.092 0.003*SL 0.031 0.021 0.005*SL 0.033 0.024 0.004*SL 0.097 0.091 0.003*SL 0.100 0.093 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-43
STDH150
ND6/ND6D2/ND6D4
6-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND6D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.023 0.002*SL 0.025 0.002*SL 0.091 0.001*SL 0.090 0.001*SL 0.023 0.002*SL 0.025 0.002*SL 0.096 0.001*SL 0.093 0.001*SL 0.023 0.002*SL 0.025 0.002*SL 0.100 0.001*SL 0.094 0.001*SL 0.024 0.002*SL 0.024 0.002*SL 0.096 0.001*SL 0.099 0.001*SL 0.024 0.002*SL 0.025 0.002*SL 0.101 0.001*SL 0.102 0.001*SL 0.025 0.002*SL 0.024 0.002*SL 0.105 0.001*SL 0.102 0.001*SL
Parameter
Delay [ns]
Group3*
0.014 0.002*SL 0.023 0.002*SL 0.094 0.001*SL 0.101 0.001*SL 0.015 0.002*SL 0.025 0.002*SL 0.100 0.001*SL 0.104 0.001*SL 0.015 0.002*SL 0.024 0.002*SL 0.104 0.001*SL 0.104 0.001*SL 0.015 0.002*SL 0.024 0.002*SL 0.100 0.001*SL 0.109 0.001*SL 0.015 0.002*SL 0.024 0.002*SL 0.105 0.001*SL 0.112 0.001*SL 0.015 0.002*SL 0.023 0.002*SL 0.110 0.001*SL 0.112 0.001*SL
0.027 0.022 0.002*SL 0.027 0.023 0.002*SL 0.092 0.089 0.002*SL 0.091 0.088 0.002*SL 0.027 0.021 0.003*SL 0.028 0.023 0.002*SL 0.097 0.094 0.002*SL 0.094 0.091 0.002*SL 0.027 0.022 0.002*SL 0.028 0.024 0.002*SL 0.101 0.098 0.002*SL 0.095 0.091 0.002*SL 0.028 0.023 0.003*SL 0.027 0.022 0.002*SL 0.097 0.094 0.002*SL 0.100 0.096 0.002*SL 0.027 0.022 0.003*SL 0.027 0.023 0.002*SL 0.102 0.099 0.002*SL 0.103 0.099 0.002*SL 0.029 0.024 0.003*SL 0.028 0.024 0.002*SL 0.107 0.103 0.002*SL 0.103 0.099 0.002*SL *Group1 *Group2 *Group3
STDH150
3-44
Samsung ASIC
ND8/ND8D2/ND8D4
8-Input NAND with 1X/2X/4X Drive Logic Symbol Truth Table
Other States
Cell Data
Input Load (SL) ND8D2 ND8D4 Gate Count 5.00 ND8D2 5.33 ND8D4 6.67
Samsung ASIC
3-45
STDH150
ND8/ND8D2/ND8D4
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.018 0.015*SL 0.021 0.009*SL 0.079 0.007*SL 0.081 0.005*SL 0.015 0.015*SL 0.021 0.009*SL 0.087 0.007*SL 0.086 0.005*SL 0.016 0.015*SL 0.021 0.010*SL 0.093 0.007*SL 0.088 0.005*SL 0.014 0.015*SL 0.021 0.010*SL 0.097 0.007*SL 0.089 0.005*SL 0.017 0.015*SL 0.021 0.009*SL 0.085 0.007*SL 0.087 0.005*SL 0.017 0.015*SL 0.021 0.009*SL 0.092 0.007*SL 0.092 0.005*SL 0.017 0.015*SL 0.022 0.009*SL 0.097 0.007*SL 0.095 0.005*SL 0.017 0.015*SL 0.022 0.009*SL 0.102 0.007*SL 0.096 0.005*SL
Parameter
Delay [ns]
Group3*
0.013 0.015*SL 0.014 0.010*SL 0.078 0.007*SL 0.084 0.005*SL 0.011 0.016*SL 0.014 0.010*SL 0.087 0.007*SL 0.088 0.005*SL 0.012 0.015*SL 0.015 0.010*SL 0.093 0.007*SL 0.091 0.005*SL 0.011 0.016*SL 0.015 0.010*SL 0.097 0.007*SL 0.092 0.005*SL 0.013 0.015*SL 0.014 0.010*SL 0.086 0.007*SL 0.090 0.005*SL 0.013 0.015*SL 0.014 0.010*SL 0.092 0.007*SL 0.095 0.005*SL 0.013 0.015*SL 0.014 0.010*SL 0.098 0.007*SL 0.097 0.005*SL 0.012 0.015*SL 0.015 0.010*SL 0.102 0.007*SL 0.098 0.005*SL
0.053 0.027 0.013*SL 0.039 0.019 0.010*SL 0.092 0.078 0.007*SL 0.089 0.076 0.007*SL 0.047 0.019 0.014*SL 0.039 0.019 0.010*SL 0.100 0.086 0.007*SL 0.094 0.081 0.007*SL 0.047 0.017 0.015*SL 0.038 0.018 0.010*SL 0.105 0.091 0.007*SL 0.096 0.083 0.007*SL 0.048 0.020 0.014*SL 0.039 0.018 0.010*SL 0.110 0.096 0.007*SL 0.098 0.085 0.007*SL 0.048 0.019 0.015*SL 0.039 0.018 0.010*SL 0.098 0.084 0.007*SL 0.095 0.082 0.007*SL 0.048 0.019 0.015*SL 0.039 0.018 0.010*SL 0.105 0.090 0.007*SL 0.100 0.087 0.007*SL 0.048 0.019 0.015*SL 0.039 0.018 0.010*SL 0.110 0.096 0.007*SL 0.103 0.090 0.007*SL 0.048 0.018 0.015*SL 0.039 0.018 0.010*SL 0.115 0.101 0.007*SL 0.104 0.091 0.007*SL *Group3 *Group1 *Group2
STDH150
3-46
Samsung ASIC
ND8/ND8D2/ND8D4
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND8D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.022 0.005*SL 0.028 0.003*SL 0.092 0.002*SL 0.096 0.002*SL 0.021 0.005*SL 0.027 0.004*SL 0.099 0.002*SL 0.101 0.002*SL 0.021 0.005*SL 0.027 0.004*SL 0.104 0.002*SL 0.104 0.002*SL 0.020 0.005*SL 0.028 0.004*SL 0.109 0.002*SL 0.105 0.002*SL 0.021 0.005*SL 0.028 0.003*SL 0.095 0.002*SL 0.100 0.002*SL 0.022 0.005*SL 0.028 0.004*SL 0.101 0.002*SL 0.106 0.002*SL 0.022 0.005*SL 0.029 0.003*SL 0.107 0.002*SL 0.107 0.002*SL 0.023 0.005*SL 0.026 0.004*SL 0.112 0.002*SL 0.110 0.002*SL
Group3*
0.013 0.005*SL 0.024 0.004*SL 0.094 0.002*SL 0.105 0.002*SL 0.013 0.005*SL 0.026 0.004*SL 0.101 0.002*SL 0.111 0.002*SL 0.013 0.005*SL 0.026 0.004*SL 0.106 0.002*SL 0.113 0.002*SL 0.012 0.005*SL 0.026 0.004*SL 0.111 0.002*SL 0.114 0.002*SL 0.014 0.005*SL 0.023 0.004*SL 0.097 0.002*SL 0.110 0.002*SL 0.013 0.005*SL 0.026 0.004*SL 0.104 0.002*SL 0.115 0.002*SL 0.014 0.005*SL 0.023 0.004*SL 0.110 0.002*SL 0.117 0.002*SL 0.014 0.005*SL 0.026 0.004*SL 0.115 0.002*SL 0.119 0.002*SL
0.031 0.021 0.005*SL 0.033 0.024 0.004*SL 0.095 0.089 0.003*SL 0.098 0.092 0.003*SL 0.031 0.022 0.005*SL 0.034 0.027 0.004*SL 0.102 0.096 0.003*SL 0.104 0.097 0.003*SL 0.030 0.021 0.005*SL 0.034 0.027 0.004*SL 0.108 0.102 0.003*SL 0.106 0.099 0.003*SL 0.030 0.021 0.004*SL 0.033 0.025 0.004*SL 0.112 0.106 0.003*SL 0.107 0.101 0.003*SL 0.030 0.021 0.005*SL 0.034 0.025 0.004*SL 0.098 0.092 0.003*SL 0.103 0.096 0.003*SL 0.031 0.022 0.005*SL 0.033 0.024 0.005*SL 0.104 0.099 0.003*SL 0.108 0.101 0.003*SL 0.031 0.022 0.005*SL 0.034 0.025 0.004*SL 0.110 0.105 0.003*SL 0.109 0.103 0.003*SL 0.032 0.023 0.005*SL 0.033 0.025 0.004*SL 0.115 0.109 0.003*SL 0.112 0.105 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-47
STDH150
ND8/ND8D2/ND8D4
8-Input NAND with 1X/2X/4X Drive Switching Characteristics
ND8D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.025 0.002*SL 0.026 0.002*SL 0.104 0.001*SL 0.100 0.001*SL 0.023 0.002*SL 0.025 0.002*SL 0.111 0.001*SL 0.105 0.001*SL 0.026 0.002*SL 0.027 0.002*SL 0.116 0.001*SL 0.107 0.001*SL 0.026 0.002*SL 0.027 0.002*SL 0.121 0.001*SL 0.108 0.001*SL 0.026 0.002*SL 0.025 0.002*SL 0.109 0.001*SL 0.107 0.001*SL 0.024 0.002*SL 0.025 0.002*SL 0.115 0.001*SL 0.112 0.001*SL 0.027 0.002*SL 0.025 0.002*SL 0.121 0.001*SL 0.114 0.001*SL 0.028 0.002*SL 0.026 0.002*SL 0.126 0.001*SL 0.115 0.001*SL
Parameter
Delay [ns]
Group3*
0.016 0.002*SL 0.026 0.002*SL 0.108 0.001*SL 0.110 0.001*SL 0.014 0.002*SL 0.025 0.002*SL 0.115 0.001*SL 0.115 0.001*SL 0.015 0.002*SL 0.025 0.002*SL 0.120 0.001*SL 0.118 0.001*SL 0.016 0.002*SL 0.024 0.002*SL 0.125 0.001*SL 0.119 0.001*SL 0.016 0.002*SL 0.026 0.002*SL 0.113 0.001*SL 0.118 0.001*SL 0.016 0.002*SL 0.025 0.002*SL 0.120 0.001*SL 0.123 0.001*SL 0.017 0.002*SL 0.026 0.002*SL 0.125 0.001*SL 0.125 0.001*SL 0.016 0.002*SL 0.024 0.002*SL 0.130 0.001*SL 0.126 0.001*SL
0.029 0.023 0.003*SL 0.029 0.024 0.002*SL 0.105 0.102 0.002*SL 0.101 0.097 0.002*SL 0.028 0.024 0.002*SL 0.029 0.025 0.002*SL 0.112 0.109 0.002*SL 0.106 0.102 0.002*SL 0.030 0.025 0.002*SL 0.030 0.026 0.002*SL 0.117 0.114 0.002*SL 0.108 0.104 0.002*SL 0.030 0.025 0.003*SL 0.031 0.027 0.002*SL 0.123 0.119 0.002*SL 0.109 0.106 0.002*SL 0.030 0.025 0.003*SL 0.028 0.024 0.002*SL 0.110 0.106 0.002*SL 0.108 0.104 0.002*SL 0.029 0.026 0.002*SL 0.029 0.025 0.002*SL 0.116 0.113 0.002*SL 0.113 0.109 0.002*SL 0.031 0.026 0.002*SL 0.028 0.024 0.002*SL 0.122 0.119 0.002*SL 0.115 0.112 0.002*SL 0.031 0.026 0.003*SL 0.029 0.024 0.002*SL 0.127 0.124 0.002*SL 0.116 0.113 0.002*SL *Group3 *Group1 *Group2
STDH150
3-48
Samsung ASIC
NR2/NR2A/NR2D2/NR2D4/NR2D8
2-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
1.33 NR2A 1.67 NR2A Input Load (SL) NR2D2 Gate Count NR2D2 2.00 NR2D4 NR2D4 3.67 NR2D8 5.33 NR2D8
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.037 0.019*SL 0.026 0.006*SL 0.029 0.009*SL 0.023 0.004*SL 0.032 0.019*SL 0.029 0.006*SL 0.033 0.009*SL 0.026 0.004*SL
Parameter
Delay [ns]
Group3*
0.027 0.020*SL 0.017 0.007*SL 0.029 0.009*SL 0.024 0.004*SL 0.027 0.020*SL 0.022 0.007*SL 0.033 0.009*SL 0.027 0.004*SL
0.077 0.042 0.018*SL 0.040 0.029 0.005*SL 0.046 0.028 0.009*SL 0.027 0.016 0.005*SL 0.073 0.037 0.018*SL 0.044 0.034 0.005*SL 0.050 0.032 0.009*SL 0.031 0.021 0.005*SL *Group3 *Group1 *Group2
NR2A
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.036 0.009*SL 0.028 0.007*SL 0.025 0.004*SL 0.027 0.004*SL 0.031 0.009*SL 0.036 0.007*SL 0.029 0.004*SL 0.033 0.004*SL
Group3*
0.025 0.010*SL 0.018 0.008*SL 0.025 0.004*SL 0.028 0.004*SL 0.023 0.010*SL 0.029 0.007*SL 0.030 0.004*SL 0.034 0.004*SL
0.057 0.042 0.008*SL 0.042 0.028 0.007*SL 0.031 0.020 0.006*SL 0.033 0.022 0.005*SL 0.050 0.032 0.009*SL 0.049 0.035 0.007*SL 0.037 0.026 0.005*SL 0.040 0.031 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-49
STDH150
NR2/NR2A/NR2D2/NR2D4/NR2D8
2-Input with 1X/2X P-Tr, N-Tr/2X/4X/8X Drive Switching Characteristics
NR2D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.037 0.009*SL 0.026 0.003*SL 0.028 0.004*SL 0.019 0.002*SL 0.033 0.009*SL 0.031 0.003*SL 0.032 0.004*SL 0.023 0.002*SL
Parameter
Delay [ns]
Group3*
0.025 0.010*SL 0.017 0.003*SL 0.028 0.004*SL 0.024 0.002*SL 0.024 0.010*SL 0.020 0.003*SL 0.032 0.004*SL 0.026 0.002*SL
0.060 0.045 0.007*SL 0.033 0.028 0.003*SL 0.035 0.025 0.005*SL 0.020 0.014 0.003*SL 0.053 0.035 0.009*SL 0.037 0.032 0.003*SL 0.040 0.030 0.005*SL 0.025 0.019 0.003*SL *Group1 *Group2 *Group3
NR2D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.041 0.005*SL 0.028 0.001*SL 0.027 0.002*SL 0.017 0.001*SL 0.036 0.005*SL 0.033 0.001*SL 0.032 0.002*SL 0.021 0.001*SL
Group3*
0.026 0.005*SL 0.018 0.002*SL 0.028 0.002*SL 0.024 0.001*SL 0.025 0.005*SL 0.023 0.002*SL 0.033 0.002*SL 0.026 0.001*SL
0.053 0.046 0.003*SL 0.030 0.026 0.002*SL 0.030 0.025 0.003*SL 0.017 0.014 0.002*SL 0.045 0.036 0.005*SL 0.035 0.031 0.002*SL 0.035 0.030 0.003*SL 0.022 0.019 0.002*SL *Group1 *Group2 *Group3
NR2D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.026 0.001*SL 0.022 0.001*SL 0.100 0.001*SL 0.069 0.001*SL 0.027 0.001*SL 0.022 0.001*SL 0.104 0.001*SL 0.072 0.001*SL
Group3*
0.018 0.001*SL 0.020 0.001*SL 0.105 0.001*SL 0.077 0.000*SL 0.018 0.001*SL 0.019 0.001*SL 0.110 0.001*SL 0.080 0.000*SL
0.028 0.025 0.001*SL 0.024 0.022 0.001*SL 0.100 0.099 0.001*SL 0.069 0.068 0.001*SL 0.029 0.026 0.001*SL 0.023 0.021 0.001*SL 0.104 0.102 0.001*SL 0.073 0.071 0.001*SL *Group1 *Group2 *Group3
STDH150
3-50
Samsung ASIC
NR2B/NR2BD2/NR2BD4/NR2BD8
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
NR2B NR2B 1.67 Input Load (SL) NR2BD2 NR2BD4 Gate Count NR2BD2 NR2BD4 2.67 4.00 NR2BD8 NR2BD8 5.67
Switching Characteristics
NR2B
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.028 0.020*SL 0.022 0.007*SL 0.041 0.009*SL 0.055 0.004*SL 0.032 0.019*SL 0.029 0.006*SL 0.034 0.009*SL 0.025 0.004*SL
Parameter
Delay [ns]
Group3*
0.027 0.020*SL 0.015 0.007*SL 0.041 0.009*SL 0.057 0.004*SL 0.027 0.020*SL 0.022 0.007*SL 0.034 0.009*SL 0.026 0.004*SL
0.069 0.032 0.019*SL 0.035 0.021 0.007*SL 0.058 0.040 0.009*SL 0.061 0.051 0.005*SL 0.073 0.037 0.018*SL 0.044 0.034 0.005*SL 0.051 0.032 0.009*SL 0.030 0.020 0.005*SL *Group3 *Group1 *Group2
NR2BD2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.028 0.010*SL 0.030 0.003*SL 0.049 0.004*SL 0.066 0.002*SL 0.035 0.009*SL 0.031 0.003*SL 0.033 0.004*SL 0.023 0.002*SL
Group3*
0.026 0.010*SL 0.024 0.003*SL 0.049 0.004*SL 0.074 0.002*SL 0.026 0.010*SL 0.021 0.003*SL 0.034 0.004*SL 0.026 0.002*SL
0.050 0.033 0.009*SL 0.035 0.027 0.004*SL 0.057 0.048 0.005*SL 0.069 0.063 0.003*SL 0.054 0.035 0.009*SL 0.038 0.032 0.003*SL 0.041 0.031 0.005*SL 0.024 0.018 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-51
STDH150
NR2B/NR2BD2/NR2BD4/NR2BD8
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
NR2BD4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.038 0.005*SL 0.046 0.002*SL 0.065 0.002*SL 0.092 0.001*SL 0.038 0.005*SL 0.033 0.001*SL 0.033 0.002*SL 0.021 0.001*SL
Parameter
Delay [ns]
Group3*
0.030 0.005*SL 0.043 0.002*SL 0.066 0.002*SL 0.107 0.001*SL 0.029 0.005*SL 0.023 0.002*SL 0.036 0.002*SL 0.026 0.001*SL
0.053 0.049 0.002*SL 0.048 0.043 0.002*SL 0.068 0.063 0.003*SL 0.093 0.089 0.002*SL 0.047 0.037 0.005*SL 0.035 0.030 0.002*SL 0.037 0.031 0.003*SL 0.021 0.018 0.002*SL *Group1 *Group2 *Group3
NR2BD8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.027 0.001*SL 0.021 0.001*SL 0.112 0.001*SL 0.103 0.001*SL 0.027 0.001*SL 0.022 0.001*SL 0.104 0.001*SL 0.072 0.001*SL
Group3*
0.017 0.001*SL 0.019 0.001*SL 0.117 0.001*SL 0.111 0.000*SL 0.018 0.001*SL 0.019 0.001*SL 0.110 0.001*SL 0.080 0.000*SL
0.029 0.026 0.001*SL 0.023 0.022 0.001*SL 0.112 0.110 0.001*SL 0.103 0.102 0.001*SL 0.028 0.024 0.002*SL 0.023 0.021 0.001*SL 0.104 0.103 0.001*SL 0.072 0.071 0.001*SL *Group1 *Group2 *Group3
STDH150
3-52
Samsung ASIC
NR3/NR3A/NR3D2/NR3D4
3-Input with 1X/2X P-Tr, N-Tr/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
Input Load (SL) 1.67 NR3A NR3A 2.33 Gate Count NR3D2 NR3D2 3.00 NR3D4 NR3D4 3.67
Samsung ASIC
3-53
STDH150
NR3/NR3A/NR3D2/NR3D4
3-Input with 1X/2X P-Tr, N-Tr/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.050 0.029*SL 0.025 0.011*SL 0.030 0.013*SL 0.028 0.006*SL 0.047 0.029*SL 0.031 0.011*SL 0.043 0.013*SL 0.033 0.006*SL 0.046 0.029*SL 0.040 0.011*SL 0.047 0.013*SL 0.035 0.006*SL
Parameter
Delay [ns]
Group3*
0.045 0.029*SL 0.016 0.012*SL 0.030 0.013*SL 0.028 0.006*SL 0.045 0.029*SL 0.024 0.012*SL 0.043 0.013*SL 0.034 0.006*SL 0.045 0.029*SL 0.032 0.012*SL 0.047 0.013*SL 0.037 0.006*SL
0.111 0.056 0.027*SL 0.050 0.030 0.010*SL 0.057 0.031 0.013*SL 0.039 0.025 0.007*SL 0.108 0.053 0.028*SL 0.056 0.036 0.010*SL 0.069 0.042 0.013*SL 0.044 0.031 0.007*SL 0.106 0.049 0.028*SL 0.064 0.041 0.011*SL 0.073 0.047 0.013*SL 0.047 0.034 0.007*SL *Group1 *Group2 *Group3
NR3A
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.047 0.014*SL 0.027 0.009*SL 0.027 0.007*SL 0.031 0.005*SL 0.044 0.014*SL 0.037 0.009*SL 0.039 0.007*SL 0.039 0.005*SL 0.042 0.014*SL 0.050 0.009*SL 0.043 0.007*SL 0.044 0.005*SL
Group3*
0.038 0.015*SL 0.020 0.010*SL 0.027 0.007*SL 0.032 0.005*SL 0.038 0.015*SL 0.032 0.010*SL 0.039 0.007*SL 0.040 0.005*SL 0.037 0.015*SL 0.045 0.010*SL 0.043 0.007*SL 0.046 0.005*SL
0.078 0.052 0.013*SL 0.048 0.033 0.008*SL 0.039 0.025 0.007*SL 0.040 0.028 0.006*SL 0.074 0.048 0.013*SL 0.059 0.043 0.008*SL 0.051 0.037 0.007*SL 0.049 0.038 0.005*SL 0.070 0.041 0.014*SL 0.071 0.054 0.008*SL 0.056 0.042 0.007*SL 0.054 0.042 0.006*SL *Group3 *Group1 *Group2
STDH150
3-54
Samsung ASIC
NR3/NR3A/NR3D2/NR3D4
3-Input with 1X/2X P-Tr, N-Tr/2X/4X Drive Switching Characteristics
NR3D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.051 0.014*SL 0.028 0.006*SL 0.029 0.007*SL 0.026 0.003*SL 0.046 0.015*SL 0.033 0.006*SL 0.041 0.007*SL 0.032 0.003*SL 0.045 0.015*SL 0.042 0.006*SL 0.046 0.007*SL 0.034 0.003*SL
Parameter
Delay [ns]
Group3*
0.041 0.015*SL 0.016 0.006*SL 0.029 0.007*SL 0.028 0.003*SL 0.042 0.015*SL 0.023 0.006*SL 0.041 0.007*SL 0.033 0.003*SL 0.041 0.015*SL 0.032 0.006*SL 0.046 0.007*SL 0.036 0.003*SL
0.082 0.057 0.013*SL 0.039 0.028 0.005*SL 0.042 0.029 0.007*SL 0.030 0.021 0.004*SL 0.078 0.051 0.013*SL 0.045 0.035 0.005*SL 0.054 0.040 0.007*SL 0.037 0.029 0.004*SL 0.075 0.047 0.014*SL 0.052 0.039 0.006*SL 0.058 0.045 0.007*SL 0.039 0.032 0.004*SL *Group1 *Group2 *Group3
NR3D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.024 0.002*SL 0.023 0.002*SL 0.099 0.001*SL 0.078 0.001*SL 0.026 0.002*SL 0.022 0.002*SL 0.110 0.001*SL 0.083 0.001*SL 0.025 0.002*SL 0.024 0.002*SL 0.115 0.001*SL 0.087 0.001*SL
Group3*
0.015 0.002*SL 0.020 0.002*SL 0.103 0.001*SL 0.086 0.001*SL 0.016 0.002*SL 0.019 0.002*SL 0.114 0.001*SL 0.091 0.001*SL 0.016 0.002*SL 0.021 0.002*SL 0.119 0.001*SL 0.095 0.001*SL
0.029 0.025 0.002*SL 0.026 0.021 0.002*SL 0.100 0.097 0.002*SL 0.079 0.075 0.002*SL 0.029 0.024 0.003*SL 0.025 0.020 0.002*SL 0.111 0.108 0.002*SL 0.084 0.081 0.002*SL 0.029 0.024 0.003*SL 0.027 0.023 0.002*SL 0.116 0.113 0.002*SL 0.088 0.084 0.002*SL *Group3 *Group1 *Group2
Samsung ASIC
3-55
STDH150
NR4/NR4D2/NR4D4
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
3.33 Input Load (SL) NR4D2 Gate Count NR4D2 3.67 NR4D4 NR4D4 4.67
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.028 0.015*SL 0.026 0.012*SL 0.125 0.007*SL 0.111 0.007*SL 0.027 0.015*SL 0.026 0.012*SL 0.132 0.007*SL 0.119 0.007*SL 0.027 0.015*SL 0.028 0.012*SL 0.125 0.007*SL 0.117 0.007*SL 0.027 0.015*SL 0.029 0.011*SL 0.133 0.007*SL 0.126 0.007*SL
Parameter
Delay [ns]
Group3*
0.024 0.016*SL 0.021 0.012*SL 0.126 0.007*SL 0.113 0.006*SL 0.024 0.016*SL 0.022 0.012*SL 0.133 0.007*SL 0.121 0.006*SL 0.024 0.016*SL 0.023 0.012*SL 0.127 0.007*SL 0.120 0.006*SL 0.024 0.016*SL 0.022 0.012*SL 0.134 0.007*SL 0.128 0.006*SL
0.061 0.033 0.014*SL 0.050 0.028 0.011*SL 0.137 0.121 0.008*SL 0.122 0.106 0.008*SL 0.061 0.033 0.014*SL 0.050 0.027 0.011*SL 0.144 0.128 0.008*SL 0.130 0.114 0.008*SL 0.061 0.033 0.014*SL 0.050 0.027 0.012*SL 0.137 0.121 0.008*SL 0.128 0.112 0.008*SL 0.060 0.033 0.014*SL 0.050 0.026 0.012*SL 0.145 0.129 0.008*SL 0.136 0.121 0.008*SL *Group3 *Group1 *Group2
STDH150
3-56
Samsung ASIC
NR4/NR4D2/NR4D4
4-Input with 1X/2X/4X Drive Switching Characteristics
NR4D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.021 0.005*SL 0.017 0.004*SL 0.084 0.002*SL 0.058 0.002*SL 0.022 0.005*SL 0.016 0.004*SL 0.088 0.002*SL 0.062 0.002*SL 0.022 0.005*SL 0.019 0.003*SL 0.085 0.002*SL 0.060 0.002*SL 0.022 0.005*SL 0.017 0.004*SL 0.089 0.002*SL 0.064 0.002*SL
Parameter
Delay [ns]
Group3*
0.014 0.005*SL 0.013 0.004*SL 0.087 0.002*SL 0.062 0.002*SL 0.014 0.005*SL 0.014 0.004*SL 0.091 0.002*SL 0.066 0.002*SL 0.014 0.005*SL 0.014 0.004*SL 0.088 0.002*SL 0.064 0.002*SL 0.013 0.005*SL 0.016 0.004*SL 0.092 0.002*SL 0.069 0.002*SL
0.031 0.021 0.005*SL 0.023 0.015 0.004*SL 0.087 0.081 0.003*SL 0.061 0.055 0.003*SL 0.031 0.021 0.005*SL 0.023 0.016 0.004*SL 0.091 0.085 0.003*SL 0.065 0.059 0.003*SL 0.030 0.021 0.005*SL 0.025 0.017 0.004*SL 0.088 0.082 0.003*SL 0.063 0.057 0.003*SL 0.031 0.021 0.005*SL 0.024 0.016 0.004*SL 0.092 0.086 0.003*SL 0.067 0.061 0.003*SL *Group3 *Group1 *Group2
NR4D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.028 0.002*SL 0.024 0.002*SL 0.095 0.001*SL 0.068 0.001*SL 0.028 0.002*SL 0.022 0.002*SL 0.099 0.001*SL 0.072 0.001*SL 0.026 0.002*SL 0.024 0.002*SL 0.099 0.001*SL 0.071 0.001*SL 0.029 0.002*SL 0.024 0.002*SL 0.102 0.001*SL 0.075 0.001*SL
Group3*
0.020 0.002*SL 0.022 0.002*SL 0.103 0.001*SL 0.077 0.001*SL 0.022 0.002*SL 0.021 0.002*SL 0.107 0.001*SL 0.080 0.001*SL 0.021 0.002*SL 0.022 0.002*SL 0.106 0.001*SL 0.080 0.001*SL 0.022 0.002*SL 0.022 0.002*SL 0.110 0.001*SL 0.084 0.001*SL
0.032 0.027 0.002*SL 0.026 0.022 0.002*SL 0.097 0.093 0.002*SL 0.069 0.065 0.002*SL 0.032 0.027 0.002*SL 0.025 0.021 0.002*SL 0.100 0.097 0.002*SL 0.073 0.069 0.002*SL 0.032 0.027 0.002*SL 0.026 0.022 0.002*SL 0.100 0.096 0.002*SL 0.072 0.069 0.002*SL 0.032 0.026 0.003*SL 0.027 0.023 0.002*SL 0.104 0.100 0.002*SL 0.076 0.072 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-57
STDH150
NR5/NR5D2/NR5D4
5-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
4.00 Input Load (SL) NR5D2 Gate Count NR5D2 4.33 NR5D4 NR5D4 5.00
STDH150
3-58
Samsung ASIC
NR5/NR5D2/NR5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.022 0.009*SL 0.020 0.007*SL 0.088 0.004*SL 0.071 0.004*SL 0.022 0.009*SL 0.020 0.007*SL 0.099 0.004*SL 0.077 0.004*SL 0.022 0.009*SL 0.021 0.007*SL 0.104 0.004*SL 0.081 0.004*SL 0.018 0.010*SL 0.021 0.007*SL 0.079 0.004*SL 0.064 0.004*SL 0.020 0.009*SL 0.022 0.007*SL 0.083 0.004*SL 0.068 0.004*SL
Group3*
0.016 0.010*SL 0.016 0.007*SL 0.090 0.004*SL 0.074 0.004*SL 0.015 0.010*SL 0.016 0.007*SL 0.101 0.004*SL 0.080 0.004*SL 0.015 0.010*SL 0.016 0.007*SL 0.105 0.004*SL 0.083 0.004*SL 0.015 0.010*SL 0.016 0.007*SL 0.081 0.004*SL 0.067 0.004*SL 0.014 0.010*SL 0.016 0.007*SL 0.085 0.004*SL 0.071 0.004*SL
0.041 0.023 0.009*SL 0.033 0.017 0.008*SL 0.095 0.085 0.005*SL 0.078 0.068 0.005*SL 0.041 0.024 0.009*SL 0.034 0.019 0.007*SL 0.107 0.096 0.005*SL 0.083 0.073 0.005*SL 0.041 0.023 0.009*SL 0.033 0.018 0.008*SL 0.111 0.101 0.005*SL 0.087 0.077 0.005*SL 0.039 0.022 0.008*SL 0.035 0.020 0.007*SL 0.087 0.077 0.005*SL 0.070 0.060 0.005*SL 0.040 0.021 0.009*SL 0.035 0.020 0.007*SL 0.091 0.081 0.005*SL 0.074 0.064 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-59
STDH150
NR5/NR5D2/NR5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
NR5D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.024 0.005*SL 0.017 0.004*SL 0.098 0.002*SL 0.071 0.002*SL 0.024 0.005*SL 0.017 0.004*SL 0.109 0.002*SL 0.076 0.002*SL 0.023 0.005*SL 0.018 0.004*SL 0.114 0.002*SL 0.079 0.002*SL 0.022 0.005*SL 0.019 0.003*SL 0.086 0.002*SL 0.060 0.002*SL 0.022 0.005*SL 0.017 0.004*SL 0.089 0.002*SL 0.065 0.002*SL
Parameter
Delay [ns]
Group3*
0.015 0.005*SL 0.017 0.004*SL 0.101 0.002*SL 0.074 0.002*SL 0.015 0.005*SL 0.014 0.004*SL 0.113 0.002*SL 0.080 0.002*SL 0.015 0.005*SL 0.014 0.004*SL 0.117 0.002*SL 0.084 0.002*SL 0.014 0.005*SL 0.014 0.004*SL 0.089 0.002*SL 0.065 0.002*SL 0.013 0.005*SL 0.015 0.004*SL 0.093 0.002*SL 0.069 0.002*SL
0.033 0.023 0.005*SL 0.024 0.016 0.004*SL 0.101 0.095 0.003*SL 0.073 0.068 0.003*SL 0.033 0.023 0.005*SL 0.024 0.017 0.004*SL 0.112 0.106 0.003*SL 0.079 0.073 0.003*SL 0.032 0.023 0.004*SL 0.024 0.017 0.004*SL 0.117 0.111 0.003*SL 0.082 0.076 0.003*SL 0.031 0.021 0.005*SL 0.025 0.017 0.004*SL 0.089 0.083 0.003*SL 0.063 0.057 0.003*SL 0.031 0.021 0.005*SL 0.024 0.016 0.004*SL 0.092 0.086 0.003*SL 0.067 0.061 0.003*SL *Group1 *Group2 *Group3
STDH150
3-60
Samsung ASIC
NR5/NR5D2/NR5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
NR5D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.030 0.002*SL 0.024 0.002*SL 0.111 0.001*SL 0.081 0.001*SL 0.029 0.002*SL 0.023 0.002*SL 0.123 0.001*SL 0.087 0.001*SL 0.032 0.002*SL 0.023 0.002*SL 0.128 0.001*SL 0.090 0.001*SL 0.028 0.002*SL 0.023 0.002*SL 0.097 0.001*SL 0.070 0.001*SL 0.030 0.002*SL 0.024 0.002*SL 0.101 0.001*SL 0.074 0.001*SL
Parameter
Delay [ns]
Group3*
0.021 0.002*SL 0.021 0.002*SL 0.119 0.001*SL 0.090 0.001*SL 0.021 0.002*SL 0.021 0.002*SL 0.131 0.001*SL 0.095 0.001*SL 0.021 0.002*SL 0.021 0.002*SL 0.136 0.001*SL 0.099 0.001*SL 0.022 0.002*SL 0.022 0.002*SL 0.105 0.001*SL 0.079 0.001*SL 0.020 0.002*SL 0.023 0.002*SL 0.109 0.001*SL 0.084 0.001*SL
0.034 0.028 0.003*SL 0.026 0.021 0.003*SL 0.112 0.109 0.002*SL 0.082 0.078 0.002*SL 0.034 0.030 0.002*SL 0.026 0.021 0.002*SL 0.125 0.121 0.002*SL 0.088 0.084 0.002*SL 0.036 0.030 0.003*SL 0.026 0.022 0.002*SL 0.129 0.125 0.002*SL 0.091 0.087 0.002*SL 0.032 0.027 0.002*SL 0.027 0.023 0.002*SL 0.099 0.095 0.002*SL 0.071 0.068 0.002*SL 0.033 0.027 0.003*SL 0.027 0.023 0.002*SL 0.103 0.099 0.002*SL 0.075 0.072 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-61
STDH150
NR6/NR6D2/NR6D4
6-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Other States
Cell Data
4.33 Input Load (SL) NR6D2 Gate Count NR6D2 4.67 NR6D4 NR6D4 5.67
STDH150
3-62
Samsung ASIC
NR6/NR6D2/NR6D4
6-Input with 1X/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.021 0.009*SL 0.019 0.007*SL 0.086 0.004*SL 0.069 0.004*SL 0.021 0.009*SL 0.019 0.007*SL 0.097 0.004*SL 0.075 0.004*SL 0.021 0.009*SL 0.020 0.007*SL 0.102 0.004*SL 0.079 0.004*SL 0.018 0.010*SL 0.022 0.007*SL 0.090 0.004*SL 0.074 0.004*SL 0.018 0.010*SL 0.021 0.007*SL 0.101 0.004*SL 0.080 0.004*SL 0.018 0.010*SL 0.021 0.007*SL 0.105 0.004*SL 0.083 0.004*SL
Group3*
0.015 0.010*SL 0.016 0.007*SL 0.087 0.004*SL 0.072 0.004*SL 0.015 0.010*SL 0.016 0.007*SL 0.099 0.004*SL 0.077 0.004*SL 0.014 0.010*SL 0.016 0.007*SL 0.103 0.004*SL 0.081 0.004*SL 0.015 0.010*SL 0.017 0.007*SL 0.091 0.004*SL 0.077 0.004*SL 0.015 0.010*SL 0.015 0.007*SL 0.102 0.004*SL 0.083 0.004*SL 0.015 0.010*SL 0.017 0.007*SL 0.107 0.004*SL 0.086 0.004*SL
0.041 0.023 0.009*SL 0.032 0.017 0.008*SL 0.093 0.083 0.005*SL 0.076 0.066 0.005*SL 0.041 0.023 0.009*SL 0.033 0.018 0.007*SL 0.105 0.095 0.005*SL 0.082 0.072 0.005*SL 0.040 0.022 0.009*SL 0.033 0.019 0.007*SL 0.109 0.099 0.005*SL 0.085 0.075 0.005*SL 0.039 0.023 0.008*SL 0.034 0.018 0.008*SL 0.097 0.087 0.005*SL 0.081 0.071 0.005*SL 0.040 0.023 0.008*SL 0.034 0.018 0.008*SL 0.108 0.098 0.005*SL 0.086 0.076 0.005*SL 0.040 0.023 0.008*SL 0.034 0.018 0.008*SL 0.113 0.103 0.005*SL 0.090 0.080 0.005*SL *Group1 *Group2 *Group3
Samsung ASIC
3-63
STDH150
NR6/NR6D2/NR6D4
6-Input with 1X/2X/4X Drive Switching Characteristics
NR6D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.024 0.005*SL 0.017 0.004*SL 0.098 0.002*SL 0.071 0.002*SL 0.024 0.005*SL 0.017 0.004*SL 0.110 0.002*SL 0.077 0.002*SL 0.022 0.005*SL 0.018 0.004*SL 0.115 0.002*SL 0.080 0.002*SL 0.023 0.005*SL 0.018 0.004*SL 0.097 0.002*SL 0.072 0.002*SL 0.024 0.005*SL 0.018 0.004*SL 0.109 0.002*SL 0.078 0.002*SL 0.024 0.005*SL 0.019 0.004*SL 0.113 0.002*SL 0.081 0.002*SL
Group3*
0.015 0.005*SL 0.017 0.004*SL 0.102 0.002*SL 0.074 0.002*SL 0.016 0.005*SL 0.014 0.004*SL 0.114 0.002*SL 0.081 0.002*SL 0.015 0.005*SL 0.015 0.004*SL 0.118 0.002*SL 0.084 0.002*SL 0.016 0.005*SL 0.016 0.004*SL 0.101 0.002*SL 0.077 0.002*SL 0.016 0.005*SL 0.016 0.004*SL 0.113 0.002*SL 0.082 0.002*SL 0.016 0.005*SL 0.014 0.004*SL 0.117 0.002*SL 0.086 0.002*SL
0.033 0.024 0.005*SL 0.024 0.016 0.004*SL 0.101 0.095 0.003*SL 0.074 0.068 0.003*SL 0.033 0.023 0.005*SL 0.024 0.017 0.004*SL 0.113 0.107 0.003*SL 0.079 0.073 0.003*SL 0.032 0.024 0.004*SL 0.024 0.017 0.004*SL 0.118 0.111 0.003*SL 0.083 0.077 0.003*SL 0.031 0.022 0.005*SL 0.024 0.016 0.004*SL 0.100 0.094 0.003*SL 0.075 0.069 0.003*SL 0.032 0.022 0.005*SL 0.024 0.016 0.004*SL 0.112 0.106 0.003*SL 0.081 0.075 0.003*SL 0.032 0.022 0.005*SL 0.025 0.017 0.004*SL 0.116 0.110 0.003*SL 0.084 0.078 0.003*SL *Group1 *Group2 *Group3
STDH150
3-64
Samsung ASIC
NR6/NR6D2/NR6D4
6-Input with 1X/2X/4X Drive Switching Characteristics
NR6D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.032 0.002*SL 0.024 0.002*SL 0.109 0.001*SL 0.080 0.001*SL 0.030 0.002*SL 0.024 0.002*SL 0.120 0.001*SL 0.085 0.001*SL 0.032 0.002*SL 0.024 0.002*SL 0.125 0.001*SL 0.089 0.001*SL 0.031 0.002*SL 0.026 0.002*SL 0.110 0.001*SL 0.082 0.001*SL 0.031 0.002*SL 0.026 0.002*SL 0.121 0.001*SL 0.088 0.001*SL 0.029 0.002*SL 0.026 0.002*SL 0.126 0.001*SL 0.092 0.001*SL
Parameter
Delay [ns]
Group3*
0.023 0.002*SL 0.022 0.002*SL 0.117 0.001*SL 0.089 0.001*SL 0.022 0.002*SL 0.022 0.002*SL 0.128 0.001*SL 0.094 0.001*SL 0.021 0.002*SL 0.023 0.002*SL 0.133 0.001*SL 0.098 0.001*SL 0.021 0.002*SL 0.022 0.002*SL 0.118 0.001*SL 0.092 0.001*SL 0.024 0.002*SL 0.024 0.002*SL 0.130 0.001*SL 0.098 0.001*SL 0.023 0.002*SL 0.023 0.002*SL 0.135 0.001*SL 0.101 0.001*SL
0.036 0.031 0.002*SL 0.027 0.023 0.002*SL 0.110 0.106 0.002*SL 0.081 0.077 0.002*SL 0.035 0.030 0.002*SL 0.026 0.021 0.002*SL 0.121 0.118 0.002*SL 0.086 0.083 0.002*SL 0.036 0.030 0.003*SL 0.027 0.022 0.002*SL 0.126 0.122 0.002*SL 0.090 0.086 0.002*SL 0.035 0.030 0.003*SL 0.028 0.024 0.002*SL 0.112 0.108 0.002*SL 0.084 0.080 0.002*SL 0.034 0.029 0.003*SL 0.028 0.024 0.002*SL 0.123 0.119 0.002*SL 0.089 0.085 0.002*SL 0.034 0.029 0.002*SL 0.029 0.024 0.002*SL 0.128 0.124 0.002*SL 0.093 0.089 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-65
STDH150
NR8/NR8D2/NR8D4
8-Input with 1X/2X/4X Drive Logic Symbol Truth Table
Other States
Cell Data
Input Load (SL) NR8D2 NR8D4 Gate Count 5.33 NR8D2 5.67 NR8D4 6.67
STDH150
3-66
Samsung ASIC
NR8/NR8D2/NR8D4
8-Input with 1X/2X/4X Drive Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.027 0.009*SL 0.022 0.007*SL 0.101 0.004*SL 0.074 0.004*SL 0.027 0.009*SL 0.021 0.007*SL 0.112 0.004*SL 0.080 0.004*SL 0.027 0.009*SL 0.021 0.007*SL 0.117 0.004*SL 0.084 0.004*SL 0.026 0.009*SL 0.025 0.007*SL 0.104 0.004*SL 0.078 0.004*SL 0.026 0.009*SL 0.024 0.007*SL 0.116 0.004*SL 0.084 0.004*SL 0.025 0.009*SL 0.024 0.007*SL 0.120 0.005*SL 0.087 0.004*SL 0.027 0.009*SL 0.023 0.007*SL 0.094 0.004*SL 0.069 0.004*SL 0.026 0.009*SL 0.024 0.007*SL 0.098 0.004*SL 0.073 0.004*SL
Parameter
Delay [ns]
Group3*
0.020 0.010*SL 0.017 0.007*SL 0.104 0.004*SL 0.078 0.004*SL 0.020 0.010*SL 0.017 0.007*SL 0.115 0.004*SL 0.083 0.004*SL 0.020 0.010*SL 0.018 0.007*SL 0.120 0.004*SL 0.087 0.004*SL 0.020 0.010*SL 0.018 0.007*SL 0.108 0.004*SL 0.082 0.004*SL 0.021 0.010*SL 0.018 0.007*SL 0.119 0.004*SL 0.088 0.004*SL 0.021 0.010*SL 0.018 0.007*SL 0.124 0.004*SL 0.091 0.004*SL 0.020 0.010*SL 0.019 0.007*SL 0.097 0.004*SL 0.073 0.004*SL 0.019 0.010*SL 0.018 0.007*SL 0.101 0.004*SL 0.077 0.004*SL
0.046 0.029 0.009*SL 0.035 0.019 0.008*SL 0.108 0.097 0.006*SL 0.081 0.071 0.005*SL 0.046 0.028 0.009*SL 0.035 0.020 0.007*SL 0.119 0.108 0.006*SL 0.086 0.076 0.005*SL 0.045 0.027 0.009*SL 0.034 0.019 0.007*SL 0.123 0.112 0.006*SL 0.090 0.079 0.005*SL 0.046 0.029 0.009*SL 0.037 0.021 0.008*SL 0.111 0.100 0.006*SL 0.084 0.074 0.005*SL 0.046 0.029 0.009*SL 0.036 0.020 0.008*SL 0.122 0.111 0.006*SL 0.090 0.080 0.005*SL 0.046 0.029 0.008*SL 0.036 0.020 0.008*SL 0.127 0.116 0.006*SL 0.093 0.083 0.005*SL 0.045 0.026 0.010*SL 0.036 0.021 0.007*SL 0.101 0.089 0.006*SL 0.075 0.065 0.005*SL 0.044 0.024 0.010*SL 0.037 0.023 0.007*SL 0.104 0.093 0.006*SL 0.079 0.069 0.005*SL *Group3 *Group1 *Group2
Samsung ASIC
3-67
STDH150
NR8/NR8D2/NR8D4
8-Input with 1X/2X/4X Drive Switching Characteristics
NR8D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.029 0.005*SL 0.019 0.004*SL 0.109 0.002*SL 0.073 0.002*SL 0.028 0.005*SL 0.018 0.004*SL 0.120 0.002*SL 0.078 0.002*SL 0.027 0.005*SL 0.019 0.004*SL 0.125 0.002*SL 0.081 0.002*SL 0.031 0.004*SL 0.019 0.004*SL 0.116 0.002*SL 0.077 0.002*SL 0.030 0.005*SL 0.019 0.004*SL 0.128 0.002*SL 0.083 0.002*SL 0.031 0.005*SL 0.019 0.004*SL 0.132 0.002*SL 0.086 0.002*SL 0.030 0.005*SL 0.021 0.004*SL 0.104 0.002*SL 0.067 0.002*SL 0.029 0.005*SL 0.020 0.004*SL 0.108 0.002*SL 0.071 0.002*SL
Parameter
Delay [ns]
Group3*
0.022 0.005*SL 0.016 0.004*SL 0.116 0.002*SL 0.078 0.002*SL 0.022 0.005*SL 0.015 0.004*SL 0.128 0.002*SL 0.083 0.002*SL 0.022 0.005*SL 0.017 0.004*SL 0.132 0.002*SL 0.087 0.002*SL 0.022 0.005*SL 0.015 0.004*SL 0.124 0.002*SL 0.083 0.002*SL 0.022 0.005*SL 0.016 0.004*SL 0.135 0.002*SL 0.088 0.002*SL 0.023 0.005*SL 0.016 0.004*SL 0.140 0.002*SL 0.092 0.002*SL 0.021 0.005*SL 0.017 0.004*SL 0.111 0.002*SL 0.073 0.002*SL 0.021 0.005*SL 0.018 0.004*SL 0.115 0.002*SL 0.077 0.002*SL
0.038 0.028 0.005*SL 0.025 0.017 0.004*SL 0.112 0.105 0.003*SL 0.075 0.069 0.003*SL 0.037 0.028 0.005*SL 0.024 0.017 0.004*SL 0.123 0.116 0.003*SL 0.081 0.075 0.003*SL 0.037 0.029 0.004*SL 0.025 0.017 0.004*SL 0.128 0.121 0.003*SL 0.084 0.078 0.003*SL 0.039 0.028 0.005*SL 0.026 0.018 0.004*SL 0.119 0.112 0.003*SL 0.080 0.074 0.003*SL 0.038 0.028 0.005*SL 0.026 0.018 0.004*SL 0.131 0.124 0.004*SL 0.085 0.079 0.003*SL 0.038 0.028 0.005*SL 0.026 0.018 0.004*SL 0.135 0.128 0.004*SL 0.089 0.083 0.003*SL 0.038 0.027 0.005*SL 0.027 0.019 0.004*SL 0.107 0.100 0.003*SL 0.070 0.063 0.003*SL 0.037 0.027 0.005*SL 0.026 0.018 0.004*SL 0.111 0.104 0.003*SL 0.073 0.067 0.003*SL *Group3 *Group1 *Group2
STDH150
3-68
Samsung ASIC
NR8/NR8D2/NR8D4
8-Input with 1X/2X/4X Drive Switching Characteristics
NR8D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.036 0.002*SL 0.026 0.002*SL 0.126 0.001*SL 0.083 0.001*SL 0.036 0.002*SL 0.025 0.002*SL 0.137 0.001*SL 0.088 0.001*SL 0.036 0.002*SL 0.026 0.002*SL 0.141 0.001*SL 0.092 0.001*SL 0.038 0.002*SL 0.026 0.002*SL 0.133 0.001*SL 0.087 0.001*SL 0.039 0.002*SL 0.027 0.002*SL 0.144 0.001*SL 0.093 0.001*SL 0.038 0.002*SL 0.026 0.002*SL 0.149 0.001*SL 0.097 0.001*SL 0.038 0.002*SL 0.026 0.002*SL 0.118 0.001*SL 0.076 0.001*SL 0.037 0.002*SL 0.028 0.002*SL 0.122 0.001*SL 0.080 0.001*SL
Group3*
0.033 0.002*SL 0.023 0.002*SL 0.139 0.001*SL 0.093 0.001*SL 0.033 0.002*SL 0.024 0.002*SL 0.150 0.001*SL 0.098 0.001*SL 0.033 0.002*SL 0.024 0.002*SL 0.154 0.001*SL 0.102 0.001*SL 0.034 0.002*SL 0.024 0.002*SL 0.146 0.001*SL 0.098 0.001*SL 0.033 0.002*SL 0.026 0.002*SL 0.157 0.001*SL 0.104 0.001*SL 0.034 0.002*SL 0.025 0.002*SL 0.162 0.001*SL 0.107 0.001*SL 0.033 0.002*SL 0.025 0.002*SL 0.131 0.001*SL 0.087 0.001*SL 0.033 0.002*SL 0.026 0.002*SL 0.135 0.001*SL 0.091 0.001*SL
0.041 0.037 0.002*SL 0.029 0.024 0.002*SL 0.127 0.123 0.002*SL 0.084 0.080 0.002*SL 0.041 0.037 0.002*SL 0.027 0.023 0.002*SL 0.138 0.134 0.002*SL 0.089 0.086 0.002*SL 0.041 0.037 0.002*SL 0.028 0.023 0.002*SL 0.143 0.139 0.002*SL 0.093 0.089 0.002*SL 0.043 0.038 0.002*SL 0.028 0.023 0.002*SL 0.134 0.130 0.002*SL 0.088 0.084 0.002*SL 0.044 0.039 0.002*SL 0.029 0.024 0.002*SL 0.145 0.141 0.002*SL 0.094 0.090 0.002*SL 0.041 0.036 0.003*SL 0.029 0.024 0.002*SL 0.150 0.146 0.002*SL 0.098 0.094 0.002*SL 0.042 0.037 0.002*SL 0.029 0.025 0.002*SL 0.119 0.115 0.002*SL 0.077 0.073 0.002*SL 0.040 0.035 0.003*SL 0.031 0.026 0.002*SL 0.123 0.119 0.002*SL 0.081 0.077 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-69
STDH150
OR2/OR2D2/OR2D4/OR2D8
2-Input with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) OR2D2 OR2D4 OR2D8 1.67 Gate Count OR2D2 OR2D4 OR2D8 2.00 3.67 5.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.017 0.009*SL 0.021 0.007*SL 0.039 0.004*SL 0.054 0.004*SL 0.018 0.010*SL 0.021 0.007*SL 0.044 0.004*SL 0.058 0.004*SL
Parameter
Delay [ns]
Group3*
0.010 0.010*SL 0.017 0.007*SL 0.039 0.004*SL 0.058 0.004*SL 0.012 0.010*SL 0.019 0.007*SL 0.045 0.004*SL 0.062 0.004*SL
0.037 0.018 0.009*SL 0.036 0.022 0.007*SL 0.047 0.038 0.005*SL 0.060 0.050 0.005*SL 0.037 0.017 0.010*SL 0.035 0.020 0.008*SL 0.052 0.043 0.005*SL 0.065 0.054 0.005*SL *Group1 *Group2 *Group3
OR2D2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.019 0.005*SL 0.026 0.003*SL 0.046 0.002*SL 0.063 0.002*SL 0.019 0.005*SL 0.027 0.004*SL 0.050 0.002*SL 0.067 0.002*SL
Group3*
0.011 0.005*SL 0.023 0.004*SL 0.047 0.002*SL 0.071 0.002*SL 0.013 0.005*SL 0.025 0.004*SL 0.051 0.002*SL 0.075 0.002*SL
0.028 0.019 0.005*SL 0.032 0.024 0.004*SL 0.049 0.044 0.003*SL 0.065 0.058 0.003*SL 0.031 0.024 0.003*SL 0.033 0.025 0.004*SL 0.053 0.048 0.003*SL 0.069 0.062 0.003*SL *Group1 *Group2 *Group3
STDH150
3-70
Samsung ASIC
OR2/OR2D2/OR2D4/OR2D8
2-Input with 1X/2X/4X/8X Drive Switching Characteristics
OR2D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.024 0.002*SL 0.025 0.002*SL 0.044 0.001*SL 0.059 0.001*SL 0.026 0.002*SL 0.026 0.002*SL 0.048 0.001*SL 0.063 0.001*SL
Parameter
Delay [ns]
Group3*
0.012 0.002*SL 0.024 0.002*SL 0.045 0.001*SL 0.069 0.001*SL 0.014 0.002*SL 0.024 0.002*SL 0.051 0.001*SL 0.073 0.001*SL
0.025 0.017 0.004*SL 0.027 0.021 0.003*SL 0.045 0.042 0.002*SL 0.060 0.057 0.002*SL 0.026 0.017 0.005*SL 0.029 0.024 0.002*SL 0.049 0.046 0.002*SL 0.064 0.060 0.002*SL *Group1 *Group2 *Group3
OR2D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.027 0.001*SL 0.036 0.001*SL 0.060 0.001*SL 0.078 0.001*SL 0.030 0.001*SL 0.037 0.001*SL 0.064 0.001*SL 0.083 0.001*SL
Group3*
0.019 0.001*SL 0.039 0.001*SL 0.066 0.001*SL 0.095 0.000*SL 0.020 0.001*SL 0.037 0.001*SL 0.071 0.001*SL 0.099 0.000*SL
0.029 0.027 0.001*SL 0.038 0.036 0.001*SL 0.060 0.058 0.001*SL 0.079 0.077 0.001*SL 0.031 0.027 0.002*SL 0.039 0.037 0.001*SL 0.065 0.063 0.001*SL 0.084 0.081 0.001*SL *Group1 *Group2 *Group3
Samsung ASIC
3-71
STDH150
OR2B/OR2BD2/OR2BD4/OR2BD8
2-Input with Inverted Input, 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
OR2B Input Load (SL) OR2BD2 OR2BD4 OR2BD8 OR2B 2.33 Gate Count OR2BD2 OR2BD4 OR2BD8 2.67 4.00 5.67
Switching Characteristics
OR2B
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.017 0.009*SL 0.023 0.007*SL 0.072 0.004*SL 0.066 0.004*SL 0.018 0.010*SL 0.022 0.007*SL 0.044 0.004*SL 0.059 0.004*SL
Parameter
Delay [ns]
Group3*
0.010 0.010*SL 0.018 0.007*SL 0.072 0.004*SL 0.070 0.004*SL 0.012 0.010*SL 0.018 0.007*SL 0.045 0.004*SL 0.063 0.004*SL
0.037 0.018 0.009*SL 0.036 0.020 0.008*SL 0.079 0.070 0.005*SL 0.072 0.062 0.005*SL 0.037 0.019 0.009*SL 0.036 0.023 0.007*SL 0.052 0.043 0.005*SL 0.065 0.054 0.005*SL *Group1 *Group2 *Group3
OR2BD2
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.017 0.005*SL 0.027 0.003*SL 0.072 0.002*SL 0.078 0.002*SL 0.015 0.005*SL 0.028 0.004*SL 0.041 0.002*SL 0.070 0.002*SL
Group3*
0.010 0.005*SL 0.023 0.004*SL 0.074 0.002*SL 0.088 0.002*SL 0.011 0.005*SL 0.027 0.004*SL 0.042 0.002*SL 0.080 0.002*SL
0.027 0.017 0.005*SL 0.033 0.025 0.004*SL 0.076 0.071 0.003*SL 0.081 0.074 0.003*SL 0.026 0.018 0.004*SL 0.033 0.024 0.005*SL 0.045 0.039 0.003*SL 0.073 0.066 0.003*SL *Group1 *Group2 *Group3
STDH150
3-72
Samsung ASIC
OR2B/OR2BD2/OR2BD4/OR2BD8
2-Input with Inverted Input, 1X/2X/4X/8X Drive Switching Characteristics
OR2BD4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.019 0.002*SL 0.025 0.002*SL 0.076 0.001*SL 0.077 0.001*SL 0.027 0.002*SL 0.026 0.002*SL 0.048 0.001*SL 0.064 0.001*SL
Parameter
Delay [ns]
Group3*
0.012 0.002*SL 0.025 0.002*SL 0.078 0.001*SL 0.087 0.001*SL 0.013 0.002*SL 0.024 0.002*SL 0.050 0.001*SL 0.074 0.001*SL
0.024 0.020 0.002*SL 0.028 0.023 0.002*SL 0.077 0.074 0.002*SL 0.078 0.074 0.002*SL 0.027 0.017 0.005*SL 0.029 0.025 0.002*SL 0.049 0.046 0.002*SL 0.065 0.061 0.002*SL *Group1 *Group2 *Group3
OR2BD8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.028 0.001*SL 0.039 0.001*SL 0.091 0.001*SL 0.096 0.001*SL 0.030 0.001*SL 0.038 0.001*SL 0.064 0.001*SL 0.084 0.001*SL
Group3*
0.020 0.001*SL 0.039 0.001*SL 0.098 0.001*SL 0.112 0.000*SL 0.020 0.001*SL 0.038 0.001*SL 0.071 0.001*SL 0.101 0.000*SL
0.029 0.026 0.002*SL 0.041 0.040 0.001*SL 0.092 0.090 0.001*SL 0.096 0.094 0.001*SL 0.031 0.027 0.002*SL 0.039 0.036 0.001*SL 0.065 0.063 0.001*SL 0.085 0.082 0.001*SL *Group1 *Group2 *Group3
Samsung ASIC
3-73
STDH150
OR3/OR3D2/OR3D4
3-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) OR3D2 OR3D4 2.00 Gate Count OR3D2 OR3D4 2.67 4.67
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.014 0.010*SL 0.030 0.007*SL 0.044 0.004*SL 0.068 0.005*SL 0.018 0.010*SL 0.033 0.007*SL 0.050 0.004*SL 0.080 0.004*SL 0.017 0.010*SL 0.033 0.007*SL 0.053 0.004*SL 0.084 0.004*SL
Group3*
0.012 0.010*SL 0.029 0.007*SL 0.044 0.004*SL 0.077 0.004*SL 0.012 0.010*SL 0.030 0.007*SL 0.050 0.004*SL 0.089 0.004*SL 0.015 0.010*SL 0.030 0.007*SL 0.054 0.004*SL 0.093 0.004*SL
0.036 0.019 0.008*SL 0.043 0.026 0.008*SL 0.052 0.042 0.005*SL 0.074 0.062 0.006*SL 0.039 0.022 0.008*SL 0.043 0.026 0.009*SL 0.057 0.048 0.005*SL 0.086 0.073 0.006*SL 0.038 0.021 0.009*SL 0.043 0.025 0.009*SL 0.060 0.050 0.005*SL 0.090 0.078 0.006*SL *Group1 *Group2 *Group3
STDH150
3-74
Samsung ASIC
OR3/OR3D2/OR3D4
3-Input with 1X/2X/4X Drive Switching Characteristics
OR3D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.028 0.004*SL 0.037 0.004*SL 0.051 0.002*SL 0.080 0.003*SL 0.020 0.005*SL 0.037 0.004*SL 0.056 0.002*SL 0.092 0.003*SL 0.033 0.004*SL 0.039 0.004*SL 0.058 0.002*SL 0.097 0.003*SL
Group3*
0.013 0.005*SL 0.039 0.004*SL 0.053 0.002*SL 0.095 0.002*SL 0.014 0.005*SL 0.039 0.004*SL 0.058 0.002*SL 0.107 0.002*SL 0.017 0.005*SL 0.040 0.004*SL 0.062 0.002*SL 0.112 0.002*SL
0.032 0.020 0.006*SL 0.042 0.033 0.005*SL 0.054 0.049 0.003*SL 0.083 0.075 0.004*SL 0.031 0.023 0.004*SL 0.044 0.036 0.004*SL 0.059 0.053 0.003*SL 0.095 0.087 0.004*SL 0.037 0.024 0.006*SL 0.044 0.034 0.005*SL 0.061 0.056 0.003*SL 0.099 0.091 0.004*SL *Group1 *Group2 *Group3
OR3D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.021 0.002*SL 0.034 0.002*SL 0.048 0.001*SL 0.075 0.001*SL 0.022 0.002*SL 0.036 0.002*SL 0.053 0.001*SL 0.087 0.001*SL 0.028 0.002*SL 0.034 0.002*SL 0.055 0.001*SL 0.091 0.001*SL
Group3*
0.011 0.002*SL 0.039 0.002*SL 0.051 0.001*SL 0.091 0.001*SL 0.013 0.002*SL 0.036 0.002*SL 0.057 0.001*SL 0.103 0.001*SL 0.015 0.002*SL 0.038 0.002*SL 0.060 0.001*SL 0.108 0.001*SL
0.027 0.023 0.002*SL 0.037 0.033 0.002*SL 0.050 0.047 0.002*SL 0.076 0.072 0.002*SL 0.026 0.020 0.003*SL 0.038 0.033 0.003*SL 0.055 0.051 0.002*SL 0.088 0.083 0.002*SL 0.032 0.026 0.003*SL 0.037 0.032 0.002*SL 0.057 0.054 0.002*SL 0.092 0.088 0.002*SL *Group1 *Group2 *Group3
Samsung ASIC
3-75
STDH150
OR4/OR4D2/OR4D4
4-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
3.00 Input Load (SL) OR4D2 Gate Count OR4D2 3.33 OR4D4 OR4D4 6.67
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.022 0.010*SL 0.031 0.009*SL 0.038 0.004*SL 0.063 0.005*SL 0.023 0.010*SL 0.030 0.009*SL 0.042 0.005*SL 0.067 0.005*SL 0.027 0.010*SL 0.028 0.009*SL 0.040 0.005*SL 0.064 0.005*SL 0.026 0.010*SL 0.028 0.009*SL 0.043 0.005*SL 0.068 0.005*SL
Parameter
Delay [ns]
Group3*
0.018 0.010*SL 0.027 0.009*SL 0.039 0.004*SL 0.066 0.005*SL 0.019 0.010*SL 0.026 0.009*SL 0.042 0.004*SL 0.070 0.004*SL 0.022 0.010*SL 0.025 0.009*SL 0.040 0.004*SL 0.067 0.005*SL 0.023 0.010*SL 0.024 0.009*SL 0.044 0.004*SL 0.071 0.005*SL
0.044 0.024 0.010*SL 0.047 0.028 0.009*SL 0.047 0.037 0.005*SL 0.071 0.059 0.006*SL 0.044 0.024 0.010*SL 0.047 0.029 0.009*SL 0.050 0.041 0.005*SL 0.074 0.063 0.006*SL 0.048 0.029 0.010*SL 0.045 0.026 0.009*SL 0.048 0.039 0.005*SL 0.072 0.061 0.005*SL 0.048 0.030 0.009*SL 0.045 0.027 0.009*SL 0.052 0.043 0.005*SL 0.076 0.065 0.005*SL *Group1 *Group2 *Group3
STDH150
3-76
Samsung ASIC
OR4/OR4D2/OR4D4
4-Input with 1X/2X/4X Drive Switching Characteristics
OR4D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.024 0.005*SL 0.032 0.004*SL 0.043 0.002*SL 0.070 0.003*SL 0.021 0.005*SL 0.035 0.004*SL 0.046 0.002*SL 0.074 0.003*SL 0.026 0.005*SL 0.031 0.004*SL 0.046 0.002*SL 0.075 0.003*SL 0.028 0.005*SL 0.031 0.004*SL 0.049 0.002*SL 0.079 0.003*SL
Parameter
Delay [ns]
Group3*
0.016 0.005*SL 0.030 0.004*SL 0.043 0.002*SL 0.077 0.002*SL 0.017 0.005*SL 0.030 0.004*SL 0.047 0.002*SL 0.081 0.002*SL 0.022 0.005*SL 0.028 0.004*SL 0.047 0.002*SL 0.082 0.002*SL 0.021 0.005*SL 0.030 0.004*SL 0.050 0.002*SL 0.087 0.002*SL
0.034 0.024 0.005*SL 0.041 0.032 0.004*SL 0.047 0.041 0.003*SL 0.074 0.067 0.003*SL 0.033 0.025 0.004*SL 0.043 0.033 0.005*SL 0.050 0.045 0.003*SL 0.078 0.071 0.003*SL 0.037 0.029 0.004*SL 0.038 0.028 0.005*SL 0.050 0.045 0.003*SL 0.079 0.072 0.003*SL 0.037 0.026 0.005*SL 0.038 0.027 0.005*SL 0.053 0.048 0.002*SL 0.082 0.076 0.003*SL *Group1 *Group2 *Group3
OR4D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.022 0.002*SL 0.031 0.002*SL 0.041 0.001*SL 0.067 0.001*SL 0.024 0.002*SL 0.033 0.002*SL 0.044 0.001*SL 0.071 0.001*SL 0.026 0.002*SL 0.027 0.002*SL 0.044 0.001*SL 0.071 0.001*SL 0.026 0.002*SL 0.029 0.002*SL 0.047 0.001*SL 0.075 0.001*SL
Group3*
0.016 0.003*SL 0.030 0.002*SL 0.043 0.001*SL 0.076 0.001*SL 0.016 0.003*SL 0.031 0.002*SL 0.046 0.001*SL 0.080 0.001*SL 0.020 0.003*SL 0.028 0.002*SL 0.045 0.001*SL 0.081 0.001*SL 0.021 0.003*SL 0.028 0.002*SL 0.049 0.001*SL 0.085 0.001*SL
0.027 0.022 0.002*SL 0.035 0.030 0.002*SL 0.043 0.040 0.001*SL 0.069 0.065 0.002*SL 0.028 0.023 0.003*SL 0.037 0.032 0.002*SL 0.046 0.044 0.001*SL 0.072 0.069 0.002*SL 0.032 0.028 0.002*SL 0.031 0.026 0.002*SL 0.046 0.043 0.001*SL 0.073 0.069 0.002*SL 0.031 0.026 0.002*SL 0.032 0.027 0.003*SL 0.049 0.047 0.001*SL 0.077 0.073 0.002*SL *Group3 *Group1 *Group2
Samsung ASIC
3-77
STDH150
OR5/OR5D2/OR5D4
5-Input with 1X/2X/4X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) OR5D2 OR5D4 3.33 Gate Count OR5D2 OR5D4 3.67 7.33
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.022 0.010*SL 0.036 0.009*SL 0.048 0.005*SL 0.071 0.005*SL 0.022 0.010*SL 0.035 0.009*SL 0.053 0.005*SL 0.083 0.005*SL 0.024 0.010*SL 0.035 0.009*SL 0.056 0.005*SL 0.087 0.005*SL 0.022 0.010*SL 0.026 0.009*SL 0.038 0.005*SL 0.062 0.005*SL 0.025 0.010*SL 0.026 0.009*SL 0.042 0.005*SL 0.066 0.005*SL
Parameter
Delay [ns]
Group3*
0.016 0.010*SL 0.032 0.009*SL 0.048 0.004*SL 0.078 0.005*SL 0.017 0.010*SL 0.031 0.009*SL 0.054 0.004*SL 0.090 0.005*SL 0.019 0.010*SL 0.031 0.009*SL 0.058 0.004*SL 0.094 0.005*SL 0.020 0.010*SL 0.023 0.009*SL 0.038 0.004*SL 0.065 0.005*SL 0.020 0.010*SL 0.023 0.009*SL 0.043 0.004*SL 0.069 0.005*SL
0.042 0.023 0.010*SL 0.051 0.032 0.010*SL 0.056 0.046 0.005*SL 0.079 0.066 0.006*SL 0.043 0.025 0.009*SL 0.051 0.032 0.009*SL 0.062 0.052 0.005*SL 0.090 0.077 0.006*SL 0.045 0.026 0.009*SL 0.051 0.032 0.009*SL 0.065 0.054 0.005*SL 0.094 0.082 0.006*SL 0.044 0.025 0.009*SL 0.042 0.024 0.009*SL 0.047 0.037 0.005*SL 0.070 0.059 0.006*SL 0.045 0.025 0.010*SL 0.042 0.024 0.009*SL 0.051 0.041 0.005*SL 0.074 0.062 0.006*SL *Group1 *Group2 *Group3
STDH150
3-78
Samsung ASIC
OR5/OR5D2/OR5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
OR5D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.026 0.005*SL 0.045 0.004*SL 0.056 0.002*SL 0.086 0.003*SL 0.026 0.005*SL 0.044 0.004*SL 0.061 0.002*SL 0.097 0.003*SL 0.029 0.005*SL 0.047 0.004*SL 0.064 0.002*SL 0.102 0.003*SL 0.025 0.005*SL 0.031 0.004*SL 0.046 0.002*SL 0.075 0.003*SL 0.026 0.005*SL 0.029 0.005*SL 0.049 0.002*SL 0.079 0.003*SL
Parameter
Delay [ns]
Group3*
0.020 0.005*SL 0.043 0.004*SL 0.058 0.002*SL 0.098 0.002*SL 0.020 0.005*SL 0.042 0.004*SL 0.063 0.002*SL 0.110 0.002*SL 0.022 0.005*SL 0.042 0.004*SL 0.067 0.002*SL 0.114 0.002*SL 0.022 0.005*SL 0.030 0.004*SL 0.046 0.002*SL 0.083 0.002*SL 0.021 0.005*SL 0.031 0.004*SL 0.049 0.002*SL 0.087 0.002*SL
0.039 0.032 0.003*SL 0.052 0.041 0.005*SL 0.060 0.054 0.003*SL 0.089 0.082 0.004*SL 0.038 0.029 0.004*SL 0.052 0.043 0.005*SL 0.065 0.059 0.003*SL 0.101 0.093 0.004*SL 0.042 0.036 0.003*SL 0.053 0.041 0.006*SL 0.067 0.061 0.003*SL 0.105 0.098 0.004*SL 0.036 0.026 0.005*SL 0.038 0.028 0.005*SL 0.050 0.045 0.003*SL 0.078 0.072 0.003*SL 0.036 0.027 0.005*SL 0.037 0.028 0.005*SL 0.053 0.048 0.002*SL 0.082 0.075 0.003*SL *Group1 *Group2 *Group3
Samsung ASIC
3-79
STDH150
OR5/OR5D2/OR5D4
5-Input with 1X/2X/4X Drive Switching Characteristics
OR5D4
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.031 0.002*SL 0.042 0.002*SL 0.054 0.001*SL 0.081 0.001*SL 0.028 0.002*SL 0.042 0.002*SL 0.060 0.001*SL 0.093 0.001*SL 0.036 0.002*SL 0.043 0.002*SL 0.061 0.001*SL 0.098 0.001*SL 0.026 0.002*SL 0.027 0.002*SL 0.044 0.001*SL 0.071 0.001*SL 0.026 0.002*SL 0.028 0.002*SL 0.047 0.001*SL 0.075 0.001*SL
Parameter
Delay [ns]
Group3*
0.020 0.003*SL 0.041 0.002*SL 0.056 0.001*SL 0.094 0.001*SL 0.020 0.003*SL 0.041 0.002*SL 0.063 0.001*SL 0.107 0.001*SL 0.022 0.003*SL 0.041 0.002*SL 0.066 0.001*SL 0.111 0.001*SL 0.021 0.003*SL 0.029 0.002*SL 0.045 0.001*SL 0.080 0.001*SL 0.021 0.003*SL 0.031 0.002*SL 0.048 0.001*SL 0.084 0.001*SL
0.035 0.030 0.003*SL 0.045 0.040 0.003*SL 0.056 0.053 0.001*SL 0.082 0.078 0.002*SL 0.031 0.024 0.003*SL 0.046 0.042 0.002*SL 0.061 0.058 0.002*SL 0.095 0.091 0.002*SL 0.039 0.032 0.003*SL 0.046 0.040 0.003*SL 0.063 0.060 0.001*SL 0.099 0.095 0.002*SL 0.031 0.026 0.003*SL 0.032 0.028 0.002*SL 0.046 0.043 0.001*SL 0.073 0.069 0.002*SL 0.031 0.026 0.002*SL 0.033 0.029 0.002*SL 0.049 0.047 0.001*SL 0.077 0.073 0.002*SL *Group1 *Group2 *Group3
STDH150
3-80
Samsung ASIC
XN2/XN2D2/XN2D4/XN2D8
2-Input Exclusive-NOR with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) 2.67 XN2D2 3.33 XN2D2 Gate Count XN2D4 4.00 XN2D4 XN2D8 7.33 XN2D8
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.024 0.009*SL 0.033 0.007*SL 0.075 0.004*SL 0.079 0.004*SL 0.025 0.009*SL 0.035 0.007*SL 0.075 0.004*SL 0.071 0.005*SL
Group3*
0.019 0.010*SL 0.032 0.007*SL 0.077 0.004*SL 0.086 0.004*SL 0.017 0.010*SL 0.032 0.007*SL 0.076 0.004*SL 0.080 0.004*SL
0.045 0.028 0.008*SL 0.047 0.032 0.007*SL 0.083 0.072 0.005*SL 0.086 0.075 0.005*SL 0.044 0.026 0.009*SL 0.046 0.029 0.008*SL 0.082 0.072 0.005*SL 0.076 0.064 0.006*SL *Group1 *Group2 *Group3
Samsung ASIC
3-81
STDH150
XN2/XN2D2/XN2D4/XN2D8
2-Input Exclusive-NOR with 1X/2X/4X/8X Drive Switching Characteristics
XN2D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.033 0.004*SL 0.043 0.004*SL 0.082 0.002*SL 0.087 0.003*SL 0.032 0.005*SL 0.042 0.004*SL 0.082 0.002*SL 0.079 0.003*SL
Group3*
0.023 0.005*SL 0.042 0.004*SL 0.087 0.002*SL 0.101 0.002*SL 0.024 0.005*SL 0.044 0.004*SL 0.087 0.002*SL 0.095 0.002*SL
0.041 0.031 0.005*SL 0.047 0.036 0.005*SL 0.085 0.079 0.003*SL 0.090 0.083 0.003*SL 0.039 0.028 0.005*SL 0.047 0.037 0.005*SL 0.085 0.079 0.003*SL 0.081 0.073 0.004*SL *Group1 *Group2 *Group3
XN2D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.044 0.002*SL 0.060 0.002*SL 0.097 0.001*SL 0.107 0.002*SL 0.045 0.002*SL 0.060 0.002*SL 0.097 0.001*SL 0.100 0.002*SL
Group3*
0.039 0.002*SL 0.069 0.002*SL 0.107 0.001*SL 0.132 0.001*SL 0.040 0.002*SL 0.070 0.002*SL 0.107 0.001*SL 0.125 0.001*SL
0.049 0.044 0.002*SL 0.065 0.062 0.001*SL 0.099 0.095 0.002*SL 0.108 0.104 0.002*SL 0.049 0.044 0.003*SL 0.064 0.060 0.002*SL 0.098 0.094 0.002*SL 0.101 0.096 0.003*SL *Group1 *Group2 *Group3
XN2D8
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.051 0.001*SL 0.069 0.001*SL 0.103 0.001*SL 0.113 0.001*SL 0.051 0.001*SL 0.069 0.001*SL 0.112 0.001*SL 0.112 0.001*SL
Group3*
0.046 0.001*SL 0.078 0.001*SL 0.116 0.001*SL 0.141 0.001*SL 0.047 0.001*SL 0.079 0.001*SL 0.126 0.001*SL 0.141 0.001*SL
0.054 0.053 0.001*SL 0.071 0.069 0.001*SL 0.103 0.101 0.001*SL 0.114 0.111 0.001*SL 0.054 0.052 0.001*SL 0.071 0.068 0.001*SL 0.112 0.110 0.001*SL 0.113 0.110 0.001*SL *Group1 *Group2 *Group3
STDH150
3-82
Samsung ASIC
XN3/XN3D2/XN3D4
3-Input Exclusive-NOR with 1X/2X/4X Drive Logic Symbol Truth Table
Cell Data
Input Load (SL) XN3D2 XN3D4 4.67 Gate Count XN3D2 XN3D4 5.00 5.67
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.036 0.009*SL 0.047 0.008*SL 0.080 0.005*SL 0.080 0.006*SL 0.042 0.009*SL 0.052 0.007*SL 0.124 0.005*SL 0.137 0.005*SL 0.040 0.009*SL 0.065 0.007*SL 0.124 0.005*SL 0.125 0.006*SL
Parameter
Delay [ns]
Group3*
0.032 0.010*SL 0.057 0.007*SL 0.088 0.004*SL 0.098 0.004*SL 0.034 0.010*SL 0.052 0.007*SL 0.131 0.004*SL 0.153 0.004*SL 0.034 0.010*SL 0.070 0.007*SL 0.131 0.004*SL 0.146 0.004*SL
0.052 0.032 0.010*SL 0.058 0.039 0.010*SL 0.086 0.073 0.007*SL 0.086 0.071 0.008*SL 0.057 0.037 0.010*SL 0.065 0.050 0.008*SL 0.130 0.118 0.006*SL 0.143 0.128 0.008*SL 0.058 0.039 0.009*SL 0.076 0.059 0.009*SL 0.130 0.118 0.006*SL 0.131 0.114 0.009*SL *Group1 *Group2 *Group3
Samsung ASIC
3-83
STDH150
XN3/XN3D2/XN3D4
3-Input Exclusive-NOR with 1X/2X/4X Drive Switching Characteristics
XN3D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Delay Equations [ns] Group1* Group2*
0.044 0.005*SL 0.063 0.004*SL 0.090 0.003*SL 0.096 0.003*SL 0.045 0.004*SL 0.063 0.004*SL 0.134 0.003*SL 0.150 0.003*SL 0.043 0.005*SL 0.076 0.004*SL 0.134 0.003*SL 0.140 0.003*SL
Parameter
Delay [ns]
Group3*
0.042 0.005*SL 0.078 0.004*SL 0.105 0.002*SL 0.123 0.002*SL 0.038 0.005*SL 0.065 0.004*SL 0.148 0.002*SL 0.173 0.002*SL 0.039 0.005*SL 0.087 0.003*SL 0.148 0.002*SL 0.168 0.002*SL
0.052 0.042 0.005*SL 0.069 0.059 0.005*SL 0.093 0.085 0.004*SL 0.099 0.088 0.005*SL 0.052 0.040 0.006*SL 0.068 0.058 0.005*SL 0.137 0.130 0.004*SL 0.153 0.143 0.005*SL 0.053 0.045 0.004*SL 0.083 0.075 0.004*SL 0.137 0.129 0.004*SL 0.143 0.132 0.005*SL *Group1 *Group2 *Group3
XN3D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.065 0.002*SL 0.105 0.002*SL 0.118 0.002*SL 0.139 0.002*SL 0.059 0.002*SL 0.111 0.002*SL 0.160 0.002*SL 0.185 0.002*SL 0.058 0.002*SL 0.111 0.002*SL 0.160 0.002*SL 0.180 0.002*SL
Group3*
0.064 0.002*SL 0.118 0.002*SL 0.140 0.001*SL 0.173 0.001*SL 0.059 0.002*SL 0.122 0.002*SL 0.180 0.001*SL 0.219 0.001*SL 0.058 0.002*SL 0.122 0.002*SL 0.180 0.001*SL 0.214 0.001*SL
0.068 0.062 0.003*SL 0.109 0.105 0.002*SL 0.120 0.115 0.002*SL 0.141 0.134 0.003*SL 0.064 0.060 0.002*SL 0.115 0.111 0.002*SL 0.162 0.157 0.002*SL 0.187 0.181 0.003*SL 0.065 0.061 0.002*SL 0.114 0.109 0.003*SL 0.162 0.157 0.002*SL 0.182 0.176 0.003*SL *Group1 *Group2 *Group3
STDH150
3-84
Samsung ASIC
XO2/XO2D2/XO2D4/XO2D8
2-Input Exclusive-OR with 1X/2X/4X/8X Drive Logic Symbol
Truth Table
Cell Data
Input Load (SL) 3.00 XO2D2 3.67 XO2D2 Gate Count XO2D4 4.33 XO2D4 XO2D8 7.67 XO2D8
Switching Characteristics
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.027 0.009*SL 0.037 0.007*SL 0.077 0.004*SL 0.083 0.004*SL 0.027 0.009*SL 0.034 0.007*SL 0.080 0.004*SL 0.073 0.005*SL
Group3*
0.018 0.010*SL 0.033 0.007*SL 0.079 0.004*SL 0.088 0.004*SL 0.019 0.010*SL 0.032 0.007*SL 0.083 0.004*SL 0.083 0.004*SL
0.046 0.028 0.009*SL 0.048 0.031 0.008*SL 0.084 0.074 0.005*SL 0.090 0.079 0.005*SL 0.048 0.032 0.008*SL 0.045 0.028 0.008*SL 0.087 0.075 0.006*SL 0.079 0.066 0.006*SL *Group1 *Group2 *Group3
Samsung ASIC
3-85
STDH150
XO2/XO2D2/XO2D4/XO2D8
2-Input Exclusive-OR with 1X/2X/4X/8X Drive Switching Characteristics
XO2D2
Path
(Typical process, 25°C, 1.2V, tR/tF 0.07ns, Standard Load)
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.033 0.004*SL 0.042 0.004*SL 0.084 0.002*SL 0.091 0.002*SL 0.032 0.005*SL 0.040 0.004*SL 0.087 0.002*SL 0.083 0.003*SL
Group3*
0.024 0.005*SL 0.045 0.004*SL 0.088 0.002*SL 0.103 0.002*SL 0.026 0.005*SL 0.044 0.004*SL 0.095 0.002*SL 0.100 0.002*SL
0.041 0.030 0.005*SL 0.047 0.038 0.005*SL 0.087 0.080 0.003*SL 0.094 0.087 0.004*SL 0.040 0.029 0.005*SL 0.046 0.036 0.005*SL 0.090 0.083 0.004*SL 0.086 0.077 0.004*SL *Group1 *Group2 *Group3
XO2D4
Path
Parameter
Delay [ns]
Delay Equations [ns] Group1* Group2*
0.046 0.002*SL 0.060 0.002*SL 0.098 0.001*SL 0.109 0.002*SL 0.047 0.002*SL 0.059 0.002*SL 0.104 0.001*SL 0.106 0.002*SL
Group3*
0.039 0.002*SL 0.069 0.002*SL 0.111 0.00
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