Library Description Features Support Product Family. 1.4.1 Analog Core

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Library Description Features Support Product Family. 1.4.1 Analog Core

Datasheet Thumbnail

Top Searches for this datasheet

Library Description Features Support Product Family. 1.4.1 Analog Core Cells. 1.4.2 Standard Logic Cells 1.4.3 Compiled Memory 1.4.4 Input/Output Cells 1-11 Timings. 1-13 Design Test (DFT) Methodology 1-22 Maximum Fanouts. 1-25 Package Capability Pitch Lead Count 1-31 Crystal Oscillator Considerations 1-32
Library Description
Library Description
STD150 Samsung's next generation Standard Cell library containing standard cells implemented Samsung's 0.13µm, process technology. Samsung's process uses metal interconnect layers. STD150 library contains diverse application specific digital analog System-on-Chip (SoC) applications. Samsung provides full range cells within STD150 library address challenges designing producing ultra power well high density devices that take advantage integration. With reduced power dissipation high density, STD150 help reduce system cost high performance applications such HDD, Networking, Displays. STD150 library supports gate counts million gates with usability. Gate delay faster than that STD130, 0.18µm library. Logic compiled memory density twice denser than those STD130, respectively. STD150 supports also fully user configurable memories suitable high-density low-power applications. much higher yield designs, contains repairable memory with redundant elements high-capacity memory. STD150 library also supports wide range interface voltages standards. cells that drive 2.5V, 3.3V available tolerant I/Os. Available standards include LVTTL, LVCMOS, PCI, PCI-X, OSC, AGP, PECL, HSTL, SSTL2, GTLp, LVDS. better support design, robust collection digital analog cores available. Digital cores include ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, ARM946E-S, ARM926E-JS from Ltd., well Teak TeakLite cores from Group. Analog cores include ADCs, DACs, CODECs, PLLs with various configurations frequency ranges. thick oxide process option allows high resolution operation analog cores with 3.3V power supply. addition, STD150 library supports communication data transmission cores such IEEE1284, IEEE1394 link controller, UART, controller, PCMCIA controller 10/100 ethernet MAC. Samsung's design methodology offers comprehensive timing driven design flow including automated time budgeting, tight floor plan synthesis integration, powerful timing analysis, timing driven layout. advanced characterization flow provides accurate timing data robust delay models L13, 0.13µm very deep sub-micron process technology. Static verification methods, such static timing analysis formal equivalence checking, provide effective verification methodology with variety simulators. Samsung's Design-for-Test (DFT) methodology supports full partial scan chain design, BIST, JTAG boundary scan, Built-in-Redundancy-Analysis (BIRA) reparable SRAM. Samsung provides full test ready cores with efficient core test integration methodology.
Samsung ASIC
STD150
Features
Features
Robust 1.2V standard cell library including processor, DSP, analog cores. 0.13µm CMOS process technology with optional metal layers. High gate count design million gates with utilization metal layer. Typical input NAND gate delay 52ps with fanout Characterized industrial (-40°C 85°C) commercial (0°C 70°C) temperature ranges. Robust Digital Cores Hard macro cells ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, ARM946E-S, ARM926E-JS, Teak, TeakLite. embedded trace macro cells ETM7 ETM9 Soft macro cells USB1.1, IrDA, 16C450 16C550 UART, Fast Ether MAC, P1394a LINK, IEEE1284, controller, PCMCIA controller. Ultra Voltage (1.2V) High Resolution (3.3V) Analog Cores Analog core supply voltages -1.2V, 2.5V, 3.3V. ADC: (250KHz, 1.2V 125MHz, 3.3V), (30MHz, 1.2V), (250KHz-10MHz, 3.3V) DAC: (80MHz, 1.2V), (2MHz 300MHz, 3.3V) CODEC: Sigma-Delta (8KHz 11KHz, 2.5V) PLL: 1.2V FSPLL (25MHz 300MHz 100MHz 500MHz), SSCG (1.2V, 200MHz) Fully User Configurable SRAMs ROMs Suitable high density power memory applications Single port (1RW, 1R), dual port (2RW), multi port (1R1W 2R1W, 2R2W) Bit-write capability bank architecture available Zero hold time data address control pins Flexible aspect ratio 256K-bit single port(1RW) SRAM 1M-bit single port(1RW) repairable SRAM 128K-bit dual port(2RW) SRAM 1M-bit single port(1R) via-1 programmable 16K-bit multi port(1R1W, 2R1W, 2R2W) register files 32K-bit with binary (on-demand) 64K-bit FIFO (On-demand) 4M-bit single port(1RW) SRAM with burst operations (On-demand) 4M-bit single port(1R) via-1 programmable (On-demand) Full Compliment Cells 2.5V/3.3V drive 5.0V tolerant I/Os levels (high, medium, slew rate control Minimum wire bonded pitch 70µm single line I/Os 35µm staggered I/Os Drive capabilities 12mA drive I/Os tolerant I/Os
STD150
Samsung ASIC
Features
Standard Interface compliant, 33/66MHz, tolerant compliant, full speed/low speed, 3.3V SSTL2 Class-I SDRAM interface, 200MHz ATA4/UDMA66, 3.3V, tolerant compliant, 66MHz 133MHz 266MHz PECL, 200MHz single ended, 500MHz differential point-to-point Ainterface HSTL, 300MHz, 1.5V SRAM interface with programmable output impedance control Swap pre-charge, pre-charge PCI-X, compliant, 133MHz, 3.3V Fully Integrated software support Logic synthesis: Synopsys Design compiler Physical synthesis: Synopsys Physical compiler Logic simulation: Cadence Verilog Cadence NC-Verilog/VHDL, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VCS. DFT, scan insertion ATPG: Synopsys TestGen, Synopsys TestCompiler, Synopsys TetraMax, Mentor Fastscan. Static timing analysis: Synopsys PrimeTime analysis: Avant! Star-RCXT Power analysis: Synopsys DesignPower, Sequence Watt Watcher, CubicPower (Samsung in-house tool). Formal verification: Synopsys Formality, Avant! Design VERIFYer, Verplex Tuxedo-LEC Fault simulation: Cadence Verifault Delay calculator: CubicDelay (Samsung in-house tool). Floor planner: Avant! PlanerPL, CubicPlan (Samsung in-house tool). Place Route: Avant! Apollo, Cadence Silicon Ensemble LVS: Dracula, Hercules, Calibre Easy Accurate Clock Tree Insertion user selectable clock tree cells Accurate pre-layout post-layout correlation Insertion delay, skew, transition time management Clock tree information file generation Tightly coupled with in-house delay calculator, CubicDelay. more information flow, refer "Clock Analysts Flow (with CTC) User Guide CubicDelay" included Samsung Design Kit.
Samsung ASIC
STD150
Support
Support
Samsung provides effective solution multi-million gate designs very deep submicron technology. large designs, static timing verification methodology will reduce design cycle time reduce ever increasing time-tomarket pressure. design-for-test (DFT) methodology service enables phases test insertion, test pattern generation, fault grading resulting highest test coverage. STD150 design methodology supports rich collection industry standard tools from Cadence, Synopsys, Mentor Graphics, Avant! Solaris platforms. Customers choose from among industry leading tools design capture, synthesis, simulation, layout. Several powerful proprietary software tools seamlessly integrated design kits improve design quality. STD150 design methodology uses proprietary delay calculator, CubicDelay, high timing simulation accuracy. Cell delay calculated based matrix delay parameters each macrocell signal interconnection delay calculated based tree analysis.
Product Family
STD150 library includes following design elements: Analog core cells Digital core cells Internal macrocells Compiled memory macrocells Input/Output cells 1.4.1 ANALOG CORE CELLS Introduction Analog Cores (see Appendix glossary analog terms) Samsung leading supplier cell based mixed signal design elements. leading supplier mixed signal elements, Samsung more analog design experience than other ASIC suppliers. Analog cell development been will continue part strategic focus Samsung ASIC. Symbolic representations analog cells supplied design entry Customers Samsung design technology center replaced with cell physicals during place route. Samsung design methodology uses same automatic layout verification tools analog cells digital cells. Mixed signal designs processed same production line pure digital designs. Samsung's analog core family consists ADCs, DACs, PLLs, CODECs. brief description each follows. Analog-to-Digital Converter Analog-to-digital converters, ADCs, provides link between analog world digital systems. produces digital output, function analog input, f(A) While input assume infinite number values, output takes only finite digital values determined converter's resolution output word length. Thus, must approximate each input level with these values. This process also called quantization.
STD150
Samsung ASIC
Product Family
digital systems, input signal amplitude, sampled discrete time intervals then quantized into discrete steps output digital value, sampling time interval also known sampling frequency. Digital-to-Analog Converter Digital-to-Analog Converters, DACs, digital value analog signal conversion circuits. output form current voltage wave form. DACs provide interface between digital systems analog world. DACs employed variety applications from display systems voice synthesizers automatic test systems, digital controlled attenuators, process control actuators. Figure shows functional block diagram basic DAC. input digital value, made stream bits. output analog current voltage quantity, related input KVREF
where scale factor, VREF reference voltage, resolution expressed total number bits, coefficients. output exhibits discrete voltage levels ranging from zero maximum value
Vo(max)= VREF
with minimum step change given
Figure 1-1.
Functional Block Diagram Basic
Digital Data Input
Analog Output
Samsung ASIC
STD150
Product Family
Sigma-Delta ADC/DAC Samsung's process offers high speed high density, reduced accuracy signal range (dynamic range) analog components. Hence, exchange digital complexity resolution time resolution signal amplitude needed. good solution this trade-off over sampling data converter. over sampling sigma-delta converter ideal slow speed (audio band) applications. It's noise shaping (sigma-delta) feature produces high resolution output with signal noise ratio 100dB. ADC, analog signal converted differential signal then filtered with anti-aliasing filter. sigma delta modulator converts signal into over sampled noise-shaping 1-bit pulse density modulated (PDM) signal. digital decimation filter then rejects out-of-band noise outputs 16-bit high resolution digital signal that down sampled sampling rate, DAC, digital data over sampled interpolation filter converted noise shaped 1-bit signal through digital sigma-delta modulator. analog post filter rejects out-of-band noise. anti-image filter then rejects sampling images outputs high resolution analog signal. Phase Locked Loop Samsung's cores implemented analog function provide frequency multiplication enabling designers synchronize chip level clock networks common reference signal. past, designers wishing incorporate PLLs into digital design only options: special mixed signal process, typically expensive process combing bi-polar CMOS processing same silicon, implement analog functions. digital design requiring very large silicon area that could implemented standard CMOS digital process. This type design usually exhibits poor locking time. Samsung's cores analog PLLs implemented standard digital CMOS process. Advantages Samsung's cores are: Require only off-chip passive components implement function. need expensive mixed signal (bi-polar CMOS) process. Provide faster locking time than full digital implementation. Have jitter characteristics. Customer Service Technical Support Samsung provides full support customers needing analog cores. Support provided through Samsung's worldwide Technology Design Centers. addition, Samsung analog design engineers available design customize Samsung analog cores meet specific customer needs. Since mixed signal design quite different from digital design terms design techniques, layout, test methodology, Samsung provides mixed signal technical guide describing development steps. addition, each core fully documented delivered with data sheet. following description analog core data sheets:
STD150
Samsung ASIC
Product Family
Core Preview Describes main features specifications core that under development. Some specifications, such exact pin-out, finalized time publication. purpose this document provide customers with advanced product planning information. Preliminary Data Sheet Completely describes core. preliminary data sheet contains feature list, applications notes, timing diagrams, theory operation, core information, test guide, layout guide, preliminary AC/DC electrical information. electrical information based worst case simulation data prototype silicon performance. purpose this data sheet allow customers confidently begin active development with core. Final Data Sheet Updated version preliminary data sheet reflecting fully characterized silicon performance. Updates include more complete tighter electrical specifications. purpose this data sheet communicate confirmed performance core after full characterization passing qualification.
Samsung ASIC
STD150
Product Family
1.4.2 STANDARD LOGIC CELLS Samsung standard cell library designed enable designers achieve high-integration with best performance STD150. addition, this standard cell library carefully verified silicon ensure much higher manufacturability. this, system-on-chips (SoC) designed using these standard cells will obtained much higher yield. Rich standard cells, consisting about cells, with least four drive strengths have been optimized specifically synthesis place route tools. cells were selected achieve best performance with synthesis tool give designers elements need create high-integration designs. Each cell been carefully hand-crafted provide optimal solution high-integration applications with best performance. Each cells been very accurately modeled both timing power guarantee timing closure eliminate many meaningless iterative design cycles. models carefully qualified tested using in-house library automation environment. Some features STD150 standard cell library summarized follows: Complete optimized library with synthesis place route tool Hand-crafted layouts optimal densities each process manufacturing cost Reducing design time Providing more accurate timing power Complete interfaces with popular tools STD150 standard cell library contains protection diode cell. protection diode cell used avoid antenna effect. During place route, router connect wires input gates cells that longer than maximum length allowable antenna effect rule. protection diode cell used this case diode close input gates which meet rule. Also, protection diode added input drivers softmacro cores. protection diode cell composed forward reverse diodes. included this databook. addition, STD150 standard cell library contains several filler cells. During place route, filler cells used connect power ground rails across area including cells. filler cells also used make sure that gaps occur between well implant layers which cause some design rule violations.
STD150
Samsung ASIC
Product Family
1.4.3 COMPILED MEMORY Today's System-On-Chip (SoC) designs require various configurations embedded memories. These configurations must optimized each process also optimized speed, density, power consumption. Samsung's memory compiler, called CubicCompiler, designed under efficiency custom memory design achieve optimal designs. Using CubicCompiler helpful designers perform optimal floorplanning design because designers evaluate architectural tradeoffs between performance, area power easily varying aspect ratios, word depths word widths their designs. Once satisfied with resulting configuration, CubicCompiler allows designers easily generate complete models including functional model, timing model physical layout. There memory families STD150, high-density compiled memories low-power compiled memories. high-density memories fully optimized smallest area targeted highintegration applications. low-power memories fully optimized lowest power consumption targeted low-power applications. Memories STD150 fully user-configurable provided compiler follows: High-Density Compiled Memories Single-port synchronous SRAM Single-port synchronous SRAM with bit-write Single-port synchronous SRAM with redundancy Dual-port synchronous SRAM Dual-port synchronous SRAM with bit-write Multi-port synchronous register file Multi-port synchronous register file with bit-write Single-port synchronous via-1 programmable Synchronous First-In First-Out Memory (On-demand) Synchronous Content Addressable Memory with binary (On-demand) High-capacity 4Mbits) single-port synchronous SRAM with burst operations (On-demand) High-capacity 4Mbits) single-port synchronous via-1 programmable (On-demand) Low-Power Compiled Memories (Under development) Single-port synchronous static Single-port synchronous static with bit-write Single-port synchronous static with redundancy Dual-port synchronous static Dual-port Synchronous static with bit-write STD150 compiled memory families adopt most advanced memory design techniques such self-controlled timing circuits, partial activation architecture, multi-stage power decoding structure high-sensitivity sense amplifiers with high stability, dramatically improve performance reduce power consumption. Such circuits extensively optimized specified voltage, temperature process give designers high performance high stability. compiled memories provide edge-triggered synchronous read write operations, bit-write byte write capability, zero hold time data-in, addresses control pins. Fully static design provides low-voltage data retention zero standby current. case multi-port register file, 2-port(1read/1-writ), 3-port(2-read/1-write) 4-port(2-read/2-write) available.
Samsung ASIC
STD150
Product Family
speciality memory, types memories supported customer's requirements: Synchronous First-In First-Out Memory (FIFO) synchronous Content Addressable Memory with Binary state (CAM). FIFO, which widely used communication buffering types applications, also fully synchronous operation rising-edge clock. CAM, which useful many applications such cache tables translation look-up table buffers, also fully synchronous operation rising-edge clock. Additional information about above speciality memory obtained from your local Samsung Design Center Samsung's worldwide headquarters. SoC(System-On-Chip) design, memory becomes much more dominant larger memory required. support high-capacity memory, which covers from 2M-bit 4M-bit, provided user-configurable compiler: HighCapacity Single-Port Synchronous SRAM with Burst features (HCSPSRAM) High-Capacity Single-Port Synchronous Via-1Programmable (HCVROM). HCSPSRAM contains both Row-Redundancy Column-Redundancy schemes guarantee higher yield provides burst-read burst-write operations suitable cache applications. HCVROM via-1 programmable targeted high-density applications with lower power consumption. HCVROM easily extended 4Mbits. Those memories will also supported customer's requirements. Additional information obtained from your local Samsung Design Center Samsung's worldwide headquarters. Built-In-Self-Test (BIST) circuitry available most STD150 compiled memories. BIST circuits designed detect fault types that impact functionality memory generated softmacro-based BIST generator. softmacro-based BIST generator generates either individual BIST netlist each memory shared BIST netlist memories design. However, when several memories same different type area used design, generate individual BIST netlist each memory, there some redundant blocks because individual BIST netlist same function. this case, would better shared BIST netlist eliminate such redundancies. case compiled memory with redundancy, supports BuiltIn-Redundancy-Analysis (BIRA) repair failed bits.
STD150
1-10
Samsung ASIC
Product Family
1.4.4 INPUT/OUTPUT CELLS There about 1000 different cells STD150 library designer choose from. Three types output buffers bi-directional buffers (non-inverting, tri-state, open drain) available range drive capabilities from 12mA 2.5V, 3.3V drive outputs, from tolerant cells. Three levels slew rate control provided each buffer type except drive buffers, reduce output power ground noise signal ringing, especially simultaneously switching outputs. buffers have been fully characterized protection latch-up resistance. Test logic provided enable efficient parametric testing input buffers including LVCMOS level converters, Schmitt trigger input buffers, clock drivers, oscillator buffers. 100K pull-down pull-up resistors optional features. 1.4.4.1 Applications
support mixed voltage environments, LVCMOS Schmitt trigger cells available 2.5V, 3.3V interface tolerant interface. application diagram follows. Figure 1-2. Applications
2.5V 2.5/ tolerant Internal Circuit operating voltage: 1.2V
2.5V 3.3V
3.3V 3.3/ tolerant
Input Buffer
Output Buffer
1.4.4.2
Cell Drives Options
provide flexibility, designer choose from various output current drive levels. choice current drive level affects propagation delay noise. Slew rate control helps decrease system noise output signal overshoot undershoot caused switching output buffers. output signal edge slew rates slowed down selecting high slew rate control cells.
Samsung ASIC
STD150
Product Family
1.4.4.4
Tolerant Buffers
Samsung's L18G process thick gate oxide option that optimized 2.5V/ 3.3V circuit operation. specified maximum voltage across gate oxide this process option 5.25V avoid gate oxide breakdown. special circuit available tolerant LVCMOS driver 6mA. This tolerant driver used normal 2.5V 3.3V buffer. Figure 1-3. Tolerant Buffers
2.5V/3.3V Output voltage 2.5V/3.3V Open drain output tolerant input Tri-state output Bi-directional 0.13µm 2.5V/3.3V process Normal 5.0V process 2.5V/3.3V 5.0V
1.4.4.5
Buffers
buffers designed industry standard high performance local applications. STD150 library offers input, output, bi-directional buffers 33MHz 66MHz operation compliant with local specification 2.2. 1.4.4.6 (Universal Serial Bus) Buffers
STD150 library offers full speed speed compliant buffers. 1.4.4.7 Other Buffers STD150 library also offers various other buffers including HSTL, SSTL2, GTLp, AGP, PECL, LVDS. more information about buffers that included this data book, please contact your local Samsung Technology Design Centers.
STD150
1-12
Samsung ASIC
Timings
Timings
1.5.1 WIRE LENGTH LOAD Table 1-1, Table 1-2, Appendix show equivalent standard load matrix 7metal layer interconnect. equivalent standard load values function gate count fanout. These values based capacitive loading used with wire length estimates which affect propagation delay.
Samsung ASIC
1-13
STD150
Timings
Table 1-1.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000 0.518 0.541 0.600 0.894 3.457 4.831 5.315 5.801 6.468 6.927 7.980 8.965 11.665 14.191 16.557 18.772 21.535 24.148 27.079 29.472 33.049 0.569 0.594 0.661 0.982 3.803 5.313 5.846 6.382 7.116 7.620 8.778 9.860 12.833 15.610 18.213 20.650 23.689 26.563 29.787 32.419 36.354
Equivalent Standard Loads 4-layer 5-layer Metal Interconnect
Fanouts
0.996 1.443 1.801 2.004 5.152 6.031 6.405 7.348 8.598 9.073 11.100 11.602 15.508 19.274 23.191 25.447 28.614 34.346 37.789 45.929 51.498
1.646 1.817 2.528 3.126 5.740 6.783 7.461 8.083 9.081 9.778 11.360 12.841 16.870 20.650 24.183 27.490 31.539 35.364 39.651 49.329 55.31
2.364 2.720 4.228 4.518 7.283 7.819 8.705 9.394 10.535 11.327 13.134 14.823 19.425 23.744 27.781 31.559 36.207 40.596 45.522 54.305 60.892
2.748 3.079 5.175 5.404 7.874 8.587 9.535 10.313 11.555 12.409 14.374 16.205 21.213 25.902 30.293 34.394 39.457 44.246 49.614 57.604 64.590
3.364 4.278 6.356 6.579 8.941 9.561 10.602 11.480 12.852 13.799 15.967 17.992 23.528 28.715 33.567 38.104 43.714 49.018 54.962 61.360 68.805
3.766 4.933 7.533 8.691 9.579 10.232 11.331 12.285 13.746 14.750 17.059 19.215 25.108 30.626 35.795 40.624 46.606 52.262 58.602 65.423 73.360
5.041 5.957 7.974 9.118 10.276 10.817 11.968 12.951 14.526 15.616 18.106 20.435 26.785 32.736 38.305 43.514 49.919 55.974 62.766 72.876 81.716
7.224 8.581 10.281 11.872 13.037 13.707 15.146 16.374 17.427 17.929 19.374 20.718 29.642 38.303 41.838 45.138 53.762 55.268 65.667 76.525 85.472
12.585 14.628 15.988 17.179 19.028 20.150 22.238 23.994 25.545 26.283 28.411 30.394 36.346 41.915 47.116 51.970 59.626 66.858 74.966 93.260 104.569
24.466 29.120 31.185 34.996 36.644 38.169 40.201 42.291 45.378 48.248 53.894 56.413 68.258 76.518 88.273 99.332 113.175 119.138 140.927 185.830 189.592
27.283 31.937 35.624 43.248 43.970 45.913 47.244 47.925 51.010 52.472 56.709 60.638 72.482 83.559 93.905 103.559 118.809 133.220 149.380 188.960 208.370
48.047 54.478 57.228 70.549 77.254 81.195 89.551 96.621 102.829 105.777 114.309 122.236 146.100 168.425 189.277 208.730 239.464 268.511 301.082 374.548 419.98
52.874 58.819 60.929 74.464 77.852 81.827 90.246 97.354 103.634 106.622 115.246 123.260 147.376 169.933 191.004 210.659 241.681 270.996 303.868 378.017 423.867
0.906 1.311 1.638 1.821 4.683 5.482 5.823 6.681 7.817 8.248 10.091 10.547 14.098 17.522 21.083 23.134 26.014 31.224 34.354 41.754 46.817
1.496 1.652 2.297 2.843 5.218 6.167 6.781 7.348 8.256 8.888 10.327 11.673 15.337 18.772 21.984 24.990 28.671 32.150 36.047 44.844 50.283
2.150 2.472 3.844 4.106 6.622 7.108 7.913 8.539 9.577 10.297 11.939 13.474 17.659 21.585 25.256 28.691 32.915 36.905 41.384 49.368 55.356
2.498 2.799 4.705 4.911 7.157 7.805 8.669 9.376 10.504 11.281 13.067 14.732 19.283 23.547 27.539 31.268 35.870 40.224 45.104 52.368 58.718
3.059 3.888 5.778 5.980 8.128 8.691 9.638 10.437 11.683 12.545 14.516 16.356 21.388 26.104 30.516 34.640 39.740 44.561 49.966 55.781 62.549
3.423 4.484 6.848 7.902 8.709 9.301 10.301 11.169 12.496 13.409 15.508 17.468 22.825 27.842 32.541 36.931 42.370 47.510 53.275 59.476 66.69
4.583 5.415 7.250 8.289 9.341 9.833 10.880 11.774 13.205 14.197 16.461 18.577 24.350 29.760 34.823 39.557 45.382 50.886 57.059 66.250 74.287
6.567 7.801 9.346 10.793 11.852 12.461 13.770 14.886 15.842 16.299 17.612 18.835 26.947 34.821 38.035 41.033 48.874 50.244 59.697 69.569 77.703
11.441 13.297 14.535 15.618 17.297 18.317 20.216 21.813 23.222 23.894 25.829 27.630 33.041 38.104 42.833 47.246 54.205 60.779 68.151 84.781 95.063
22.242 26.472 28.350 31.815 33.313 34.699 36.545 38.447 41.252 43.862 48.994 51.285 62.053 69.561 80.248 90.303 102.886 108.307 128.116 168.937 172.356
24.803 29.033 32.386 39.317 39.972 41.740 42.949 43.569 46.372 47.703 51.553 55.126 65.894 75.962 85.368 94.144 108.008 121.110 135.799 171.781 189.427
43.679 49.525 52.025 64.136 70.230 73.813 81.409 87.829 93.480 96.161 103.917 111.124 132.819 153.114 172.071 189.754 217.694 244.102 273.710 340.499 381.800
48.067 53.472 55.390 67.695 70.775 74.388 82.041 88.504 94.212 96.929 104.769 112.055 133.978 154.484 173.639 191.507 219.710 246.360 276.244 343.651 385.334
STD150
1-14
Samsung ASIC
Timings
Table 1-2.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000 0.419 0.439 0.486 0.724 2.799 3.913 4.305 4.699 5.240 5.610 6.465 7.262 9.449 11.494 13.411 15.205 17.443 19.559 21.933 23.872 26.770 0.467 0.486 0.541 0.805 3.110 4.348 4.783 5.220 5.821 6.234 7.183 8.069 10.498 12.772 14.902 16.894 19.382 21.732 24.370 26.526 29.744
Equivalent Standard Loads 6-layer 7-layer Metal Interconnect
Fanouts
0.815 1.179 1.474 1.638 4.215 4.935 5.240 6.014 7.035 7.423 9.081 9.492 12.689 15.770 18.974 20.821 23.411 28.102 30.919 37.579 42.136
1.346 1.486 2.067 2.559 4.697 5.551 6.104 6.614 7.431 8.000 9.293 10.506 13.803 16.894 19.785 22.492 25.805 28.935 32.443 40.360 45.256
1.935 2.224 3.461 3.695 5.961 6.398 7.122 7.685 8.618 9.268 10.746 12.128 15.894 19.425 22.730 25.821 29.624 33.215 37.246 44.431 49.82
2.248 2.520 4.234 4.419 6.441 7.026 7.803 8.439 9.453 10.154 11.760 13.260 17.354 21.193 24.785 28.142 32.283 36.203 40.594 47.132 52.846
2.754 3.498 5.201 5.382 7.821 7.821 8.673 9.394 10.516 11.291 13.065 14.720 19.248 23.494 27.465 31.175 35.766 40.104 44.970 50.203 56.293
3.081 1.035 6.163 7.112 7.839 8.372 9.272 10.053 11.246 12.069 13.957 15.722 20.543 25.059 29.287 33.238 38.134 42.760 47.949 53.529 60.022
4.124 4.874 6.526 7.461 8.405 8.850 9.791 10.596 11.884 12.778 14.815 16.718 21.915 26.783 31.340 35.600 40.844 45.797 51.352 59.626 66.858
5.909 7.022 8.411 9.715 10.667 11.215 12.392 13.398 14.258 14.669 15.850 16.951 24.252 31.339 34.232 36.929 43.986 45.220 53.726 62.612 69.933
10.297 11.968 13.083 14.057 15.567 16.484 18.195 19.632 20.900 21.504 23.246 24.866 29.738 34.293 38.549 42.522 48.783 54.701 61.336 76.303 85.557
20.018 23.825 25.516 28.634 29.982 31.228 32.892 34.602 37.126 39.476 44.094 46.157 55.848 62.604 72.222 81.273 92.596 97.476 115.305 152.043 155.120
22.323 26.130 29.148 35.386 35.974 37.567 38.653 39.213 41.734 42.933 46.398 49.614 59.305 68.366 76.831 84.730 97.206 109.000 122.218 154.602 170.484
39.311 44.573 46.823 57.722 63.207 66.431 73.268 79.045 84.132 86.545 93.525 100.012 119.537 137.803 154.864 170.777 195.925 219.692 246.340 306.450 343.62
43.260 48.126 49.850 60.925 63.699 66.949 73.836 79.653 84.791 87.236 94.293 100.850 120.580 139.035 156.275 172.356 197.740 221.724 248.620 309.285 346.800
0.734 1.061 1.327 1.474 3.793 4.441 4.717 5.411 6.333 6.681 8.173 8.543 11.419 14.193 17.077 18.738 21.071 25.291 27.827 33.821 37.92
1.213 1.339 1.860 2.303 4.226 4.996 5.492 5.953 6.687 7.199 8.364 9.455 12.423 15.205 17.807 20.242 23.224 26.041 29.199 36.325 40.730
1.742 2.002 3.114 3.327 5.364 5.758 6.409 6.917 7.758 8.341 9.671 10.913 14.305 17.484 20.457 23.240 26.661 29.894 33.522 39.988 44.838
2.024 2.268 3.811 3.978 5.797 6.323 7.022 7.594 8.508 9.138 10.585 11.933 15.620 19.073 22.307 25.327 29.055 32.583 36.535 42.417 47.56
2.478 3.150 4.679 4.844 6.583 7.039 7.807 8.455 9.463 10.161 11.758 13.248 17.325 21.144 24.718 28.059 32.189 36.094 40.472 45.183 50.665
2.774 3.632 5.547 6.400 7.053 7.533 8.344 9.047 10.122 10.862 12.561 14.150 18.488 22.553 26.358 29.913 34.319 38.482 43.153 48.175 54.020
3.7133 4.386 5.872 6.715 7.565 7.965 8.813 9.537 10.695 11.500 13.333 15.047 19.724 24.106 28.207 32.041 36.760 41.218 46.218 53.663 60.173
5.319 6.319 7.571 8.742 9.600 10.092 11.154 12.057 12.833 13.203 14.266 15.256 21.827 28.205 30.809 33.236 39.589 40.697 48.354 56.350 62.939
9.268 10.772 11.774 12.652 14.010 14.837 16.376 17.669 18.811 19.354 20.921 22.380 26.764 30.864 34.695 38.270 43.905 49.232 55.203 68.673 77.002
18.016 21.443 22.965 25.770 26.984 28.106 29.602 31.142 33.413 35.527 39.685 41.541 50.264 56.344 65.000 73.146 83.336 87.728 103.773 136.838 139.608
20.091 23.518 26.232 31.846 32.378 33.809 34.789 35.291 37.561 38.640 41.758 44.651 53.374 61.529 69.147 76.256 87.486 98.098 109.998 139.143 153.435
35.380 40.116 42.140 51.951 56.886 59.789 65.941 71.142 75.718 77.892 84.173 90.010 107.582 124.021 139.378 153.700 176.332 197.722 221.872 275.805 309.259
38.935 43.313 44.866 54.833 57.329 60.254 66.453 71.689 76.313 78.512 84.864 90.764 108.521 125.132 140.647 155.122 177.966 199.551 223.827 278.358 312.12
Samsung ASIC
1-15
STD150
Timings
1.5.2 TIMING PARAMETERS This section defines discusses timing parameters. 1.5.2.1 Rise Fall Transition Time Rise time, fall time, defined time that waveform takes transition between supply voltage (Figure 1-5). Figure 1-4. Rise Fall Transition Time
1.5.2.2
Propagation Delay
Propagation delay, defined time from when input waveform reaches supply voltage time that output waveform reaches supply voltage (Figure 1-6). Figure 1-5. Propagation Delay
tPLH
tPHL
tPLH
tPHL
STD150
1-16
Samsung ASIC
Timings
1.5.2.3
Setup Hold Time
Setup time, tSU, defined minimum time that data signal must stable before active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Hold time, tHD, defined minimum time that data signal must remain valid after active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Figure 1-6. Setup Hold Time
1.5.2.4 Recovery Time Recovery time, tRC, defined time between release asynchronous control signal from active state circuit next active clock edge (Figure 1-8). active clock edge occurs soon after release control signal, violation occurs that result erroneous value being clocked circuit. Figure 1-7. Recovery Time
Samsung ASIC
1-17
STD150
Timings
1.5.2.5
Removal Time
Removal time, tRM, defined minimum time between active clock edge release asynchronous control signal from active state (Figure 19). control signal released from active state soon after active clock edge, violation occurs that result erroneous value being clocked into circuit. Figure 1-8. Removal Time
1.5.2.6 Minimum Pulse Width Minimum pulse width, tPW, defined minimum time allowed high phase signal measured time between rising falling edges reaching supply voltage (Figure 1-10). short pulse width results timing violation result signal being recognized circuitry. Figure 1-9. Minimum Pulse Width
tPWH tPWL
1.5.2.7 Minimum Period Minimum period, tPRD, defined minimum allowable time complete cycle signal (Figure 1-11). short period results timing violation result signal being recognized circuitry. Figure 1-10. Minimum Period
tPRD
STD150
1-18
Samsung ASIC
Timings
1.5.3 BEST WORST CASE CONDITIONS timing value best-case (worst-case) calculated using derating factor derived from following equations: (TWC) TNOM where, (TWC) best-case (worst-case) timing. local process derating factor which different value according each cell, local temperature derating factor which different value according each cell, local voltage derating factor which different value according each cell, TNOM nominal timing characterized under typical-process, 25°C 1.2V power supply. best-case (worst-case) timing values determined picking proper derating values from Table 1-3, Table Table 1-5. Derating factors conditions between those shown tables determined linear interpolation. 1.5.4 DERATING FACTORS STD150 Cell timing primarily determined cell drive capability loading determined cell input capacitance wiring. following critical variables also affect timing system environment design: Process variation Supply voltage Junction Temperature
Process variation occurs manufacturing environments variation change physical characteristics. variation affects electrical characteristics devices, increasing decreasing performance power. other hand, design chips which operate wide range voltage temperature environments, have consider typical-case, worstcase best-case conditions compensate variations. yield much more timing accuracy, cell-specific local derating factor used STD150 standard cells. example, process, temperature voltage derating factors cell follows Table 1-3, Table Table respectively. Table 1-3. STD150 Cell Process Derating Factor (KP) Slow 1.233 1.000 Fast 0.864
Process Factor (KP) Table 1-4. Temp. Table 1-5. Voltage (oC)
STD150 Cell Temperature Derating Factor (KT) 1.083 1.052 1.039 1.000 0.989 0.963
STD150 Cell Voltage Derating Factor (KV) 1.10 1.114 1.20 1.000 1.30 0.920
Notice that shown Table 1-3, Table Table only available standard cells.
Samsung ASIC
1-19
STD150
1.5.5
DELAY MODEL
STD150 cell timing characteristics consist following components: Cell propagation delay from input output transitions based input waveform slope, fanout distributed interconnection wire resistances capacitances. Interconnection wire delay. Timing requirement parameters including time, hold time, recovery time, skew time, minimum pulse width. Derating factors junction temperature, power supply voltage, process variation. accomplish accurate timing model, dimensional table look-up delay model been developed. index variables this table input waveform slope output load capacitance (Figure 1-12). Samsung's design methodology supports n-dimensional table model, even though dimensional model used. Figure 1-11. 2-Dimensional Table Delay Model
Propagation Delay [ns] Input Waveform Slope [ns] Load [pF]
Table shows propagation delay data 2-input NAND cell. data this table high-to-low transition delay times from input pins output pin. number points values index variables differ each cell. Table 1-6.
SLOPE
Table Delay Model Example
0.003 0.02951 0.05192 0.07615 0.10730 0.14177 0.012 0.05674 0.08228 0.12041 0.16793 0.21847 0.037 0.13300 0.15866 0.20552 0.28622 0.36820 0.087 0.28564 0.31147 0.35758 0.45226 0.58147 0.163 0.51755 0.54348 0.58935 0.68260 0.82528 0.263 0.82271 0.84869 0.89445 0.98697 1.12780
0.011 0.112 0.293 0.656 1.200
STD150
1-20
Samsung ASIC
Notice that 5-by-6 table used. This general table delay model provides great flexibility well high accuracy since extensive software revisions required when cell library updated. other timing components, such interconnection wire delay, timing requirement parameters derating factors characterized commonly accepted industry. Figure 1-13 summarizes features STD150 library delay model. Figure 1-12. Features Delay Model
dimensional table delay model output loading input waveform slope used. rise fall times delay times cell instances calculated recursively. input waveform slope each primary input loading capacitance each primary output assigned individually default. delays cells interconnection wires defined. effect distributed interconnection wire resistances capactitances cell delay analysed using lumped capacitances.
Samsung ASIC
STD150
Design Test (DFT) Methodology
Design Test (DFT) Methodology
Samsung's libraries designed with mind. Samsung's methodology includes ability include full partial scan path testing, boundary-scan JTAG board level testing, Memory BIST, analog testing. brief description features Samsung's scan, BIST, JTAG well more detailed discussion boundary scan architecture follows. 1.6.1 SCAN DESIGN Multiplexed scan flip-flops that minimize area delay overhead needed implement scan design. Automated design rule checking, scan insertion, test pattern generation High fault coverage synchronous designs
1.6.2 BIST (BUILT-IN SELF-TEST) Efficient test solution compiled memory macrocells speed parallel testing multiple memories Combination with internal scan design core testing
1.6.3 BOUNDARY SCAN IEEE 1149.1 JTAG boundary scan registers implemented with primitive cells Boundary Scan Description Language (BSDL) board testing combed with internal scan design core testing
JTAG Boundary Scan Architecture Boundary scan architecture contains (Test Access Port), controller, instruction register, group test data registers. instruction test data registers separate shift-register-based paths connected parallel with common serial data input common serial data output. common serial data input output connected TAP, signals. controller selects alternative instruction test data register paths between TDO. schematic view level design JTAG test logic architecture shown Figure 1-14.
STD150
1-22
Samsung ASIC
Design Test (DFT) Methodology
Figure 1-14. JTAG Test Access Port (TAP) Block Diagram
Scannable Register Device Identity Register Instruction Register Controller Bypass Register TEST ACCESS PORT (TAP)
SYSTEM LOGIC
Multiplexer
Boundary Scan Path
Functional Block Descriptions (Test Access Port) general-purpose port that provides access many test support functions built into component including test logic. includes three inputs (TCK -Test Clock Signal; -Test Mode Signal; -Test Data Input) output (TDO -Test Data Output) required test logic. optional fourth input (TRSTN Test Reset) provided asynchronous initialization test logic. values applied pins sampled rising edge TCK, value placed changes falling edge TCK. Controller controller receives TCK, interprets signals TMS, generates clock control signals both instruction test data registers other parts test circuit required. Instruction Register/Instruction Decoder Test instructions shifted into held instruction register. Test instructions include tests performed test data register addresses accessed. basic 3-bit instruction register instruction decoder provided macrofunctions library. Test Data Registers Test data registers include bypass register, boundary scan register, device identification register other design specific registers. Only bypass boundary scan registers mandatory; rest optional.
Samsung ASIC
1-23
STD150
Design Test (DFT) Methodology
Test Data Registers Description Bypass register: bypass register provides single-bit serial connection through circuit when none other test data registers selected. used allow test data flow through given device other components product without affecting normal operation. Boundary scan register: boundary scan register detects typical production defects board interconnects, such opens, shorts. also allows access component inputs outputs when testing their logic sample flow-through signals. Special boundary scan register macrocells provided this purpose. Design-specific test data register: These optional registers provided allow access designspecific test support features integrated circuit, such self-test scan test. Device identification register: This optional test data register that allows manufacturer part number revision identified. 32-bit identification register partitioned into four fields: Device version identifier field Device part number Manufacturer's JEDEC number first four bits beginning from field bits field bits field tied High
ASIC designer free fill version part number manner long twenty bits used. Samsung's JEDEC code: decimal 1001110 Continuation field bits) 0000 Contents device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 Users define these fields.
STD150
1-24
Samsung ASIC
Maximum Fanouts
Maximum Fanouts
1.7.1 INTERNAL MACROCELLS maximum fanouts STD150 primitive cells tabulated Table Appendix Note that these fanout limitation values calculated when rise fall times input signal 0.112ns. Depending rise fall times, maximum fanout limitations varied case case. following table maximum fanout values pins STD150 internal macrocells listed. Table 1-7. Maximum Fanouts Internal Macrocells (When input tR/tF 0.112ns, fanout (SL) 0.00305pF) Cell Output Maximum Name Fanouts
ad2b ad2bd2 ad2bd4 ad2bd8 ad2d2 ad2d4 ad2d8 ad3d2 ad3d4 ad4d2 ad4d4 ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d4 ao21d2 ao21d4 ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2a ao222d2 ao222d4 ao22a ao22d2a ao22d2 ao22d4
Cell Name
ao31 ao31d2 ao31d4 ao311 ao311d2 ao3111 ao3111d2 ao31d2 ao31d4 ao32 ao321 ao321d2 ao322 ao32d2 ao33 ao331 ao331d2 ao332 ao332d2 ao33d2 busholder cglp cglpd2 cglpd4 fad2 fad4 fd1d2 fd1d4 fd1cs fd1csd2 fd1csd4 fd1q fd1qd2 fd1qd4 fd1s fd1sd2 fd1sd4 fd1sq fd1sqd2 fd1sqd4 fd2d2 fd2d4 fd2cs fd2csd2
Output
Maximum Fanouts
10000
Samsung ASIC
1-25
STD150
Maximum Fanouts
Cell Name
fd2csd4 fd2q fd2qd2 fd2qd4 fd2s fd2sd2 fd2sd4 fd2sq fd2sqd2 fd2sqd4 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s fd3sd2 fd3sq fd3sqd2 fd4d2 fd4cs fd4csd2 fd4q fd4qd2 fd4s fd4sd2 fd4sq fd4sqd2 fd5d2 fd5s fd5sd2 fd6d2 fd6s fd6sd2
Output
Maximum Fanouts
Cell Name
fd7d2 fd7s fd7sd2 fd8d2 fd8s fd8sd2 fds2 fds2d2 fds2cs fds2csd2 fds2s fds2sd2 fds3 fds3d2 fds3cs fds3csd2 fds3s fds3sd2 fj2d2 fj2s fj2sd2 fj4d2 fj4s fj4sd2 ft2d2 had2 had4
Output
Maximum Fanouts
STD150
1-26
Samsung ASIC
Maximum Fanouts
Cell Name
ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 ivd24 ivtd2 ivtd4 ivtd8 ivtd16 ld1d2 ld1d4 ld1q ld1qd2 ld1qd4 ld2d2 ld2q ld2qd2 ld3d2 ld4d2 ld5d2 ld5q ld5qd2 ld6d2 ld6q ld6qd2 mx2d2 mx2d4 mx2d8 mx2i mx2ia mx2id2 mx2id2a mx2id4 mx2id4a mx4d2 mx4d4 mx8d2 mx8d4 nd2b
Output
Maximum Fanouts
1103 1651 1091
Cell Name
nd2bd2 nd2bd4 nd2bd8 nd2d2 nd2d4 nd2d8 nd3b nd3bd2 nd3bd4 nd3bd8 nd3d2 nd3d4 nd3d8 nd4d2 nd4d4 nd5d2 nd5d4 nd6d2 nd6d4 nd8d2 nd8d4 nid16 nid2 nid3 nid4 nid6 nid8 nid24 nitd16 nitd2 nitd4 nitd8 nr2a nr2b nr2bd2 nr2bd4 nr2bd8 nr2d2 nr2d4 nr2d8 nr3a nr3d2 nr3d4 nr4d2 nr4d4 nr5d2 nr5d4 nr6d2 nr6d4 nr8d2 nr8d4
Output
Maximum Fanouts
1091 1634 1087
Samsung ASIC
1-27
STD150
Maximum Fanouts
Cell Name
oa211 oa2111 oa2111d2 oa211d2 oa211d4 oa21d2 oa21d4 oa22 oa221 oa221d2 oa221d4 oa222 oa2222 oa2222d2 oa2222d4 oa222d2 oa222d4 oa22a oa22d2 oa22d2a oa22d4 oa22d4a oa31 oa311 oa3111 oa31d2 oa31d4 oa32 oa32d2 oa321 oa321d2 oa322 oa322d2 oa33 oa33d2 or2b or2bd2 or2bd4 or2bd8 or2d2 or2d4 or2d8 or3d2 or3d4 or4d2 or4d4 or5d2 or5d4 scg1 scg1d2 scg2 scg2d2 scg2d4 scg3 scg3d2 scg3d4 scg4 scg4d2 scg4d4 scg5 scg5d2
Output
Maximum Fanouts
Cell Name
scg5d4 scg6 scg6d2 scg6d4 scg7 scg7d2 scg7d4 scg8 scg8d2 scg9 scg9d2 scg9d4 scg10 scg10d2 scg10d4 scg11 scg11d2 scg12 scg12d2 scg12d4 scg13 scg13d2 scg13d4 scg14 scg14d2 scg14d4 scg15 scg15d2 scg15d4 scg16 scg16d2 scg16d4 scg17 scg17d2 scg17d4 scg18 scg18d2 scg18d4 scg19 scg19d2 scg20 scg20d2 scg20d4 scg21 scg21d2 scg22 scg22d2 scg22d4 xn2d2 xn2d4 xn2d8 xn3d2 xn3d4 xo2d2 xo2d4 xo2d8 xo3d2 xo3d4
Output
Maximum Fanouts
STD150
1-28
Samsung ASIC
Maximum Fanouts
1.7.2 Cells maximum fanouts cells follows. Table 1-8. Maximum Fanouts Cells (When input tR/tF 0.112ns, fanout (SL) 0.00305pF) Cell Output Maximum Name Fanouts
phic phic_abb phicc_abb phicd phicd_abb phicen_abb phicu phicu_abb phis phis_abb phisd phisd_abb phisu phisu_abb phsckdc2 phsckdc4 phsckdc6 phsckdc8 phsckdcd2 phsckdcd4 phsckdcd6 phsckdcd8 phsckdcu2 phsckdcu4 phsckdcu6 phsckdcu8 phsckds2 phsckds4 phsckds6 phsckds8 phsckdsd2 phsckdsd4 phsckdsd6 phsckdsd8 phsckdsu2 phsckdsu4 phsckdsu6 phsckdsu8 phtic phticd phticu phtis phtisd phtisu phsosck1 phsosck17 phsoscm1 phsoscm16 phsoscm2 phsoscm26 phsoscm3 phsoscm36 pmic pmic_abb pmicc_abb pmicd pmicd_abb 1075 2151 3138 4189 1074 2150 3137 4186 1074 2152 3136 4188 1074 2152 3137 4189 1074 2151 3137 4189 1074 2152 3136 4187 1889 1873 4273 4267 6051 6051
Cell Name
pmicen_abb pmicu pmicu_abb pmis pmis_abb pmisd pmisd_abb pmisu pmisu_abb pmsckdc2 pmsckdc4 pmsckdc6 pmsckdc8 pmsckdcd2 pmsckdcd4 pmsckdcd6 pmsckdcd8 pmsckdcu2 pmsckdcu4 pmsckdcu6 pmsckdcu8 pmsckds2 pmsckds4 pmsckds6 pmsckds8 pmsckdsd2 pmsckdsd4 pmsckdsd6 pmsckdsd8 pmsckdsu2 pmsckdsu4 pmsckdsu6 pmsckdsu8 pmsosck1 pmsoscm1 pmsoscm2 pmtic pmticd pmticu
Output
Maximum Fanouts
1074 2151 3137 4189 1074 2152 3136 4186 1075 2150 3138 4186 1074 2151 3136 4186 1075 2150 3138 4188 1074 2150 3138 4186 1865 4133
Samsung ASIC
1-29
STD150
Maximum Fanouts
<Condition> Library STD150 1.2V Fanout 0.00312pF input FD1) Standard Load (SL) 0.00305pF Input slope 0.112ns Maximum output transition time (mott) 1.1ns Maximum frequency 300MHz length (µm/fanout): branch length each fanout except trunk Table 1-9. Maximum Fanout Cells
2000 5000 2000 5000 case that interconnection considered 1091 1634
Trunk width (µm) length (µm/fanout) Trunk length (µm) nid2 nid3 nid4 nid6 nid8 nid16 nid24
high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis.
STD150
1-30
Samsung ASIC
Package Capability Pitch Lead Count
Package Capability Pitch Lead Count
Appendix Samsung's package capability this writing. most current package availability capability obtained from your local Samsung Technology Design Centers.
Samsung ASIC
STD150
Crystal Oscillator Consideration
Crystal Oscillator Consideration
1.9.1 OVERVIEW STD150 library contains cell commonly referred on-chip oscillator. on-chip oscillator itself really oscillator, amplifier suitable being used feedback amplifier oscillator circuit. With proper selection off-chip components (crystal ceramic resonator, resistors capacitors) this oscillator circuit performs better than other types clock oscillators. very important select suitable off-chip components on-chip oscillator circuitry. should noted, however, that Samsung cannot assume responsibility writing specifications off-chip components performance finished oscillator design production since optimization crystal oscillator circuit will specific given application. Samsung does, however, spec guarantee performance on-chip oscillator cell. 1.9.2 OSCILLATOR DESIGN CONSIDERATIONS designers have number options clocking system. primary decision whether on-chip oscillator external oscillator. choice on-chip oscillator, designer must then choose type oscillator off-chip component values. These decisions will based both economic technical requirements.The following section discusses some factors considered. 1.9.2.1 On-Chip Oscillator most cases, on-chip oscillator with appropriate external components provides most economical solution clocking problem. Exceptions arise server environments when frequency tolerances tighter than about 0.01%. external components commonly used oscillator circuit positive reactance (normal crystal oscillator), capacitors, resistors, shown Figure below. Figure 1-15. CMOS Oscillator Inside Chip PADA
PADY
Feedback Amplifier
1.9.2.2 Crystal Specifications Specifications appropriate crystal very critical. fundamental mode crystal medium better quality used. Crystal resistance affects start-up time steady state amplitude compensated choice however, lower crystal resistance, better. discussion external components follows below.
STD150
1-32
Samsung ASIC
Crystal Oscillator Consideration
1.9.2.3 Oscillation Frequency oscillation frequency mainly determined crystal. on-chip oscillator little effect frequency. influence on-chip oscillator frequency results from input output (pin-to-ground) capacitances which parallel PADA-toPADY (pin-to-pin) capacitance which parallels crystal. input pin-topin capacitances about each. 1.9.2.4 Selection Optimal values depend whether quartz crystal ceramic resonator being used, application-specific requirements start-up time frequency tolerance. Start-up time sometimes more critical microcontroller systems than frequency stability because various reset initialization requirements. Accuracy oscillator frequency less commonly critical, when oscillator being used time base. general rule, fast start-up stable frequency tend pull oscillator design opposite directions. Considerations both start-up time frequency stability over temperature suggest that should about equal least 15pF (but they don't have either). Increasing value these capacitors above 40pF 50pF improves frequency stability, also increases start-up time. capacitors large (several hundred pF), oscillator won't start all. 1.9.2.5 Selection
large ohm) holds on-chip oscillator CMOS inverter) linear region allowing oscillate. inverter fairly output resistance which de-stabilizes oscillator circuit. several K-ohms added feedback network, shown Figure 1-15, stabilize oscillator circuit. higher oscillator frequencies, 20pF 30pF capacitor sometimes used place compensate internal propagation delay. 1.9.3 CONSIDERATIONS
Noise glitches arising PADA PADY pins wrong time cause miscount internal clock-generating circuitry. These kinds glitches produced through capacitive coupling between oscillator components traces carrying digital signals with fast rise fall times. this reason, oscillator components should mounted close chip have short, direct traces PADA, PADY, pins. possible, dedicated pins on-chip oscillator. addition, surrounding oscillator components with "quiet" traces (VDD VSS) will alleviate capacitive coupling signals having fast edges. minimize inductive coupling, layout should minimize lead, wire, trace lengths oscillator components.
Samsung ASIC
1-33
STD150
Crystal Oscillator Consideration
Paths that need checked are: PADA through resonator PADY; PADA through pin; PADY through pin. unusual find that ground ends connect through long traces board. 1.9.4 TROUBLESHOOTING OSCILLATOR PROBLEMS cause oscillator problem difficult find once detected. Below some suggested first things investigate oscillator problem detected. There significant differences stray capacitances between test fixture actual application, particularly actual application multilayer board. This result oscillator problem occurring test fixture that will occur board, problem occurring board that cannot duplicated test fixture. Noise glitches present test fixture present application board another cause oscillator problem. Capacitive coupling between oscillator circuitry other signal should investigated. Inductive coupling also possible there lead, trace, wire with large current nearby. Finally, should overlooked that software problems mimic symptoms slow-starting oscillator incorrect frequency. Software should also invigilated.
STD150
1-34
Samsung ASIC

Library Description Features Support Product Family. 1.4.1 Analog Core

Top Searches for this datasheet

Other recent searches