Library Description Features Support Product Family. 1.4.1 Analog Core

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Library Description Features Support Product Family. 1.4.1 Analog Core

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Library Description Features Support Product Family. 1.4.1 Analog Core Cells. 1.4.2 Standard Logic Cells 1.4.3 Compiled Memory 1.4.4 Input/Output Cells 1-10 Timings. 1-13 Design Test (DFT) Methodology 1-21 Maximum Fanouts. 1-24 Package Capability Pitch Lead Count 1-31 Power Dissipation. 1-22 1.10 VDD/VSS Rules Guidelines. 1-36 1.11 Crystal Oscillator Considerations 1-43
Library Description
Library Description
STD131 Samsung's next generation Standard Cell library containing standard cells implemented Samsung's 0.18µm, process technology. Samsung's process uses metal interconnect layers. STD131 library contains diverse application specific digital analog System-on-Chip (SoC) applications. Samsung provides full range cells within STD131 library address challenges designing producing ultra power well high density devices that take advantage integration. With reduced power dissipation high density, STD131 help reduce system cost high performance applications such HDD, Networking, Displays. STD131 library supports gate counts million gates with usability. Gate delay better than Samsung's STD110 0.25µm library. Logic memory densities respectively times better than STD110. STD131 library also contains fully user configurable complied memories high density power applications. higher yield designs, Samsung also contains repairable compiled memory with redundant elements. STD131 library also supports wide range interface voltages standards. cells that drive 1.8V, 2.5V, 3.3V available 3.3V tolerant I/Os. Available standards include LVTTL, LVCMOS, PCI, PCI-X, OSC, AGP, PECL, HSTL, SSTL2, GTLp, LVDS, 1.1. better support design, robust collection digital analog cores available. Digital cores include ARM7TDMI, ARM9TDMI, ARM920T, ARM940T from Ltd., well Teak TeakLite cores from Group. Analog cores include ADCs, DACs, CODECs, PLLs with various configurations frequency ranges. thick oxide process option allows high resolution operation analog cores with 3.3V power supply. addition, STD131 library supports communication data transmission cores such 1.1, IEEE1284, IEEE1394 link controller, UART, controller, PCMCIA controller 10/100 ethernet MAC. Samsung's design methodology offers comprehensive timing driven design flow including automated time budgeting, tight floor plan synthesis integration, powerful timing analysis, timing driven layout. advanced characterization flow provides accurate timing data robust delay models L18, 0.18um very deep sub-micron process technology. Static verification methods, such static timing analysis formal equivalence checking, provide effective verification methodology with variety simulators. Samsung's Design-for-Test (DFT) methodology supports full partial scan chain design, BIST, JTAG boundary scan, Built-in-Redundancy-Analysis (BIRA) reparable SRAM. Samsung provides full test ready cores with efficient core test integration methodology.
Samsung ASIC
STD13
Features
Features
Robust 1.8V standard cell library including processor, DSP, analog cores. 0.18µm CMOS process technology with optional metal layers. High gate count design million gates with utilization layer metal. High speed input NAND typical gate delay 50ps with fanout 0.02pF wire load. Characterized industrial (-40°C 85°C) commercial (0°C 70°C) temperature ranges. Robust digital cores Hard macro cells ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, Teak, TeakLite. core peripherals AMBA, controller, SDRAM controller, Interrupt controller, IIC, WDT, RTC. Soft macro cells USB1.1, IrDA, 16C450 16C550 UART, Fast Ether MAC, P1394a LINK, IEEE1284, controller, PCMCIA controller. Ultra Voltage (1.8V) High Resolution (3.3V) Analog Cores Analog core supply voltages -1.8V, 2.5V, 3.3V. ADC: (250KHz, 1.8V 125MHz, 3.3V), (30MHz, 1.8V), (250KHz-10MHz, 3.3V) DAC: (80MHz, 1.8V), (2MHz 300MHz, 3.3V) CODEC: Sigma-Delta (8KHz 11KHz, 2.5V) PLL: 1.8V FSPLL (25MHz 300MHz 100MHz 500MHz), SSCG (1.8V, 200MHz) Fully User Configurable SRAMs ROMs High density power memory configurations Single port (1RW, 1R), dual port (2RW), multi port (1R1W 2R2W) Zero hold time synchronous mode Bit-write capability bank architecture Flexible aspect ratio 512K-bit single port SRAM 256K-bit dual port SRAM 512K-bit diffusion metal programmable 16K-bit multi port register files 64K-bit FIFOs 32K-bit (Content Addressable Memory) megabit reparable SRAM with redundancy Full Compliment Cells 1.8V/2.5V/3.3V drive 3.3V/5.0V tolerant I/Os levels (high, medium, slew rate control Minimum wire bonded pitch 70µm single line I/Os 35µm staggered I/Os Drive capabilities 24mA drive I/Os tolerant I/Os
STD13
Samsung ASIC
Features
Standard Interface compliant,33/66MHz, tolerant compliant, full speed/low speed, 3.3V SSTL2 Class-I SDRAM interface, 200MHz ATA4/UDMA66, 3.3V, tolerant compliant, 66MHz 133MHz 266MHz PECL, 200MHz single ended, 500MHz differential point-to-point Ainterface HSTL, 300MHz, 1.5V SRAM interface with programmable output impedance control Swap pre-charge, pre-charge PCI-X, compliant, 133MHz, 3.3V Fully Integrated software support Logic synthesis: Synopsys Design compiler Physical synthesis: Synopsys Physical compiler Logic simulation: Cadence Verilog Cadence NC-Verilog, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VCS. DFT, scan insertion ATPG: Synopsys TestGen, Synopsys TestCompiler, Synopsys TetraMax, Mentor Fastscan. Static timing analysis: Synopsys PrimeTime analysis: Avant! Star-RCXT Power analysis: Synopsys DesignPower, CubicPower (Samsung in-house tool). Formal verification: Synopsys Formality, Avant! Design VERIFYer, Verplex Tuxedo-LEC Fault simulation: Cadence Verifault Delay calculator: CubicDelay (Samsung in-house tool). Floor planner: Avant! PlanerPL, CubicPlan (Samsung in-house tool). Place Route: Avant! Apollo, Cadence Silicon Ensemble LVS: Dracula, Hercules, Calibre Easy Accurate Clock Tree Insertion user selectable clock tree cells Accurate pre-layout post-layout correlation Insertion delay, skew, transition time management Clock tree information file generation Tightly coupled with in-house delay calculator, CubicDelay. more information flow, refer "CTS Flow with Clock Tree Cell User Guide CubicDelay" included Samsung Design Kit.
Samsung ASIC
STD13
Support
Support
Samsung provides effective solution multi-million gate designs very deep submicron technology. large designs, static timing verification methodology will reduce design cycle time reduce ever increasing time-tomarket pressure. design-for-test (DFT) methodology service enables phases test insertion, test pattern generation, fault grading resulting highest test coverage. STD131 design methodology supports rich collection industry standard tools from Cadence, Synopsys, Mentor Graphics, Avant! Solaris platforms. Customers choose from among industry leading tools design capture, synthesis, simulation, layout. Several powerful proprietary software tools seamlessly integrated design kits improve design quality. STD131 design methodology uses proprietary delay calculator, CubicDelay, high timing simulation accuracy. Cell delay calculated based matrix delay parameters each macrocell signal interconnection delay calculated based tree analysis.
Product Family
STD131 library includes following design elements: Analog core cells Digital core cells Internal macrocells Compiled memory macrocells Input/Output cells 1.4.1 ANALOG CORE CELLS Introduction Analog Cores (see Appendix glossary analog terms) Samsung leading supplier cell based mixed signal design elements. leading supplier mixed signal elements, Samsung more analog design experience than other ASIC suppliers. Analog cell development been will continue part strategic focus Samsung ASIC. Symbolic representations analog cells supplied design entry Customers Samsung design technology center replaced with cell physicals during place route. Samsung design methodology uses same automatic layout verification tools analog cells digital cells. Mixed signal designs processed same production line pure digital designs. Samsung's analog core family consists ADCs, DACs, PLLs, CODECs. brief description each follows. Analog-to-Digital Converter Analog-to-digital converters, ADC, provides link between analog world digital systems. produces digital output, function analog input, f(A) While input assume infinite number values, output takes only finite digital values determined converter's resolution output word length. Thus, must approximate each input level with these values. This process also called quantization.
STD13
Samsung ASIC
Product Family
digital systems, input signal amplitude, sampled discrete time intervals then quantized into discrete steps output digital value, sampling time interval also known sampling frequency. Digital-to-Analog Converter Digital-to-Analog Converters, DACs, digital value analog signal conversion circuits. output form current voltage wave form. DACs provide interface between digital systems analog world. DACs employed variety applications from display systems voice synthesizers automatic test systems, digital controlled attenuators, process control actuators. Figure shows functional block diagram basic DAC. input digital value, made stream bits. output analog current voltage quantity, related input KVREF
where scale factor, VREF reference voltage, resolution expressed total number bits, coefficients. output exhibits discrete voltage levels ranging from zero maximum value
Vo(max)= VREF
with minimum step change given
Figure 1-1.
Functional Block Diagram Basic
Digital Data Input
Analog Output
Samsung ASIC
STD13
Product Family
Sigma-Delta ADC/DAC Samsung's process offers high speed high density, reduced accuracy signal range (dynamic range) analog components. Hence, exchange digital complexity resolution time resolution signal amplitude needed. good solution this trade-off over sampling data converter. over sampling sigma-delta converter ideal slow speed (audio band) applications. It's noise shaping (sigma-delta) feature produces high resolution output with signal noise ratio 100dB. ADC, analog signal converted differential signal then filtered with anti-aliasing filter. sigma delta modulator converts signal into over sampled noise-shaping 1-bit pulse density modulated (PDM) signal. digital decimation filter then rejects out-of-band noise outputs 16-bit high resolution digital signal that down sampled sampling rate, DAC, digital data over sampled interpolation filter converted noise shaped 1-bit signal through digital sigma-delta modulator. analog post filter rejects out-of-band noise. anti-image filter then rejects sampling images outputs high resolution analog signal. Phase Locked Loop Samsung's cores implemented analog function provide frequency multiplication enabling designers synchronize chip level clock networks common reference signal. past, designers wishing incorporate into digital design only options: special mixed signal process, typically expensive process combing bi-polar CMOS processing same silicon, implement analog functions. digital design requiring very large silicon area that could implemented standard CMOS digital process. This type design usually exhibits poor locking time. Samsung's cores analog PLLs implemented standard digital CMOS process. Advantages Samsung's cores are: Require only off-chip passive components implement function. need expensive mixed signal (bi-polar CMOS) process. Provide faster locking time than full digital implementation. Have jitter characteristics. Customer Service Technical Support Samsung provides full support customers needing analog cores. Support provided through Samsung's worldwide Technology Design Centers. addition, Samsung analog design engineers available design customize Samsung analog cores meet specific customer needs. Since mixed signal design quite different from digital design terms design techniques, layout, test methodology, Samsung provides mixed signal technical guide describing development steps. addition, each core fully documented delivered with data sheet. following description analog core data sheets:
STD13
Samsung ASIC
Product Family
Core Preview Describes main features specifications core that under development. Some specifications, such exact pin-out, finalized time publication. purpose this document provide customers with advanced product planning information. Preliminary Data Sheet Completely describes core. preliminary data sheet contains feature list, applications notes, timing diagrams, theory operation, core information, test guide, layout guide, preliminary AC/DC electrical information. electrical information based worst case simulation data prototype silicon performance. purpose this data sheet allow customers confidently begin active development with core. Final Data Sheet Updated version preliminary data sheet reflecting fully characterized silicon performance. Updates include more complete tighter electrical specifications. purpose this data sheet communicate confirmed performance core after full characterization passing qualification.
Samsung ASIC
STD13
Product Family
1.4.2 STANDARD LOGIC CELLS Standard logic cells lowest level logic function hierarchy. These cells include functions like NAND, NOR, XOR, flip-flops used logic design. standard cell library contains about standard logic cells. Most have three drive strength options (1X, 4X). Cell views include logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, layout physical, place route model. 1.4.3 COMPILED MEMORY STD131 library memories fully user configurable provided through compilers. different memory types provided STD131 targeted different types applications follows: STD131HD compiled memory targeted high density applications STD131LP compiled memory targeted power applications Twelve types STD131HD high density compiled memories available follows: Single-port synchronous SRAM with without bit-write. Dual-port synchronous SRAM with without bit-write. Single-port asynchronous SRAM with without bit-write. Single-port synchronous SRAM with redundancy. Synchronous diffusion programmable metal programmable ROM. Multi-port asynchronous register file. Synchronous FIFO (First-In-First-Out) memory. Synchronous (Content Addressable Memory). types STD131LP power compiled memories available follows: Single-port synchronous SRAM with without bit-write. Dual-port synchronous SRAM with without bit-write. Single-port asynchronous SRAM with without bit-write. Synchronous memories fully synchronous rising edge clock have zero wait state. They also have optional write capability. Address, DataIn, other control pins have zero hold time. Asynchronous memories have synchronous write operation asynchronous read operation. Multi-port register files have synchronous write operation rising edge clock asynchronous read operation. Four types configurations available multi-port register files. They port read write), port read, write read, write), port read write). STD131 library contains types speciality memories: FIFO (First-InFirst-Out) (Content Addressable Memory). FIFOs, widely used communications buffering applications, fully synchronous rising edge clock. CAMs, widely used cache tables translation look-up tables, also fully synchronous rising edge clock.
STD13
Samsung ASIC
Product Family
Memory becoming much more dominant larger memory required designs. STD131 compiled memory supports repairable memories, 64Kb with redundancy. These repairable memories redundancy scheme BIRA (Built-In-Redundancy-Analysis) help guarantee higher yield. number redundant rows varies with memory size. STD131 compiled memories provide power down mode significantly reduce power during read write operation. addition, stand-by mode provided which memory contents outputs stable power greatly reduced. STD131LP, low-power compiled memories, also partial array activation architecture bit-line partition structure reduce power even more. bank architecture provided STD131HD compiled memories, except dual-port synchronous SRAM specialty memories, improve performance reduce power. this bank architecture, only bank active while other bank stand-by mode. Flexible memory aspect ratios provided facilitate floor planning design. addition, automated datasheet generator documents memory configuration, timing, aspect ratio power consumption. Physical abstract data, also called phantoms black boxes, Silicon Ensemble Apollo generated provided. BIST (Built-In Self-Test-Circuitry provided most STD131 compiled memories. BIST circuits designed detect fault types that impact functionality memory. BIST circuitry generated soft macro based BIST generator. BIST generator generates both individual BIST netlist each memory shared BIST netlist memories used design. However, when several memories used design, better generate shared BIST netlist eliminate redundancy BIST circuitry over generating BIST circuits each memory.
Samsung ASIC
STD13
Product Family
1.4.4 INPUT/OUTPUT CELLS There about 1000 different cells STD131 library designer choose from. Three types output buffers bi-directional buffers (non-inverting, tri-state, open drain) available range drive capabilities from 24mA 1.8V, 2.5V, 3.3V drive outputs, from 3.3V tolerant cells. Three levels slew rate control provided each buffer type except drive buffers, reduce output power ground noise signal ringing, especially simultaneously switching outputs. buffers have been fully characterized protection latch-up resistance. Test logic provided enable efficient parametric testing input buffers including LVCMOS level converters, Schmitt trigger input buffers, clock drivers, oscillator buffers. 100K pull-down pull-up resistors optional features. 1.4.4.1 Applications
support mixed voltage environments, LVCMOS Schmitt trigger cells available 1.8V, 2.5V, 3.3V interface 3.3V, tolerant interface. application diagram follows. Figure 1-2. Applications
1.8V 1.8/ 3.3V tolerant 1.8V 2.5V Internal Circuit 2.5/ tolerant Operating Voltage: 1.8V 2.5V 3.3V 3.3/ tolerant
3.3V
Input Buffer
Output Buffer
STD13
1-10
Samsung ASIC
Product Family
1.4.4.2
Cell Drives Options
provide flexibility, designer choose from various output current drive levels. choice current drive level affects propagation delay noise. Slew rate control helps decrease system noise output signal overshoot undershoot caused switching output buffers. output signal edge slew rates slowed down selecting high slew rate control cells. 1.4.4.3 3.3V Tolerant Buffers
STD131 library optimized Samsung's L18, 0.18µm drawn, process technology. process technology optimized operation 1.8V. specified maximum voltage across thin gate oxide 1.95V avoid gate oxide breakdown. special circuit available 3.6V tolerant LVCMOS driver 6mA. This 3.6V tolerant driver used normal 1.8V buffer. Figure 1-3. 3.3V Tolerant Buffers
1.8V Output voltage 1.8V Open drain output 3.3V tolerant input Tri-state output Bi-directional 0.18µm 1.8V process Normal 3.3V process 1.8V 3.3V
Samsung ASIC
STD13
Product Family
1.4.4.4
Tolerant Buffers
Samsung's process thick gate oxide option that optimized 3.3V circuit operation. specified maximum voltage across gate oxide this process option 5.25V avoid gate oxide breakdown. special circuit available 5.25V tolerant LVCMOS driver 6mA. This 5.25V tolerant driver used normal 2.5V 3.3V buffer. Figure 1-4. Tolerant Buffers
2.5V/3.3V Output voltage 2.5V/3.3V Open drain output tolerant input Tri-state output Bi-directional 0.18µm 3.3V process Normal 5.0V process 2.5V/3.3V 5.0V
1.4.4.5
Buffers
buffers designed industry standard high performance 32-bit 64bit local applications. STD131 library offers input, output, bidirectional buffers 33MHz 66MHz operation compliant with local specification 2.2. 1.4.4.6 (Universal Serial Bus) Buffers
STD131 library offers full speed speed compliant buffers. 1.4.4.7 Other Buffers STD131 library also offers various other buffers including HSTL, SSTL2, GTLp, AGP, PECL, LVDS. more information about buffers that included this data book, please contact your local Samsung Technology Design Centers.
STD13
1-12
Samsung ASIC
Timings
Timings
1.5.1 WIRE LENGTH LOAD Table 1-1, Table Appendix show equivalent standard load matrix metal layer interconnect. equivalent standard load values function gate count fanout. These values based capacitive loading used with wire length estimates which affect propagation delay. Equivalent Standard Loads 4-layer 5-layer Metal Interconnect
Fanouts 0.795 0.893 1.224 1.374 4.104 7.429 8.171 8.915 9.944 10.647 12.267 13.781 17.931 21.816 25.456 28.856 33.106 37.122 41.625 0.755 0.848 1.163 1.305 3.899 7.057 7.761 8.470 9.446 10.116 11.653 13.092 17.035 20.726 24.183 27.413 31.450 35.265 39.545 43.045 48.265 1.635 2.015 2.517 2.799 6.291 8.427 8.952 10.269 12.015 12.681 15.511 16.214 21.675 26.935 32.411 35.562 39.990 48.001 52.812 1.553 1.915 2.391 2.659 5.976 8.005 8.505 9.755 11.415 12.047 14.736 15.403 20.590 25.588 30.791 33.785 37.990 45.602 50.173 60.980 68.374 2.297 2.840 3.533 4.370 8.021 9.480 10.427 11.297 12.690 13.663 15.875 17.944 23.578 28.858 33.799 38.419 44.076 49.423 55.417 2.183 2.698 3.356 4.151 7.620 9.005 9.905 10.732 12.057 12.980 15.082 17.047 22.399 27.415 32.108 36.498 41.872 46.952 52.645 65.492 73.437 3.204 4.104 5.909 6.312 10.181 10.929 12.165 13.127 14.722 15.828 18.354 20.712 27.149 33.181 38.826 44.106 50.600 56.736 63.620 3.045 3.899 5.614 5.998 9.671 10.381 11.557 12.472 13.986 15.037 17.437 19.677 25.791 31.521 36.885 41.901 48.070 53.899 60.438 72.098 80.842 3.840 4.907 7.234 7.549 11.003 12.000 13.326 14.413 16.147 17.344 20.086 22.649 29.643 36.200 42.344 48.068 55.145 61.836 69.338 3.647 4.661 6.872 7.171 10.452 11.399 12.659 13.692 15.340 16.476 19.082 21.517 28.161 34.389 40.218 45.665 52.387 58.744 65.872 76.480 85.755 4.702 5.976 8.277 9.194 12.494 13.362 14.814 16.045 17.962 19.285 22.314 25.145 32.879 40.127 46.911 53.251 61.094 68.503 76.812 4.468 5.677 7.864 8.734 11.870 12.694 14.074 15.242 17.064 18.320 21.198 23.887 31.236 38.122 44.564 50.588 58.039 65.078 72.972 81.466 91.350 5.263 6.893 10.830 12.147 13.385 14.297 15.836 17.169 19.210 20.616 23.840 26.854 35.088 42.803 50.027 56.775 65.137 73.039 81.899 5.000 6.549 10.289 11.539 12.716 13.582 15.045 16.311 18.250 19.584 22.647 25.511 33.334 40.663 47.525 53.937 61.879 69.387 77.805 86.862 97.397 7.047 8.326 11.748 12.744 14.358 15.116 16.726 18.102 20.299 21.822 25.305 28.559 37.435 45.751 53.535 60.812 69.767 76.259 87.718 6.694 7.909 11.161 12.106 13.639 14.360 15.889 17.196 19.283 20.732 24.039 27.131 35.562 43.464 50.858 57.771 66.279 74.316 83.332 96.755 108.492 10.096 11.992 14.370 16.594 18.222 19.155 21.169 22.883 24.356 25.055 27.076 28.954 41.425 53.533 58.472 63.080 75.133 77.242 91.773 9.592 11.391 13.651 15.763 17.311 18.196 20.110 21.740 23.137 23.803 25.722 27.507 39.354 50.856 55.549 59.927 71.377 73.379 87.185 101.602 113.482 17.588 20.442 22.346 24.009 26.590 28.159 31.078 33.533 35.700 36.732 39.708 42.474 50.795 58.578 65.850 72.631 83.328 93.437 104.769 16.708 19.421 21.228 22.809 25.261 26.751 29.525 31.856 33.915 34.895 37.722 40.350 48.255 55.649 62.557 69.000 79.161 88.765 99.531 123.818 138.836 34.192 40.696 43.582 48.909 51.212 53.340 56.183 59.104 63.417 67.431 75.316 78.842 95.393 106.937 123.366 138.822 158.169 166.500 196.954 32.482 38.661 41.403 46.464 48.651 50.673 53.374 56.149 60.246 64.059 71.551 74.899 90.624 101.590 117.198 131.881 150.259 158.175 187.106 246.722 251.716
Table 1-1.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000
Samsung ASIC
1-13
STD13
Timings
Table 1-2.
Gate Count 5000 10000 50000 100000 150000 200000 300000 400000 500000 600000 800000 1000000 1500000 2000000 2500000 3000000 4000000 5000000 6000000 7000000 8000000
Equivalent Standard Loads 6-layer Metal Interconnect
Fanouts 1.472 1.814 2.265 2.519 5.661 7.584 8.057 9.242 10.814 11.413 13.960 14.592 19.507 24.242 29.169 32.005 35.990 43.202 47.531 57.769 64.775 2.066 2.557 3.181 3.933 7.218 8.531 9.383 10.167 11.421 12.297 14.287 16.149 21.220 25.972 30.419 34.576 39.669 44.480 49.875 62.045 69.570 2.883 3.694 5.318 5.681 9.163 9.836 10.948 11.814 13.250 14.246 16.519 18.641 24.435 29.862 34.944 39.694 45.539 51.062 57.257 68.303 76.586 3.456 4.417 6.511 6.795 9.903 10.799 11.994 12.972 14.533 15.610 18.078 20.383 26.679 32.580 38.100 43.261 49.631 55.653 62.405 72.454 81.242 4.232 5.377 7.448 8.275 11.244 12.025 13.332 14.440 16.167 17.356 20.082 22.631 29.592 36.116 42.220 47.927 54.984 61.653 69.131 77.179 86.541 4.738 6.204 9.748 10.933 12.047 12.868 14.251 15.452 17.289 18.555 21.456 24.169 31.578 38.523 45.025 51.098 58.624 65.736 73.708 82.289 92.271 6.342 7.494 10.572 11.470 12.923 13.604 15.053 16.291 18.269 19.639 22.775 25.702 33.690 41.177 48.181 54.732 62.791 68.437 78.946 91.663 102.781 9.086 10.793 12.933 14.935 16.399 17.240 19.053 20.596 21.921 22.549 24.370 26.059 37.283 48.181 52.625 56.773 67.620 69.517 82.596 96.253 107.509 15.830 18.399 20.112 21.608 23.931 25.344 27.970 30.181 32.129 33.059 35.738 38.226 45.716 52.720 59.265 65.368 74.996 84.092 94.293 117.301 131.529 30.773 36.627 39.224 44.017 46.090 48.005 50.564 53.194 57.074 60.688 67.785 70.958 85.854 96.244 111.029 124.940 142.352 149.850 177.259 233.736 238.466
0.716 0.805 1.102 1.236 3.694 6.687 7.354 8.023 8.950 9.582 11.041 12.403 16.137 19.635 22.911 25.970 29.795 33.409 37.462 40.779 45.724
STD13
1-14
Samsung ASIC
Timings
1.5.2 TIMING PARAMETERS This section defines discusses timing parameters. 1.5.2.1 Rise Fall Transition Time Rise time, fall time, defined time that waveform takes transition between supply voltage (Figure 1-5). Figure 1-5. Rise Fall Transition Time
1.5.2.2
Propagation Delay
Propagation delay, defined time from when input waveform reaches supply voltage time that output waveform reaches supply voltage (Figure 1-6). Figure 1-6. Propagation Delay
tPLH
tPHL
tPLH
tPHL
Samsung ASIC
1-15
STD13
Timings
1.5.2.3
Setup Hold Time
Setup time, tSU, defined minimum time that data signal must stable before active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Hold time, tHD, defined minimum time that data signal must remain valid after active clock transition. change data signal within this time results timing violation, result invalid data being clocked into circuit (Figure 1-7). Figure 1-7. Setup Hold Time
1.5.2.4 Recovery Time Recovery time, tRC, defined time between release asynchronous control signal from active state circuit next active clock edge (Figure 1-8). active clock edge occurs soon after release control signal, violation occurs that result erroneous value being clocked circuit. Figure 1-8. Recovery Time
STD13
1-16
Samsung ASIC
Timings
1.5.2.5
Removal Time
Removal time, tRM, defined minimum time between active clock edge release asynchronous control signal from active state (Figure 19). control signal released from active state soon after active clock edge, violation occurs that result erroneous value being clocked into circuit. Figure 1-9. Removal Time
1.5.2.6 Minimum Pulse Width Minimum pulse width, tPW, defined minimum time allowed high phase signal measured time between rising falling edges reaching supply voltage (Figure 1-10). short pulse width results timing violation result signal being recognized circuitry. Figure 1-10. Minimum Pulse Width
1.5.2.7 Minimum Period Minimum period, tPRD, defined minimum allowable time complete cycle signal (Figure 1-11). short period results timing violation result signal being recognized circuitry. Figure 1-11. Minimum Period
Samsung ASIC
1-17
STD13
Timings
1.5.3 BEST WORST CASE CONDITIONS following expressions also allow effect process variation circuit performance. Best case (Worst case): (TWC) TNOM where, (TWC) darted timing, process derating factor, temperature derating factor, voltage derating factor, TNOM nominal timing best worst case darted timings determined picking proper values derating factors (Table 1-3, Table Table 1-5). Nominal timing defined timing under conditions nominal process, 25°C junction temperature, 1.8V power supply voltage. Derating factors conditions between those shown tables determined linear interpolation. 1.5.4 DERATING FACTORS STD131 multipliers applied nominal delay data order estimate effects supply voltage (VDD), junction temperature (TJ), process. Nominal data provided conditions 1.8V, 25°C typical process. junction temperature, calculated using chip power dissipation thermal resistance package ambient temperature, (also Section. 1.9.5). Information package thermal performance obtained from your local Samsung Technology Center Samsung's worldwide headquarters. derating factors STD131 follows Tables 1-3, 1-4, 1-5. Table 1-3. STD131 Cell Process Derating Factor (KP) Slow 1.248 1.000 Fast 0.806
Process Factor (KP) Table 1-4. Temp. Table 1-5. Voltage (oC)
STD131 Cell Temperature Derating Factor (KT) 1.131 1.080 1.060 1.000 0.965 0.908
STD131 Cell Voltage Derating Factor (KV) 1.65 1.085 1.000 1.95 0.935
STD13
1-18
Samsung ASIC
1.5.5
DELAY MODEL
STD131 cell timing characteristics consist following components: Cell propagation delay from input output transitions based input waveform slope, fanout distributed interconnection wire resistances capacitances. Interconnection wire delay. Timing requirement parameters including time, hold time, recovery time, skew time, minimum pulse width. Derating factors junction temperature, power supply voltage, process variation. accomplish accurateare timing model, dimensional table look-up delay model been developed. index variables this table input waveform slope output load capacitance (Figure 1-12). Samsung's design methodology supports n-dimensional table model, even though dimensional model used. Figure 1-12. 2-Dimensional Table Delay Model
Propagation Delay [ns] Input Waveform Slope [ns] Load [pF]
Table shows propagation delay data 2-input NAND cell. data this table high-to-low transition delay times from input pins output pin. number points values index variables differ each cell. Table 1-6.
SLOPE
Table Delay Model Example
0.009 0.03824 0.05706 0.07127 0.08766 0.10107 0.035 0.07474 0.09741 0.12242 0.15323 0.18256 0.156 0.24248 0.26404 0.29618 0.36274 0.43359 0.397 0.57593 0.59727 0.62763 0.69180 0.79434 0.760 1.07810 1.09940 1.12900 1.19040 1.28710 1.243 1.74630 1.76750 1.79680 1.85670 1.95000
0.015 0.147 0.323 0.674 1.200
Samsung ASIC
1-19
STD13
Notice that 5-by-6 table used. This general table delay model provides great flexibility well high accuracy since extensive software revisions required when cell library updated. other timing components, such interconnection wire delay, timing requirement parameters derating factors characterized commonly accepted industry. Figure 1-13 summarizes features STD131 library delay model. Figure 1-13. Features Delay Model
dimensional table delay model output loading input waveform slope used. rise fall times delay times cell instances calculated recursively. input waveform slope each primary input loading capacitance each primary output assigned individually default. delays cells interconnection wires defined. effect distributed interconnection wire resistances capactitances cell delay analysed using lumped capacitances.
STD13
1-20
Samsung ASIC
Design Test (DFT) Methodology
Design Test (DFT) Methodology
Samsung's libraries designed with mind. Samsung's methodology includes ability include full partial scan path testing, boundary-scan JTAG board level testing, Memory BIST, analog testing. brief description features Samsung's scan, BIST, JTAG well more detailed discussion boundary scan architecture follows. 1.6.1 SCAN DESIGN Multiplexed scan flip-flops that minimize area delay overhead needed implement scan design. Automated design rule checking, scan insertion, test pattern generation High fault coverage synchronous designs
1.6.2 BIST (BUILT-IN SELF-TEST) Efficient test solution compiled memory macrocells speed parallel testing multiple memories Combination with internal scan design core testing
1.6.3 BOUNDARY SCAN IEEE 1149.1 JTAG boundary scan registers implemented with primitive cells Boundary Scan Description Language (BSDL) board testing combed with internal scan design core testing
JTAG Boundary Scan Architecture Boundary scan architecture contains (Test Access Port), controller, instruction register, group test data registers. instruction test data registers separate shift-register-based paths connected parallel with common serial data input common serial data output. common serial data input output connected TAP, signals. controller selects alternative instruction test data register paths between TDO. schematic view level design JTAG test logic architecture shown Figure 1-14.
Samsung ASIC
STD13
Design Test (DFT) Methodology
Figure 1-14. JTAG Test Access Port (TAP) Block Diagram
Scannable Register Device Identity Register Instruction Register Controller Bypass Register TEST ACCESS PORT (TAP)
SYSTEM LOGIC
Multiplexer
Boundary Scan Path
Functional Block Descriptions (Test Access Port) general-purpose port that provides access many test support functions built into component including test logic. includes three inputs (TCK -Test Clock Signal; -Test Mode Signal; -Test Data Input) output (TDO -Test Data Output) required test logic. optional fourth input (TRSTN Test Reset) provided asynchronous initialization test logic. values applied pins sampled rising edge TCK, value placed changes falling edge TCK. Controller controller receives TCK, interprets signals TMS, generates clock control signals both instruction test data registers other parts test circuit required. Instruction Register/Instruction Decoder Test instructions shifted into held instruction register. Test instructions include tests performed test data register addresses accessed. basic 3-bit instruction register instruction decoder provided macrofunctions library. Test Data Registers Test data registers include bypass register, boundary scan register, device identification register other design specific registers. Only bypass boundary scan registers mandatory; rest optional.
STD13
1-22
Samsung ASIC
Design Test (DFT) Methodology
Test Data Registers Description Bypass register: bypass register provides single-bit serial connection through circuit when none other test data registers selected. used allow test data flow through given device other components product without affecting normal operation. Boundary scan register: boundary scan register detects typical production defects board interconnects, such opens, shorts. also allows access component inputs outputs when testing their logic sample flow-through signals. Special boundary scan register macrocells provided this purpose. Design-specific test data register: These optional registers provided allow access designspecific test support features integrated circuit, such self-test scan test. Device identification register: This optional test data register that allows manufacturer part number revision identified. 32-bit identification register partitioned into four fields:
Device version identifier field Device part number Manufacturer's JEDEC number
first four bits beginning from field bits field bits field tied High
ASIC designer free fill version part number manner long twenty bits used. Samsung's JEDEC code: decimal 1001110 Continuation field bits) 0000 Contents device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 Users define these fields.
Samsung ASIC
1-23
STD13
Maximum Fanouts
Maximum Fanouts
1.7.1 INTERNAL MACROCELLS maximum fanouts STD131 primitive cells tabulated Table Appendix Note that these fanout limitation values calculated when rise fall times input signal 0.147ns. Depending rise fall times, maximum fanout limitations varied case case. following table maximum fanout values pins STD131 internal macrocells listed. Table 1-7. Maximum Fanouts Internal Macrocells (When input tR/tF 0.147ns, fanout (SL) 0.00866pF, wire load 0.048pF, 0.048pF correspondent with 300µm wire) Cell Output Maximum Name Fanouts
ad2b ad2bd2 ad2bd4 ad2bd8 ad2d2 ad2d4 ad2d8 ad3d2 ad3d4 ad4d2 ad4d4 ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d4 ao21d2 ao21d4 ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2 ao222d4 ao22a ao22d2 ao22d4
Cell Name
ao31 ao311 ao3111 ao31d2 ao31d4 ao32 ao321 ao322 ao32d2 ao33 ao331 ao332 busholder dl1d2 dl2d2 dl5d2 dl10d2 fad2 fd1d2 fd1cs fd1csd2 fd1q fd1qd2 fd1s fd1sd2 fd1sq fd1sqd2 fd2d2 fd2cs fd2csd2 fd2q fd2qd2 fd2s fd2sd2 fd2sq fd2sqd2 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s
Output
Maximum Fanouts
10000
STD13
1-24
Samsung ASIC
Maximum Fanouts
Cell Name
fd3sd2 fd3sq fd3sqd2 fd4d2 fd4cs fd4csd2 fd4q fd4qd2 fd4s fd4sd2 fd4sq fd4sqd2 fd5d2 fd5s fd5sd2 fd6d2 fd6s fd6sd2 fd7d2 fd7s fd7sd2 fd8d2 fd8s fd8sd2 fds2 fds2d2 fds2cs fds2csd2 fds2s fds2sd2
Output
Maximum Fanouts
Cell Name
fds3 fds3d2 fds3cs fds3csd2 fds3s fds3sd2 fj2d2 fj2s fj2sd2 fj4d2 fj4s fj4sd2 ft2d2 had2 ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 ivd24 ivtd2 ivtd4 ivtd8 ivtd16 ld1d2 ld1q ld1qd2 ld2d2 ld2q ld2qd2 ld3d2
Output
Maximum Fanouts
1355
Samsung ASIC
1-25
STD13
Maximum Fanouts
Cell Name
ld4d2 ld5d2 ld5q ld5qd2 ld6d2 ld6q ld6qd2 mx2d2 mx2d4 mx2i mx2ia mx2id2 mx2id2a mx2id4 mx2id4a mx4d2 mx4d4 mx8d2 mx8d4 nd2b nd2bd2 nd2bd4 nd2bd8 nd2d2 nd2d4 nd2d8 nd3b nd3bd2 nd3bd4 nd3bd8 nd3d2 nd3d4 nd3d8 nd4d2 nd4d4 nd5d2 nd5d4 nd6d2 nd6d4 nd8d2 nd8d4 nid16 nid2 nid3 nid4 nid6
Output
Maximum Fanouts
Cell Name
nid8 nid24 nitd16 nitd2 nitd4 nitd8 nr2a nr2b nr2bd2 nr2bd4 nr2bd8 nr2d2 nr2d4 nr2d8 nr3a nr3d2 nr3d4 nr4d2 nr4d4 nr5d2 nr5d4 nr6d2 nr6d4 nr8d2 nr8d4 oa21 oa211 oa2111 oa2111d2 oa211d2 oa211d4 oa21d2 oa21d4 oa22 oa221 oa221d2 oa221d4 oa222 oa2222 oa2222d2 oa2222d4 oa222d2 oa222d4 oa22a oa22d2 oa22d2a oa22d4 oa22d4a oa31 oa311 oa3111 oa31d2 oa31d4 oa32 oa321 oa322 oa33
Output
Maximum Fanouts
1329
STD13
1-26
Samsung ASIC
Maximum Fanouts
Cell Name
or2b or2bd2 or2bd4 or2bd8 or2d2 or2d4 or2d8 or3d2 or3d4 or4d2 or4d4 or5d2 or5d4 scg1 scg1d2 scg2 scg2d2 scg2d4 scg3 scg3d2 scg3d4 scg4 scg4d2 scg4d4 scg5 scg5d2 scg5d4 scg6 scg6d2 scg7 scg7d2 scg8 scg8d2 scg9 scg9d2 scg10 scg10d2 scg11 scg11d2 scg12 scg12d2 scg12d4 scg13 scg13d2 scg14 scg14d2 scg15 scg15d2 scg16 scg16d2 scg17 scg17d2 scg18 scg18d2 scg19 scg19d2 scg20 scg20d2 scg21 scg21d2 scg22 scg22d2
Output
Maximum Fanouts
Cell Name
xn2d2 xn2d4 xn3d2 xn3d4 xo2d2 xo2d4 xo3d2 xo3d4
Output
Maximum Fanouts
Samsung ASIC
1-27
STD13
Maximum Fanouts
1.7.2 Cells maximum fanouts cells follows.
Cell Name
picc_abb picd picd_abb picen_abb picu picu_abb pis_abb pisd pisd_abb pisu pisu_abb pmic pmic_abb pmicc_abb pmicd pmicd_abb pmicen_abb pmicu pmicu_abb pmis pmis_abb pmisd pmisd_abb pmisu pmisu_abb pmsckdc2 pmsckdc4 pmsckdc6 pmsckdc8 pmsckdcd2 pmsckdcd4 pmsckdcd6 pmsckdcd8 pmsckdcu2 pmsckdcu4 pmsckdcu6 pmsckdcu8 pmsckds2 pmsckds4 pmsckds6 pmsckds8 pmsckdsd2 pmsckdsd4 pmsckdsd6 pmsckdsd8 pmsckdsu2 pmsckdsu4 pmsckdsu6 pmsckdsu8 pmsosck1 pmsosck2 pmsoscm1 pmsoscm2 pmtic pmticd pmticu pmtis pmtisd pmtisu psckdc2 psckdc4 psckdc6 psckdc8 psckdcd2 psckdcd4 psckdcd6 psckdcd8
Output
Maximum Fanouts
1107 1443 1107 1442 1107 1442 1107 1443 1107 1442 1107 1443 1115 1466 1113 1460
Table 1-8. Maximum Fanouts Cells (When input tR/tF 0.147ns, fanout (SL) 0.00866pF) Cell Output Maximum Name Fanouts
phic phic_abb phicc_abb phicd phicd_abb phicen_abb phicu phicu_abb phis phis_abb phisd phisd_abb phisu phisu_abb phsckdc2 phsckdc4 phsckdc6 phsckdc8 phsckdcd2 phsckdcd4 phsckdcd6 phsckdcd8 phsckdcu2 phsckdcu4 phsckdcu6 phsckdcu8 phsckds2 phsckds4 phsckds6 phsckds8 phsckdsd2 phsckdsd4 phsckdsd6 phsckdsd8 phsckdsu2 phsckdsu4 phsckdsu6 phsckdsu8 phtic phticd phticu phtis phtisd phtisu phsosck1 phsosck17 phsosck2 phsosck27 phsoscm1 phsoscm16 phsoscm2 phsoscm26 phsoscm3 phsoscm36 pic_abb 1127 1487 1127 1487 1127 1487 1127 14876 1127 1487 1127 1487
STD13
1-28
Samsung ASIC
Maximum Fanouts
Cell Name
psckdcu2 psckdcu4 psckdcu6 psckdcu8 psckds2 psckds4 psckds6 psckds8 psckdsd2 psckdsd4 psckdsd6 psckdsd8 psckdsu2 psckdsu4 psckdsu6 psckdsu8 psosck1 psosck2 psoscm1 psoscm2 ptic pticd pticu ptis ptisd ptisu
Output
Maximum Fanouts
1116 1464 1043 1321 1039 1317 1042 1318
Samsung ASIC
1-29
STD13
Maximum Fanouts
Maximum Fanouts
<Condition> Library STD131 1.8V Fanout 0.00958pF input FD1) Standard Load (SL) 0.00866pF Input slope 0147ns Maximum output transition time (mott) 1.2ns Maximum frequency 300MHz length (µm/fanout): branch length each fanout except trunk
Trunk width (µm) length (µm/fanout) Trunk length (µm)
2000 5000 2000 5000
case that interconnection considered 1151 1534
Trunk width (µm) length (µm/fanout) Trunk length (µm) nid2 nid3 nid4 nid6 nid8 nid16 nid24
0.28 2000 5000 2000
5000
case that interconnection considered 1329
high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis.
STD13
1-30
Samsung ASIC
Package Capability Pitch Lead Count
PACKAGE CAPABILITY PITCH LEAD COUNT
Appendix Samsung's package capability this writing. most current package availability capability obtained from your local Samsung Technology Design Centers.
Samsung ASIC
STD13
Power Dissipation
Power Dissipation
1.9.1 ESTIMATION POWER DISSIPATION CMOS CIRCUIT primary advantage CMOS circuits power consumption since they draw very small amount current under steady state, conditions. However, circuit densities clock rates increase, power dissipation CMOS circuits becomes substantial. Power dissipation CMOS circuits affected various factors such number gates, switching frequency, gate output loading. Circuit operating temperature important factor determining circuit speed reliability. Circuit power dissipation major factor determining circuit operating temperature. Designers must estimate power dissipation circuit accurately choose appropriate package system operating conditions circuit insure best performance reliability. following sections describe components power dissipation CMOS circuit (static dynamic), method calculating them Samsung STD131 library elements. 1.9.2 STATIC (DC) POWER DISSIPATION types static current contribute total static power dissipation CMOS circuits leakage current input/output current. Leakage current results from reverse bias between well substrate region CMOS circuit. Since there current path from power ground through CMOS logic gate steady state, static current except leakage current flows through internal circuitry CMOS device. amount this leakage current normally order tens nano amperes negligible. Input/output current flows through buffers when circuit interfaced with other devices, especially TTL. current pull-up/pull-down transistor input buffers typically order tens micro amperes 3.3V, 25µA 2.5V, 18µA 1.8V), which also negligible. Therefore, only current that output buffers source sink needs counted estimate total static power dissipation. power dissipation output bi-directional buffers determined following formula:
PDC_OUTPUT [mW] VOL(k) IOL(k) tL(k) VOH(k) IOH(k) tH(k) PDC_BI [mW] VOL(k) IOL(k) IOH(k) tH(k) Sout
where, Number output bi-directional buffers Total operation time output mode logic high state time logic state time (assuming that output bi-directional buffers tri-state) Sout output mode ratio bi-directional buffers. (typically 0.5)
STD13
1-32
Samsung ASIC
Power Dissipation
1.9.3 DYNAMIC (AC) POWER DISSIPATION When CMOS logic gate changes state, draws switching current result charging discharging load capacitance, power associated with switching current node capacitance,
where power supply voltage. addition power dissipated changing load capacitance, CMOS circuits consume power current flowing from power supply ground through p-channel transistors during switching. dynamic power dissipation entire chip difficult estimate since depends switching activity circuit. Samsung found that switching activity about average recommends using this number estimating total dynamic power dissipation. 1.9.4 POWER DISSIPATION STD131 This section describes equations used estimate power dissipation STD131. explained previous section, total power dissipation (PTOTAL) consists static power dissipation (PDC) dynamic power dissipation (PAC). Samsung's internal power estimation tool, CubicPower, uses methodology based following equations. PTOTAL negligible case CMOS logic general. dynamic power dissipation caused four components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bi-directional buffers (PAC_BI), internal cells (PAC_INTERNAL). PAC_ INPUT PAC_OUTPUT PAC_BI PAC_INTERNAL
Samsung ASIC
1-33
STD13
Power Dissipation
Each term mentioned above characterized following equations:
N_1.8V_input
PAC_INPUT [mW]
N_3.3V_input
N_2.5V_input Ij_eq_p i_eq_p
N_total_input (0.001 Cl_inload) k_eq_p 3.24
N_1.8V_output
PAC_OUTPUT [mW] 6.25
N_3.3V_output
N_2.5V_output i_eq_p j_eq_p N_1.8V_output 3.24 0.001 Ci_outload k_eq_p N_3.3V_output
N_2.5V_output
0.001 Cj_outload 10.89
0.001 Ck_outload
PAC_BI [mW] PAC_BI_INPUT Sout PAC_BI_OUTPUT Sout
N_1.8V_bi
PAC_BI_INPUT [mW]
N_3.3V_bi
N_2.5V_bi j_eq_p i_eq_p
N_total_bi 3.24 0.001 Cl_inload k_eq_p N_1.8V_bi
PAC_BI_OUTPUT [mW] 6.25
N_3.3V_bi
N_2.5V_bi j_eq_p i_eq_p
N_2.5V_bi
3.24 k_eq_p
N_1.8V_bi
0.001 Ci_outload
N_3.3V_bi
0.001 Cj_outload 10.89
N_macro
0.001 Ck_outload
PAC_INTERNAL [mW] 0.001 0.1506 0.0198
0.001
where, N_1.8V_input number 1.8V interface input buffers used, N_2.5V_input number 2.5V interface input buffers used, N_3.3V_input number 3.3V interface input buffers used, N_total_input N_1.8V_input N_2.5V_input N_3.3V_input, N_1.8V_output number 1.8V interface output buffers used, N_2.5V_output number 2.5V interface output buffers used, N_3.3V_output number 3.3V interface output buffers used, N_1.8V_bi number 1.8V interface bi-directional buffers used, N_2.5V_bi number 2.5V interface bi-directional buffers used, N_3.3V_bi number 3.3V interface bi-directional buffer used, N_total_bi N_1.8V_bi N_2.5V_bi N_3.3V_bi, N_macro number macro cells used, total gate count design, operating frequency MHz, estimated switching activity (typically internal logic I/O), Sout output mode ratio bi-directional buffers (typically 0.5), load capacitance characterized power i-th hard macro block. (µW/MHz)
STD13
1-34
Samsung ASIC
Power Dissipation
1.9.5 TEMPERATURE POWER DISSIPATION total power dissipation, PTOTAL used find device temperature following equation: PTOTAL where,
package thermal impedance,
junction temperature device, ambient temperature.
Thermal impedances Samsung packages given following table. junction temperature, determines derating factor propagation delays also used reliability calculations. Hence, designers achieve desired derating factor reliability targets choosing appropriate packages system cooling methods. Table 1-11. Number Thermal Impedances Samsung Plastic Packages SOP/TSOP 41-44 46-56 44-71 Number 39-59 34-56 27-33 34-46
JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W] JA[°C/W]
51-62
43-56
43-74
27-6
33-47
43-5
29-5
22-43
28-47
29-42
TQFP/LQFP Number 68-70 37-70 35-62 PBGA Number 19-22 16-19 SBGA Number 14.1 13.1 11.7 10.2 (TEPBGA) (TEPBGA) 31-34 37-56 30-42
Samsung ASIC
1-35
STD13
1.10
VDD/VSS Rules Guidelines
1.10 VDD/VSS Rules Guidelines
Three kinds power supplies exist STD131 providing power internal areas: Core logic VDD1I, VSS1I Pre-driver (I/O area) VDD3P, VDD2P, VDD1P, VSS3P, VSS2P, VSS1P Output-drive (I/O area) VDD3O, VDD2O, VDD1O, VSS3O, VSS2O, VSS1O
number pads required specific design depends following factors: Number input output buffers Number simultaneous switching outputs Number used gates simultaneous switching gates Operating frequency
1.10.1 BASIC PLACEMENT GUIDELINES purpose these guidelines minimize drop noise reliable device operations. Core logic pre-driver VDD/VSS pads should evenly distributed sides chip. have core block demanding high power (compiled memory, analog), extra power pads should used supply that block. Power pads group should evenly distributed group. place quiet signal (analog, reference), analog power (VDDA/ VSSA), bi-directional buffer next group. Opposite types power pads (VDD/VSS) should placed close together possible. possible, place power pads (VDD/VSS) corner chip.
1.10.2 VDD1I/VSS1I ALLOCATION GUIDELINES purpose these guidelines ensure that minimum number core logic power pairs used while meeting electromigration rules. number VDD1I/VSS1I pads required specific design function operating frequency chip. VDD1I width number pads equal those VSS1I VDD1I/VSS1I buses pads should distributed evenly core each side chip.
STD13
1-36
Samsung ASIC
1.10
VDD/VSS Rules Guidelines
number VDD1I/VSS1I pairs required design calculated from following expression: number VDD1I/VSS1I pairs 0.001 0.0837 0.011
N_macro
round
where, core (excluding hard macro blocks) size gate counts, switching ratio (typically 0.1), Operating frequency (MHz), Characterized current i-th hard macro block (mA/MHz), Operating frequency i-th hard macro block (MHz), Current limit VDD/VSS pairs based electromigration rule. (40mA) reliable device operation minimize drop, device should have fewer than VDD1I/VSS1I power pairs. Extra power pairs needed high power consuming macro blocks (SRAM, analog blocks, etc.). 1.10.3 VDD1P/VSS1P (VDD2P, 3P/VSS2P, ALLOCATION GUIDELINES. These guidelines ensure that adequate input threshold voltage margin maintained during switching. number VDD1P/VSS1P, VDD2P/VSS2P, VDD3P/VSS3P pads required design calculated from following expression: leq_p Number_ of_VDD1P/VSS1P(VDD2P, 3P/VSS2P, pairs round above expression, Ieq_p (Average current input/output buffers bi-direction pre-drivers maximum operational frequency) [mA] (Refer Table 1-12, Table 1-13 Table 1-14)
N_input
Ieq_p
N_output N_bi j_eq_p_out Ik_eq_p_in Sout Ik_eq_p_out Sout eq_p_in
where, N_input number input buffers used, N_output number output buffers used, N_bi number bi-directional buffers used, operating frequency MHz, Sout output mode ratio bi-directional buffers, (typically 0.5). Current limit VDD/VSS pairs based electromigration rules. (40mA)
Samsung ASIC
1-37
STD13
1.10
VDD/VSS Rules Guidelines
Table 1-12. 1.8V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.25 (mA) Tolerant 0.25 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.13 0.27 0.37 (mA) Slew-rate 0.13 0.25 0.33 Table 1-13. 2.5V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.27 (mA) Tolerant 0.27 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.27 0.60 0.84 (mA) Slew-rate 0.29 0.55 0.72 Table 1-14. 3.3V Interface Input Buffer Type CMOS Ieq_p_in Normal 0.32 (mA) Tolerant 0.31 Output Pre-Driver CMOS Driver Type B1-4 B8-16 B20-24 Ieq_p_out Normal 0.32 0.57 0.77 (mA) Slew-rate 0.30 0.57 0.75
T1-4 0.18 0.17
Schmitt Trigger 0.26 0.26 Tristate T8-16 T20-24 0.30 0.41 0.34 0.42
Tolerant 0.20 0.24
T1-4 0.28 0.29
Schmitt Trigger 0.30 0.32 Tristate T8-16 T20-24 0.67 0.77 0.61
Tolerant 0.39 0.42
T1-4 0.34
Schmitt Trigger 0.38 0.34 Tristate T8-16 T20-24 0.59 0.79 0.58 0.76
Tolerant 0.35 0.43
reliable device operation minimum voltage drop, least pairs VDD1P/VSS1P (VDD2P, 3P/VSS2P, power pads should used. 1.10.4 VDD1O/VSS1O (VDD2O, 3O/VSS2O, ALLOCATION GUIDE (Simultaneous Switching Output) current induced power ground wire inductances cause system failure because voltage spikes during switching. calculate number output drive power pads, noise well current limit based electromigration taken into consideration. defined number outputs switching simultaneously windows, such type buffers.
NOTE: case heavy loads, high frequency, package inductance, number power pads block could determined electromigration rule rather than noise limit. number power pads block should determined worst case power number determined noise electromigration rules.
Number power pads block Number power pads block under limit noise Calculating number power each group from following expressions: number_of_SSO NVDDOeach_SSO -NBvdd DSSO_mode number_of_SSO NVSSOeach_SSO -NBvss DSSO_mode
STD13
1-38
Samsung ASIC
1.10
VDD/VSS Rules Guidelines
where, NVDDOeach_sso Number VDD1O (VDD2O, required each group, NVSSOeach_sso Number VSS1O (VSS2O, required each group, NBvdd Number buffers VDD1O (VDD2O, power with lead inductance (Refer Table 1-18), NBvss Number buffers VSS1O (VSS2O, ground with lead inductance, Package lead frame inductance power/ground (Refer package capability pitch lead count), Dsso_mode DL_mode DP_mode DV_mode DT_mode DC_mode (Refer Table 1-15, Table 1-16 Table 1-17) DL_mode Lead inductance derating factor DP_mode Process derating factor DV_mode Voltage derating factor DT_mode Temperature derating factor DC_mode Cload derating factor (mode either VSS) Table 1-15. Item
Package Lead
Derating Equation (External 1.8V Interface) Equation Mode 1-8mA
DL_vdd DL_vss 0.1188 0.6931 0.0099 1.7822 0.2069 0.4598 0.0115 2.4138 1.0000 1.2574 1.8217 1.0000 1.2184 1.4483 1.5182 voltage 3.8910 1.0561 voltage 3.0594 0.9962 voltage 2.9080 0.7663 voltage 2.4943 0.00039 temp 1.0000 0.00018 temp 1.0054 0.0028 temp 1.0000 0.0029 temp 0.9958 0.0337 cload 0.6634 0.0153 cload 1.2129 0.0328 cload 0.6724 0.0155 cload 1.1896
12-24mA
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst 1.65 voltage voltage 1.95 1.65 voltage voltage 1.95 temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
0.0800 0.8000 0.0400 1.2000 0.1200 0.4000 0.0400 1.2000 1.0000 1.0800 1.3200 1.0000 1.0400 1.0800 0.8000 voltage 2.4800 0.2667 voltage 1.5200 0.2898 voltage 1.5652 0.2898 voltage 1.5652 0.00167 temp 1.0000 0.00076 temp 1.02273 0.0016 temp 1.0000 0.00145 temp 1.0036 0.0200 cload 0.8000 0.0040 cload 1.2800 0.0120 cload 0.8800 0.0020 cload 1.1800
Samsung ASIC
1-39
STD13
1.10
VDD/VSS Rules Guidelines
Table 1-16. Item
Package Lead
Derating Equation (External 2.5V Interface) Equation Mode 1-8mA
DL_vdd DL_vss 0.0123 1.9753 0.0247 1.8518 0.0430 1.5054 0.0323 1.6129 1.0000 1.6419 2.0778 1.0000 1.1613 1.7742 1.2962 voltage 4.4012 0.8025 voltage 3.1667 1.1828 voltage 4.1075 0.7527 voltage 3.0323 0.000988 temp 1.0000 0.000455 temp 1.0135 0.00258 temp 1.0000 0.00254 temp 1.00097 0.0370 cload 0.6296 0.0154 cload 1.2778 0.0328 cload 0.6720 0.0199 cload 1.059
12-24mA
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
0.1250 0.8333 0.0833 1.2500 0.0769 0.7692 0.0385 1.1538 1.0000 1.2083 1.3750 1.0000 1.0000 1.1154 0.2083 voltage 1.6042 0.4167 voltage 2.1250 0.1923 voltage 1.5577 0.3846 voltage 2.0385 0.001667 temp 1.0000 0.000758 temp 1.0227 0.00154 temp 1.0000 0.00209 temp 0.9860 0.0125 cload 0.8750 0.0021 cload 1.1875 0.0115 cload 0.8846 0.0019 cload 1.1730
Table 1-17. Item
Package Lead
Derating Equation (External 3.3V Interface) Equation Mode 1-8mA
DL_vdd DL_vss 0.0320 1.6800 0.0320 1.6800 0.0609 1.4634 0.0244 1.8293 1.0000 1.4720 1.7520 1.0000 1.1097 1.4390 1.4400 voltage 3.7280 0.9066 voltage 2.7679 0.5285 voltage 2.8536 0.3658 voltage 2.3170 0.00096 temp 1.0000 0.00058 temp 1.0095 0.00146 temp 1.0000 0.00155 temp 0.9978 0.0236 cload 0.7640 0.0264 cload 0.6800 0.0207 cload 0.7927 0.0177 cload 0.884
12-24mA
Range
10nH 10nH 15nH 10nH 10nH 15nH best typical worst best typical worst voltage voltage voltage voltage temp temp temp temp 10pF cload 30pF 30pF cload 50pF 10pF cload 30pF 30pF cload 50pF
Process
DP_vdd
DP_vss
Voltage
DV_vdd DV_vss
Temperature
DT_vdd DT_vss
Cload
DC_vdd DC_vss
0.0857 1.1429 0.1143 0.8571 0.0909 0.9091 0.0455 1.3636 1.0000 1.2000 1.3428 1.0000 1.0000 1.1304 0.2857 voltage 2.0000 0.1905 voltage 1.6857 0.1515 voltage 1.5909 0.3030 voltage +2.0909 0.00114 temp 1.0000 0.00156 temp 0.9896 0.00364 temp 1.0000 0.00165 temp 1.0496 0.0257 cload 0.7429 0.0043 cload 1.3857 0.01136 cload 0.8864 0.00227 cload 1.159
STD13
1-40
Samsung ASIC
1.10
VDD/VSS Rules Guidelines
Table 1-18.
NBvdd/NBvss Parameter (Process best, Volt 1.95V/2.7V/3.6V, Temp 0°C, Llead 1nH) Slew-Rate Medium Slew-Rate High Normal (sm) (sh) Buffer Type Voltage Type NBvdd NBvss NBvdd NBvss NBvdd NBvss pob1 (pot1) pob2 (pot2) pob4 (pot4) pob8 (pot8) Interface pob12 (pot12) pob16 (pot16) pob20 (pot20) pob24 (pot24) ptot1 3.3V Tolerant ptot2 ptot4 1.8V Interface ptot6 pmob1 (pmot1) pmob2 (pmot2) pmob4 (pmot4) pmob8 (pmot8) 2.5V Interface pmob12 (pmot12) pmob16 (pmot16) pmob20 (pmot20) pmob24 (pmot24) pmtot1 pmtot2 Tolerant 2.5V Interface pmtot4 pmtot6 phob1 (phot1) phob2 (phot2) phob4 (phot4) 3.3V Interface phob8 (phot8) phob12 (phot12) phob16 (phot16) phob20 (phot20) phob24 (phot24) phtot1 phtot2 Tolerant 3.3V Interface phtot4 phtot6
NOTE: pob1 means output driver cell, pob12 means 12mA output driver cell.
Calculating number required power total from following expression: NVDDO1sso NVDDOeach_sso NVSSO1sso NVSSOeach_sso
When there blocks which switching simultaneously with others, only maximum value NVDDO_each_sso/NVSSO_each_sso among block should used.
Samsung ASIC
STD13
1.10
VDD/VSS Rules Guidelines
above formula, NVDDOsso Number VDD1O (VDD2O, total buffers NVSSOsso Number VSS1O (VSS2O, total buffers Number power pads block limit electromigration rules: Calculating following expression: NVDDO2SSO NVSSO2SSO -Iem
N_SSO_output
Ieq_o
N_SSO_bi
Ieq_o
0.001 Ci_outload
0.001 j_outload j_out
where, N_SSO_output number simultaneous switching output buffers used, N_SSO_bi number simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF], Operating voltage [V], Maximum operating frequency [MHz], Switching ratio (typically 0.5), Sout Output mode ratio bi-directional buffers, (typically 0.5). Current limit VDD/VSS pairs based electromigration rule. (40mA) Number power pads non-SSO block Calculating following expression: NVDDOnon_SSO NVSSOnon_SSO -Iem
N_non_SSO_output
Ieq_o
N_non_SSO_bi
Ieq_o
0.001 Ci_outload
0.001 j_outload j_out
where, N_non_SSO_output number non-simultaneous switching output buffers used, N_non_SSO_bi number non-simultaneous switching bi-directional buffers used, Coutload Output load capacitance [pF], Operating voltage [V], Maximum operating frequency [MHz], Switching ratio (typically 0.5), Sout Output mode ratio bi-directional buffers, (typically 0.5). Current limit VDD/VSS pairs based electromigration rule. (40mA) Total number power pads VDD1O/VSS1O (VDD2O, 3O/VSS2O, Calculating following expressions:
Number VDD1O (VDD2O, NVDDO1SSO, NVDDO2SSO NVDDOnon_SSO round-up Number VSS1O (VSS2O, NVSSO1SSO, NVSSO2SSO NVSSOnon_SSO round-up
When open drain type buffers used, consider using VSS1O (VSS2O, pads since they have current sink only.
STD13
1-42
Samsung ASIC
Crystal Oscillator Consideration
1.11 Crystal Oscillator Consideration
1.11.1 OVERVIEW STD131 library contains cell commonly referred on-chip oscillator. on-chip oscillator itself really oscillator, amplifier suitable being used feedback amplifier oscillator circuit. With proper selection off-chip components (crystal ceramic resonator, resistors capacitors) this oscillator circuit performs better than other types clock oscillators. very important select suitable off-chip components on-chip oscillator circuitry. should noted, however, that Samsung cannot assume responsibility writing specifications off-chip components performance finished oscillator design production since optimization crystal oscillator circuit will specific given application. Samsung does, however, spec guarantee performance on-chip oscillator cell. 1.11.2 OSCILLATOR DESIGN CONSIDERATIONS designers have number options clocking system. primary decision whether on-chip oscillator external oscillator. choice on-chip oscillator, designer must then choose type oscillator off-chip component values. These decisions will based both economic technical requirements.The following section discusses some factors considered. 1.11.2.1 On-Chip Oscillator most cases, on-chip oscillator with appropriate external components provides most economical solution clocking problem. Exceptions arise server environments when frequency tolerances tighter than about 0.01%. external components commonly used oscillator circuit positive reactance (normal crystal oscillator), capacitors, resistors, shown figure below. Figure 1-15. CMOS Oscillator Inside Chip PADA
PADY
Feedback Amplifier
1.11.2.2 Crystal Specifications Specifications appropriate crystal very critical. fundamental mode crystal medium better quality used. Crystal resistance affects start-up time steady state amplitude compensated choice however, lower crystal resistance, better. discussion external components follows below.
Samsung ASIC
1-43
STD13
Crystal Oscillator Consideration
1.11.2.3 Oscillation Frequency oscillation frequency mainly determined crystal. on-chip oscillator little effect frequency. influence on-chip oscillator frequency results from input output (Pin-To-Ground) capacitances which parallel PADAto-PADY (Pin-To-Pin) capacitance which parallels crystal. input pinto-pin capacitances about each. 1.11.2.4 Selection Optimal values depend whether quartz crystal ceramic resonator being used, application-specific requirements start-up time frequency tolerance. Start-up time sometimes more critical microcontroller systems than frequency stability because various reset initialization requirements. Accuracy oscillator frequency less commonly critical, when oscillator being used time base. general rule, fast start-up stable frequency tend pull oscillator design opposite directions. Considerations both start-up time frequency stability over temperature suggest that should about equal least 15pF (but they don't have either). Increasing value these capacitors above 40pF 50pF improves frequency stability, also increases start-up time. capacitors large (several hundred pF), oscillator won't start all. 1.11.2.5 Selection large ohm) holds on-chip oscillator CMOS inverter) linear region allowing oscillate. inverter fairly output resistance which de-stabilizes oscillator circuit. several K-ohms added feedback network, shown Figure 1-15, stabilize oscillator circuit. higher oscillator frequencies, 20pF 30pF capacitor sometimes used place compensate internal propagation delay. 1.11.3 CONSIDERATIONS Noise glitches arising PADA PADY pins wrong time cause miscount internal clock-generating circuitry. These kinds glitches produced through capacitive coupling between oscillator components traces carrying digital signals with fast rise fall times. this reason, oscillator components should mounted close chip have short, direct traces PADA, PADY, pins. possible, dedicated pins on-chip oscillator. addition, surrounding oscillator components with "quiet" traces (VDD VSS) will alleviate capacitive coupling signals having fast edges. minimize inductive coupling, layout should minimize lead, wire, trace lengths oscillator components.
STD13
1-44
Samsung ASIC
Crystal Oscillator Consideration
Paths that need checked are: PADA through resonator PADY; PADA through pin; PADY through pin. unusual find that ground ends connect through long traces board. 1.11.4 TROUBLESHOOTING OSCILLATOR PROBLEMS cause oscillator problem difficult find once detected. Below some suggested first things investigate oscillator problem detected. There significant differences stray capacitances between test fixture actual application, particularly actual application multilayer board. This result oscillator problem occurring test fixture that will occur board, problem occurring board that cannot duplicated test fixture. Noise glitches present test fixture present application board another cause oscillator problem. Capacitive coupling between oscillator circuitry other signal should investigated. Inductive coupling also possible there lead, trace, wire with large current nearby. Finally, should overlooked that software problems mimic symptoms slow-starting oscillator incorrect frequency. Software should also invigilated.
Samsung ASIC
1-45
STD13

Library Description Features Support Product Family. 1.4.1 Analog Core

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