Digital-to-Analog Converter Appendix Digital-to-Analog Conve

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Digital-to-Analog Converter Appendix Digital-to-Analog Conve

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Glossary Analog Terms
Digital-to-Analog Converter
Appendix
Digital-to-Analog Converter
Resolution n-bit binary converter should able provide distinct different analog output values corresponding n-bit binary words. converter that satisfies this criterion said have resolution bits. smallest output change that resolved linear full-scale span. Accuracy Error difference between actual analog output output that expected when given digital code applied converter. Source error include gain error, offset error, linearity error noise. Error usually commensurate with resolution, less than 2-(n+1), 1/2LSB full scale. Figure 1-1.
Analog Output Actual Ideal Ideal Actual
Error
Analog Output
Gain Error
Offset Error Digital Input Digital Input
(Least-Significant Bit) system which numerical magnitude represented series binary digits, that that carries smallest value weight. represents smallest analog change that resolved n-bit converter. (Analog Value) FSR/2n Full-Scale Range, number bits (Most-Significant Bit) binary digit with largest numerical weighting. Normally, digital word weighting full range. Compliance-Voltage Range current output DAC, maximum range of(output) terminal voltage which device will provide specified currentoutput characteristics. Glitch glitch switching transient appearing output during code transition. value expressed product voltage current time duration charge transferred. Harmonic Distortion (and Total Harmonic Distortion) driven digitized representation sine wave. ratio harmonics output fundamental value THD. Usually only lower order harmonics included, such second through fifth.
20log
amplitude fundamental
STD130
Samsung ASIC
Appendix
Digital-to-Analog Converter
Signal-to-Noise Ratio (SNR) This signal noise ratio depends resolution converter automatically includes specifications linearity, distortion, sampling time uncertainty, glitches, noise, settling time. Over half sampling frequency, this signal noise ratio must specified should ideally follows theoretical formula; S/Nmax 6.02N 1.76dB Slew Rate Slew rate device circuit limitation rate change output voltage, usually imposed some basic circuit consideration such limited current charge capacitor. Amplifiers with slew rate V/µs common moderate cost. Slew rates greater than about 75V/µs usually seen only more sophisticated (and expensive) devices. output slewing speed voltage-output usually limited slew rate amplifier used output used). Settling Time time required, following prescribed data change from point login input change, output reach remain within given fraction (usually ±1/2LSB) final value. Typical prescribed changes full scale, 1MSB 1LSB major carry. Settling time current-output quite fast. major share settling time voltageoutput usually contributed settling time output op-amp circuit. Figure 1-2. Setting Time
Slew Rate Final Setting
Slewing Setting Time
Power-Supply Sensitivity -The sensitivity converter changes power-supply voltages normally expressed terms percent-of-full-scale change analog output value fractions 1LSB) change power supply. Power supply sensitivity also expressed relation specified shift supply voltage. converter considered "good" change reading full scale does exceed 1/2LSBfor change power supply. Even better specifications necessary converters designed battery operation. (Integral Linearity) Linearity error converter, expressed full-scale range multiples 1LSB, deviation analog values plot measured conversion relationship from straight line. straight line either "best straight line" determined empirically manipulation gain and/or offset equalize maximum positive negative deviation actual transfer characteristics from this straight line; straight line passing through endpoints transfer characteristic after they have been calibrated (sometimes referred "endpoint" linearity). Endpoint linearity error similar relative accuracy error. multiplying DAC, analog linearity error,
Samsung ASIC
STD130
Digital-to-Analog Converter
Appendix
specified digital code, defined same multipliers, deviation from "best straight line" through plot analog output-input response. (Differential Linearity) adjacent digital codes should result measured output values that exactly 1LSB apart full scale n-bit converter). deviation measured "step" from ideal difference called differential linearity error expressed multiplies 1LSB. important specification because differential linearity error greater than 1LSB lead non-monotonic response missed codes ADC. Monotonic said monotonic output either increases remains constant digital input increases with result that output will always single-valued function input. specification "monotonic" (over given temperature range) sometimes substituted differential nonlinearity specification since differential nonlinearity less than 1LSB sufficient condition monotonic behaviour. Analog-to-Digital Converter (Integral Linearity) Integral nonlinearity refers deviation each individual code from line drawn from "zero" through "full scale". point used "zero" occurs analog value 1/2LSB before first code transition. "Full scale" defined level 1/2LSB beyond last code transition. deviation measured from center each particular code true straight line. (Differential Linearity) ideal exhibits code transitions that exactly 1LSB apart. deviation from this ideal value. often specified terms resolution which missing codes guaranteed. Offset Error first transition should occur level "zero". Offset defined deviation actual first code transition from that point. Gain Error first code transition should occur analog value nominal negative full scale. last transition should occur analog value 1LSB below nominal positive full scale. Gain error deviation actual difference between first last code transitions ideal difference between first last code transitions. Pipeline Delay (Latency) number clock cycles between conversion initiation associated output data being made available. output data provided every clock cycle. Effective Number Bits (ENOB) This measure device's dynamic performance obtained from SNDR from sine wave curve test according following expression: ENOB SNDR 1.76/6.02 ENOB N-log2[RMS error (actual) error (ideal)] Analog Bandwidth analog input frequency which spectral power fundamental frequency, determined analysis reduced 3dB. Aperture Delay delay between sampling clock instant analog input signal sampled.
STD130
Samsung ASIC
Appendix
Digital-to-Analog Converter
Aperture Jitter sample sample variation aperture delay. Error Rate (BER) number spurious code errors produced given input sine wave frequency given clock frequency. this case number codes occurring outside histogram cusp sine wave. Signal Noise Ratio This signal noise ratio depends resolution converter automatically includes specifications linearity, distortion, sampling time uncertainty, glitches, noise, settling time. Over half sampling frequency, this signal noise ratio must specified should ideally follow theoretical formula; S/Nmax 6.02N 1.76dB
Phase Locked Loop Lock Time time takes lock onto system clock. Fast slow lock time controlled loop filter characteristics. loop filter characteristics controlled varying components. (Remember that define damping-factor well) Phase Error phase difference between feedback system clock signal. Clock Jitter deviations clock's output transitions from their ideal positions define clock jitter. Jitter sometimes specified absolute value nanoseconds. jitter measurement made specified voltage. Cycle-to-Cycle Jitter: change clock's output transition from corresponding position previous cycle. This kind jitter most difficult measure usually requires time-interval analyzer. Figure 1-3. Cycle-to-Cycle Jitter
Clock
Noise: jitter jitter maximum such values over multiple cycles (J1, J2.) max. cycle-tocycle jitter. Period Jitter: Period jitter measures maximum change clock's output transition from ideal position. period jitter measurements calculate timing margins systems.
Samsung ASIC
STD130
Digital-to-Analog Converter
Appendix
Figure 1-4.
Period Jitter
Ideal Cycle:
Clock Jitter
Long-Term Jitter: Long-term jitter measures maximum change clock's output transition from ideal position over many cycles. many cycles depend application frequency. classic example system affected long-term jitter graphics card driving CRT. Power Down Mode: state which quiescent current lowered very level conserve power. Synthesize Clock: system clock relatively rate compared system components. CPU, example, require internal clock that several times faster than system clock. Designers technology synthesize higher frequency on-chip clock using system clock reference. Deskew Clock: Multiple chips printed circuit board cores different sizes within single system chip experience clock skew. using technology shift phase reference clock within each chip core, designers minimize skew tune system perform potential. Duty Ratio: percentage period that output high state. Output Frequency Range: maximum output frequency range minus minimum output frequency that produced with input signal which cell specifications still apply.
STD130
Samsung ASIC

Digital-to-Analog Converter Appendix Digital-to-Analog Conve

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