8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Drive

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8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Drive

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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Drive LSTTL Loads Shift Register Direct Clear Package Options Include Plastic Small-Outline Ceramic Flat Packages, Ceramic Chip Carriers (FK), Standard Plastic Ceramic 300-mil DIPs
SN54HC595 PACKAGE SN74HC595 PACKAGE (TOP VIEW)
description
'HC595 contain 8-bit serial-in, parallel-out shift register that feeds 8-bit D-type storage register. storage register parallel 3-state outputs. Separate clocks provided both shift storage register. shift register direct overriding clear (SRCLR) input, serial (SER) input, serial outputs cascading. Both shift register clock (RCLK) storage register clock (SRCLK) positive-edge triggered. both clocks connected together, shift register always clock pulse ahead storage register. SN54HC595 characterized operation over full military temperature range -55°C 125°C. SN74HC595 characterized operation from -40°C 85°C.
RCLK SRCLK SRCLR
SN54HC595 PACKAGE (TOP VIEW)
RCLK SRCLK
internal connection
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1997, Texas Instruments Incorporated
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SRCLR
SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
logic symbol
RCLK SRG8
SRCLR SRCLK
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
POST OFFICE 655303
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
logic diagram (positive logic)
RCLK SRCLR SRCLK
numbers shown packages.
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
absolute maximum ratings over operating free-air temperature range
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 113°C/W package 78°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD except through-hole packages, which trace length zero.
recommended operating conditions
SN54HC595 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise fall) time 3.15 1.35 1000 SN74HC595 3.15 1.35 1000 UNIT
Operating free-air temperature this device used threshold region (from VILmax VIHmin there potential into wrong state from induced grounding, causing double clocking. Operating with inputs 1000 does damage device; however, functionally, inputs ensured while shift, count, toggle operating modes.
POST OFFICE 655303
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS QA-QH, -5.2 QA-QH, -7.8 QA-QH, QA-QH, 3.98 3.98 5.48 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.17 0.15 0.15 ±0.1 ±0.01 0.26 0.26 0.26 0.26 ±100 ±0.5 SN54HC595 ±1000 SN74HC595 3.84 3.84 5.34 5.34 0.33 0.33 0.33 0.33 ±1000 UNIT
POST OFFICE 655303
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
fclock Clock frequency SRCLK RCLK high Pulse duration SRCLR before SRCLK SRCLK before RCLK Setup time SRCLR before RCLK SRCLR high (inactive) before SRCLK Hold time, after SRCLK 25°C SN54HC595 SN74HC595 UNIT
This setup time ensures output register sees stable data from shift-register outputs. clocks tied together, which case output register clock pulse behind shift register.
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) fmax SRCLK RCLK QA-QH tPHL SRCLR QA-QH tdis QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) RCLK QA-QH QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
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SN54HC595, SN74HC595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
PARAMETER MEASUREMENT INFORMATION
PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
tdis
LOAD CIRCUIT
High-Level Pulse
VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input Data Input
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
Input tPLH In-Phase Output tPHL Out-ofPhase Output tPLH tPHL
Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH Output Waveform (See Note
tPLZ tPHZ
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
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DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated

8-Bit Serial-In, Parallel-Out Shift High-Current 3-State Outputs Drive

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