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TMS320F20x/F24x Embedded Flash Memory Technical Reference
This document contains preliminary data current publication date subject change without notice.
Literature Number: SPRU282 September 1998
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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Preface
Read This First
About This Manual
This reference guide describes operation embedded flash EEPROM module TMS320F20x/F24x digital signal processor (DSP) devices provides sample code that developing your software. performance specifications embedded flash memory have been evaluated using algorithms techniques described this guide. does recommend deviation from these algorithms techniques, since doing could affect device performance. book does describe specific flash programming tool does describe external interface DSP. information about aspect TMS320F20x/F24x devices other than embedded flash EEPROM module, Related Documentation from Texas Instruments page
This Manual
There several stand-alone flash programming tools TMS320F20x/ F24x generation DSPs. Using these stand-alone tools with TMS320F20x/F24x requires only basic understanding flash operations. More information about these flash programming tools available page, http://www.ti.com. This guide intended provide complete understanding flash operations. This level understanding necessary making modifications existing flash programming tools developing alternative programming schemes.
looking information about: Algorithms Erasing flash array Turn these locations: Chapter Algorithm Implementations Software Considerations Section 1.1, Basic Concepts Flash Memory Technology Section 2.1, Modifying Contents TMS320F20x/F24x Flash Array Section 2.6, Erase Operation Section 3.3, Erase Algorithm
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looking information about: Over-erasure (depletion) recovery
Turn these locations: Section 1.1, Basic Concepts Flash Memory Technology Section 2.7, Recovering From Over-Erasure (Flash-Write Operation) Section 3.4, Flash-Write Algorithm Section 1.1, Basic Concepts Flash Memory Technology Section 2.1, Modifying Contents TMS320F20x/F24x Flash Array Section 2.5, Program Operation Section 3.2, Programming Algorithm Appendix Assembly Source Listings Program Examples
Programming flash array
Sample code
Notational Conventions
This document uses following conventions.
flash EEPROM referred flash memory flash module.
term flash array refers actual memory array within flash module. flash module includes flash memory array associated control circuitry.
generation devices abbreviated follows: TMS320F20x/24x generation: 'F20x/24x TMS320F20x devices: 'F20x TMS320F24x devices: 'F24x Program listings code examples shown special type-
face. Here sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even
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Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
following books describe 'F20x/24x related support tools. obtain copy these documents, call Texas Instruments Literature Response Center (800) 477-8924. When ordering, please identify book title literature number.
TMS320C24x Controllers Reference Set, Volume CPU, System, Instruction (literature number SPRU160) describes TMS320C24x 16-bit, fixed-point, digital signal processor controller. Covered architecture, internal register structure, data program addressing, instruction set. Also includes instruction comparisons design considerations using XDS510 emulator. TMS320C24x Controllers Reference Volume Peripheral Library Specific Devices (literature number SPRU161) describes peripherals available TMS320C24x digital signal processor controllers their operation. Also described specific device configurations 'C24x family. TMS320C240, TMS320F240 Controllers (literature number SPRS042) data sheet contains electrical timing specifications these devices, well signal descriptions pinouts available packages. TMS320C2x/C2xx/C5x Optimizing Compiler User's Guide (literature number SPRU024) describes 'C2x/C2xx/C5x compiler. This compiler accepts ANSI standard source code produces TMS320 assembly language source code 'C2x, 'C2xx, 'C5x generations devices. TMS320F206 Digital Signal Processor (literature number SPRS050) data sheet contains electrical timing specifications 'F206 device, well signal descriptions pinout. TMS320F241, TMS320C241, TMS320C242 Controllers (literature number SPRS063) data sheet contains electrical timing specifications 'F241, 'C241, 'C242 devices, well signal descriptions pinouts. TMS320F243 Controller (literature number SPRS064) data sheet contains electrical timing specifications 'F243 device, well signal descriptions pinout. TMS320C2xx User's Guide (literature number SPRU127) discusses hardware aspects 'C2xx 16-bit, fixed-point digital signal processors. describes architecture, instruction set, on-chip peripherals.
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Read This First
Related Documentation From Texas Instruments
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TMS320C2xx Source Debugger User's Guide (literature number SPRU151) tells invoke 'C2xx emulator simulator versions source debugger interface. This book discusses various aspects debugger interface, including window management, command entry, code execution, data management, breakpoints. also includes tutorial that introduces basic debugger functionality.
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Read This First
Contents
Contents
Introduction Discusses basic flash memory technology; summarizes features benefits TMS320F20x/F24x flash module Basic Concepts Flash Memory Technology TMS320F20x/F24x Flash Module Benefits Embedded Flash Memory System
Flash Operations Control Registers Describes operations that modify content flash module; explains role control registers Operations that Modify Contents 'F20x/F24x Flash Array Accessing Flash Module 2.2.1 TMS320F206 Flash Access-Control Register 2.2.2 TMS320F24x Flash Access-Control Register Flash Module Control Registers 2.3.1 Segment Control Register (SEG_CTR) 2.3.2 Flash Test Register (TST) 2.3.3 Write Address Register (WADRS) 2.3.4 Write Data Register (WDATA) Read Modes Program Operation Erase Operation Recovering From Over-Erasure (Flash-Write Operation) Reading From Flash Array Protecting Array
Algorithm Implementations Software Considerations Describes algorithms used programming, erase, flash-write operations; discusses considerations necessary developing your software Algorithms Into Program-Erase-Reprogram Flow Programming Clear) Algorithm Erase Algorithm Flash-Write Algorithm
Assembly Source Listings Program Examples Assembly Source Algorithms
Contents
A.1.1 Header File Constants Variables, SVAR20.H A.1.2 Clear Algorithm, SCLR20.ASM A.1.3 Erase Algorithm, SERA20.ASM A.1.4 Flash-Write Algorithm, SFLW20.ASM A.1.5 Programming Algorithm, SPGM20.ASM A.1.6 Subroutines Used Four Algorithms, SUTILS20.ASM C-Callable Interface Flash Algorithms Sample Assembly Code Erase Reprogram TMS320F206 A.3.1 Assembly Code TMS320F206 A.3.2 Linker Command File TMS320F206 Sample Assembly Code Sample Code Erase Reprogram TMS320F206 A.4.1 Code That Calls Interface Flash Algorithms TMS320F206 A.4.2 Linker Command File TMS320F206 Sample Code Sample Assembly Code Erase Reprogram TMS320F240 A.5.1 Assembly Code TMS320F240 A.5.2 Linker Command File TMS320F240 Sample Assembly Code Using Algorithms With Code Erase Reprogram 'F240 A.6.1 Code That Calls Interface Flash Algorithms TMS320F240 A.6.2 Linker Command File TMS320F240 Sample Code A.6.3 Function Disabling TMS320F240 Watchdog Timer A.6.4 Functions Initializing TMS320F240
Figures
Figures
TMS320F20x/F24x Program Space Memory Maps Flash Memory Logic Levels During Programming Erasing Memory Maps Register Array Access Modes Segment Control Register (SEG_CTR) Algorithms Overall Flow Programming Algorithm Overall Flow Programming Clear Algorithm Flow Erase Algorithm Overall Flow Erase Algorithm Flow Flash-Write Algorithm Overall Flow Flash-Write Algorithm Flow
Contents
Tables
Tables
TMS320 Devices With On-Chip Flash EEPROM Operations that Modify Contents Flash Array Flash Module Control Registers Segment Control Register Field Descriptions Flash Array Segments Summary Steps Verifying Programmed Bits Applying Program Clear Pulse Steps Applying Erase Pulse Steps Applying Flash-Write Pulse
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Chapter
Introduction
TMS320F20x/F24x digital signal processors (DSPs) contain on-chip flash EEPROM (electrically-erasable programmable read-only memory). embedded flash memory provides attractive alternative masked program ROM. Like ROM, flash memory nonvolatile, advantage over ROM: in-system reprogrammability. This chapter discusses basic flash memory technology, introduces flash memory module 'F20x/F24x DSP, lists benefits flash memory embedded chip.
Topic
Page
Basic Concepts Flash Memory Technology TMS320F20x/F24x Flash Module Benefits Embedded Flash Memory System
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Basic Concepts Flash Memory Technology
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Basic Concepts Flash Memory Technology
term flash this EEPROM technology refers speed some operations performed memory (these operations will described greater detail later this document). entire block bits affected simultaneously block flash operation, rather than being affected time. contrast, writing data flash memory cannot block operation, since normally selection ones zeroes written (all bits same value). Writing selected bits create desired pattern known programming flash memory, written called programmed bit. Several different types program erase operations performed flash memory order properly produce desired pattern ones zeroes memory. should noted that, under some conditions, flash memory become overerased, resulting condition known depletion. 'F20x/F24x algorithms avoid overerasure using approach that erases small increments until complete erasure achieved. 'F20x/F24x flash EEPROM includes special operation, flash-write, that used only recover from over-erasure. Because implementation flash memory, when over-erasure occurs, particular depletion mode difficult identify. this reason, 'F20x/F24x simply writes entire block bits simultaneously; hence, name flash-write. program erase operations flash memory must provide sufficient charge margin ensure data retention, 'F20x/F24x flash module includes hardware mechanism that provides margin erasing programming. This mechanism implements voltage reference levels which ensure this logic level margin when modifying contents flash memory.
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TMS320F20x/F24x Flash Module
TMS320F20x/F24x Flash Module
'F20x/F24x flash EEPROM implemented with independent flash memory modules words. Each flash module composed flash memory array, four control registers, circuitry that produces analog voltages programming erasing. flash array size TMS320F206 TMS320F240 bits, while TMS320F241 TMS320F243 incorporate 16-bit flash array (see Table 1-1). Unlike most discrete flash memories, 'F20x/F24x flash module does require dedicated state machine, because algorithms programming erasing flash executed software core. these sophisticated, adaptive programming algorithms results reduced chip size greater programming flexibility. addition, application code manage flash memory without requirement external programming equipment.
Table 1-1. TMS320 Devices With On-Chip Flash EEPROM
Device TMS320F206 TMS320F240 TMS320F241 TMS320F243
Each array independently erased.
Array Size
Total Flash Memory
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Introduction
TMS320F20x/F24x Flash Module
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Simplified memory maps program space TMS320F20x/F24x devices shown Figure illustrate location flash modules.
Figure 1-1. TMS320F20x/F24x Program Space Memory Maps
TMS320F206 MP/MC 0000h Flash0 3FFFh 4000h Flash1 7FFFh 8000h 3FFFh 4000h 0000h Flash0 TMS320F240 MP/MC 0000h 1FFFh TMS320F241 0000h 1FFFh TMS320F243 MP/MC Flash0
Flash0 external memory available
FFFFh
FFFFh
FFFFh
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Benefits Embedded Flash Memory System
Benefits Embedded Flash Memory System
circuitry density flash memory about half that conventional EEPROM memory, making possible approach DRAM densities with flash memory. This increased density allows flash memory integrated with other peripherals single 'F20x/F24x chip. Embedded flash memory expands capabilities 'F20x/F24x DSPs areas prototyping, integrated solutions, field upgradeable designs. Embedded flash memory facilitates system development early field testing. Throughout development process, system software updated reprogrammed into flash memory testing various stages. Since flash non-volatile memory type, resulting standalone prototype tested appropriate environment without need battery backup. addition nonvolatile nature, embedded flash memory advantage in-system programming. Unlike some discrete flash EEPROM chips, embedded flash memory programmed without removing device from system board. fact, embedded flash memory 'F20x/F24x DSPs programmed using hardware emulators which already integral part development process; external programming equipment required. embedded flash memory 'F20x/F24x DSPs also makes these devices ideal highly integrated, low-cost systems. initial investment involved with making memory justifiable certain low-cost applications. Accordingly, when on-chip option, system designers usually resort using expensive static (SRAM), store system software data. SRAM provides fast access times required DSP, disadvantage being volatile memory type. address issue memory volatility, designers often low-cost EPROM flash device load SRAM after system power-up. This approach very expensive, increased chip count often prohibitive. 'F20x/F24x DSPs, with their on-chip flash memory modules, provide single chip solution with nonvolatile memory that supports full speed access rates. Another benefit embedded flash memory system remote reprogrammability. Field upgradeability extremely useful feature embedded systems. example, many modem manufacturers offer algorithm upgrades remotely, without requiring modem removed from host computer system. same type feature also being offered many handheld consumer products. Adding this capability product requires addition EEPROM flash devices, which increase chip count system cost. Since external equipment required program embedded flash memory 'F20x/F24x DSPs, these devices enable field upgradeability without impacting system cost.
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Introduction
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Chapter
Flash Operations Control Registers
operations that modify contents 'F20x/F24x flash array performed software through dedicated programming algorithms. This chapter introduces operations performed these algorithms explains role control registers this process. actual algorithms discussed Chapter
Topic
Page
Operations that Modify Contents 'F20x/F24x Flash Array Accessing Flash Module Flash Module Control Registers Read Modes 2-12 Program Operation 2-13 Erase Operation 2-14 Recovering From Over-Erasure (Flash-Write Operation) 2-15 Reading From Flash Array 2-16 Protecting Array 2-16
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Operations that Modify Contents 'F20x/F24x Flash Array
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Operations that Modify Contents 'F20x/F24x Flash Array
Operations that modify contents flash array generically referred either "programming," which drives more bits toward logic zero state, "erasing," which drives bits towards logic state. should noted that since these operations performed incrementally, single "programming" "erasing" operation does ALWAYS result valid logic zero. result each these types operations depends initial state bit(s) prior operation. This described more detail below. Within these basic types operations (which related fact that there only valid logic levels F20x/F24x device) four distinctly different types functions which actually performed. category "programming" operations, there three actual types functions that performed:
Clear which used write array bits zero state, Program which used write SELECTED array bits zero, Flash-Write which used recover array bits from depletion
category "erase" operations, there only type operation:
Erase which used write array bits state.
Clear, Program, Flash-Write, Erase only four functions that used modify flash array. Assuming that intent modification contents flash array program array with selection ones zeroes, following sequence operations must performed proper operation flash memory: array first CLEARED zeroes. array then ERASED ones. array then checked depletion recovered using FLASHWRITE necessary (note that Flash-Write used recover from depletion, this sequence must started over again with Clear Erase functions). Once array properly cleared erased, verified depletion, array then PROGRAMMED with desired selection zero bits.
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Operations that Modify Contents 'F20x/F24x Flash Array
This procedure discussed complete detail Chapter During these operations that used modify contents flash array, three special read modes, corresponding reference voltage levels, used when reading back data values verify programming erase operations. These read modes reference levels are:
VER0 which used verify logic zero level including margin, VER1 which used verify logic level including margin, Inverse Erase which used verify depletion recovery.
These concepts illustrated graphically Figure summarized Table 2-1. Note that ONLY Erase Flash-Write functions truly "flash" sense that these functions actually affect bits array simultaneously. contrast, programming levels Program Clear functions controlled individually bit-by-bit basis. Therefore, when using Erase Flash-Write functions, whole array modified, then whole array read, word word, verify whether words have reached same value not, further iterations Erase Flash-Write functions continue). these cases, mentioned previously, bits array modified simultaneously, some bits react more quickly, potentially resulting variation actual levels different bits. Therefore, when performing Erase, possible that some bits reach depletion even before other bits reach logic reference level (VER1). reason that critical clear array consistent zero level before erasing array give maximum immunity depletion when erasing. Note, however, that even when following this sequence, some flash arrays experience depletion, require recovery using Flash-Write function. contrast true "flash" operations Erase Flash-Write, after each incremental Program Clear operation, each tested against VER0 reference level determine exact point which reached proper value, following which, further incremental adjustment level made that bit. Therefore, when Program Clear operation complete, bits same zero level, which greatly increases proper data retention depletion immunity device. Again, note that programming erase operations discussed complete detail Chapter
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Flash Operations Control Registers
Operations that Modify Contents 'F20x/F24x Flash Array
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Figure 2-1. Flash Memory Logic Levels During Programming Erasing
Depletion Mode Inverse Erase Reference Level Logic VER1 Reference Level Margin Program operations
Clear Program Flash Write
Erase
(Towards logic zero level)
(Towards logic level)
Erase operation Margin VER0 Reference level Logic
Table 2-1. Operations that Modify Contents Flash Array
Change Level Towards Logic Function Erase (all bits) Reference Level VER1 Towards Logic Function Program (selected bits) Clear (all bits) Flash-Write (all bits) Reference Level VER0 VER0 Inverse Erase
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Accessing Flash Module
Accessing Flash Module
addition flash memory array, each flash module four registers that control operations flash array. These registers are:
Segment control register (SEG_CTR) Test register (TST) Write address register (WADRS) Write data register (WDATA)
flash module operates modes: which flash memory accessed directly CPU, which memory array cannot accessed directly, four control registers accessible. This mode used programming. Each flash module flash access-control register that selects between these access modes. register single-bit, I/O-mapped register. access modes summarized follows:
Array-access mode. access flash array memory space
decoded flash module. flash module remains this mode most time, because allows core read from memory array.
Register-access mode. access four control registers
memory space decoded flash module. This mode used programming. When flash module register-access mode, registers repeated every four address locations within flash module's address range. flash array directly accessible memory register-access mode, control registers directly accessible array-access mode. Figure shows memory maps flash array register array access modes.
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Flash Operations Control Registers
Accessing Flash Module
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Figure 2-2. Memory Maps Register Array Access Modes
Flash access control register (single bit) MODE Array-access mode MODE Register access mode
0100 0100
SEG_CTR register register WADRS register WDATA register registers duplicated
Flash memory array registers duplicated
1110 .110 0110 .111
registers duplicated
2.2.1
TMS320F206 Flash Access-Control Register
Because each flash module access-control register associated with 'F206 access-control registers. These registers standard I/Omapped registers that read with instruction must modified with instruction.
F_ACCESS0 mapped space 0FFE0h. F_ACCESS1 mapped space 0FFE1h.
MODE (bit access-control register selects access mode: MODE MODE Register-access mode Array-access mode
Bits 15-1 each access-control register always read unaffected writes.
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Accessing Flash Module
Although function same, access control registers 'F206 device mapped different addresses from that 'F24x devices, their values modified different way.
2.2.2
TMS320F24x Flash Access-Control Register
access-control register 'F24x devices special type I/Omapped register that cannot read. register mapped address 0FF0Fh, functions indicated below. Note: both instructions, data operand (dummy) used, valid memory location. instruction using register address port places flash module register-access mode. example:
dummy, 0FF0Fh ;Selects register-access mode
instruction using register address port places flash module array-access mode. data operand (dummy) used, valid memory location. example:
dummy, 0FF0Fh ;Selects array-access mode
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Flash Operations Control Registers
Flash Module Control Registers
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Flash Module Control Registers
Table lists control registers their relative addresses within four locations that repeat throughout module's address range.
Table 2-2. Flash Module Control Registers
Described Relative Address Register Name SEG_CTR Description Segment control register. eight MSBs enable specific segments programming. Setting enables segment. eight LSBs control program, erase, verify operations module. Test register. Reserved test; accessible user. Write address register. Holds address write operation. Write data register. Holds data write operation. Section 2.3.1 Page
WADRS WDATA
2.3.2 2.3.3 2.3.4
2.3.1
Segment Control Register (SEG_CTR)
SEG_CTR 16-bit register that initiates monitors programming erasing flash array. This register contains bits that initiate active operations (the WRITE/ERASE field bit), those used verification (VER0 VER1), those used protection (KEY0, KEY1, SEG7-SEG0). bits SEG_CTR register cleared upon reset. SEG_CTR shown Figure fields described Table 2-3.
Figure 2-3. Segment Control Register (SEG_CTR)
SEG7
RW-0
SEG6
RW-0
SEG5
RW-0
SEG4
RW-0
SEG3
RW-0
SEG2
RW-0
SEG1
RW-0
SEG0
RW-0
KEY1
RW-0
KEY0
RW-0
VER0
RW-0
VER1
RW-0
WRITE/ ERASE
RW-0
RW-0
Legend: read write value after reset don't care
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Table 2-3. Segment Control Register Field Descriptions
Bits 15-8 Name SEG7-SEG0 Description
Flash Module Control Registers
Segment enable bits. Each these bits protects specified segment against programming enables programming specified segment array. number segments (from combination) enabled time. Table segment address ranges. must cleared modify SEGx bits. SEGx enables programming corresponding segment. SEGx protects segment from programming.
Reserved KEY1, KEY0
This affected writes, reads this undefined. Execute bits. binary value must written these bits same core access which selected operation (erase, program, flash-write) start. KEY1 KEY0 must cleared same write access that clears EXE. These bits used additional protection against inadvertent programming erasure array. These bits read Verify bits. These bits select special read modes used verify proper erasure programming. Possible values: Normal read mode Verify (VER1) read mode verify margin proper erasure Verify (VER0) read mode verify margin proper programming Inverse-read mode; tests bits erased into depletion
VER0, VER1
WRITE/ERASE
Write/erase enable field. These bits select program, erase, flash-write operation. However, modification array data does actually start until set. Reset clears these bits zero. Possible values: Read operation enabled. These values required read array. Erase operation enabled Write operation enabled Flash-write operation enabled
Execute bit. conjunction with WRITE/ERASE, KEY1, KEY0, this controls program, erase, flash-write operations. Setting starts stops programming erasing flash array. KEY1 KEY0 bits must written same write access that sets EXE, must cleared same write access that clears KEY1 KEY0. must cleared modify SEGx bits.
Note:
segment enable bits intended protection during erase flash-write operations. During these operations, segments must enabled.
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Flash Operations Control Registers
Flash Module Control Registers
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Table 2-4. Flash Array Segments Summary
SEG7-SEG0 Bits 'F206/F240 Flash Module Flash0 Flash1 'F241/F243 F241/F243 Flash Module 0000-03FFh 0400-07FFh 0800-0BFFh 0C00-0FFFh 1000-13FFh 1400-17FFh 1800-1BFFh 1C00-1FFFh Array Segment Enabled
0000-07FFh 4000-47FFh 0800-0FFFh 4800-4FFFh 1000-17FFh 5000-57FFh 1800-1FFFh 5800-5FFFh 2000-27FFh 6000-67FFh 2800-2FFFh 6800-6FFFh 3000-37FFh 7000-77FFh 3800-3FFFh 7800-7FFFh
TMS320F206 flash modules. TMS320F240 device uses address ranges shown Flash0.
Although segmentation supported during erase (i.e., entire array must erased simultaneously), segment enable bits used protect portions array against unintentional programming. This useful applications which different portions array programmed different times. example, application might program flash module with large table blocks. Some time after first block programmed, next block programmed. segment enable bits used prevent corruption first block while second block being programmed.
2.3.2
Flash Test Register (TST)
flash test register (TST) 5-bit register used during manufacturing test flash array. This register accessible core.
2.3.3
Write Address Register (WADRS)
write address register (WADRS) 16-bit register that holds latched write address programming operation. array-access mode, this register loaded with value address when writing data value flash module. loaded directly register-access mode writing
2-10
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2.3.4 Write Data Register (WDATA)
Flash Module Control Registers
write data register (WDATA) 16-bit register that contains latched write data programming operation. array-access mode, this register loaded writing data value flash module. loaded directly register-access mode writing WDATA register must loaded with value FFFFh before erase operation starts.
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Flash Operations Control Registers
2-11
Read Modes
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Read Modes
'F20x/F24x flash module uses four read modes corresponding sets reference levels:
Standard Verify (VER0) Verify (VER1) Inverse-erase
Read mode selection accomplished through verify bits (bits SEG_CTR during execution algorithms. standard read mode 'F20x/F24x flash module, supply voltage (VDD) internally applied cell select reading. VER0, VER1, inverse-erase read modes differ from standard read mode internal voltage level applied flash cell. Because program erase operations must provide sufficient margin ensure data retention, verify (VER0) verify (VER1), provided flash module check sufficient margin. VER0 VER1 read modes provide method adjusting level cells during programming erasing, beyond point required reading creating required logic level margin. VER0 mode, voltage closer ideal logic zero level than necessary read logic zero internally applied cell select reading. This worst-case condition reading programmed cell, cell read VER0 mode, then also read standard read mode. Similarly, VER1 read mode, voltage closer ideal logic level than necessary read logic internally applied cell select reading. This worst-case condition reading erased cell, cell read VER1 mode, then read standard read mode. inverse-erase read mode detects flash bits that depletion mode. This read mode applies voltage array cells that cells deselected. entire array tested bits depletion mode reading first words) array inverse-erase read mode. there bits depletion mode, words read 0000h.
2-12
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Program Operation
Program Operation
program operation 'F20x/F24x flash module loads applicationspecific data pattern into flash array. basis operation applying program pulse single word flash memory. term program pulse refers time during program operation between setting clearing SEG_CTR). During program pulse, charge added addressed bits programming mechanism. Several program pulses required fully program bits word, application program pulses controlled programming algorithm. flash location programmed specified address WADRS register, data pattern programmed loaded into WDATA register. Only bits that contain programmed; positions containing remain unchanged. (See sections 2.3.3 2.3.4 information about load WADRS WDATA registers.) assure that bits programmed with enough margin, reads associated with programming performed using VER0 read mode. After program pulse been applied, byte read back VER0 mode assure that programmed bits read over entire operating range device. flash module supports programming eight bits data. Therefore, although flash bits addressed 16-bit word boundaries, only eight bits programmed time. algorithm must limit programming eight bits masking word programmed before writing WDATA register. example, mask upper byte while programming lower byte, data value logically 0Red with 0FF00h software. When program pulse applied, only selected bits programmed.
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Flash Operations Control Registers
2-13
Erase Operation
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Erase Operation
erase operation 'F20x/F24x flash module prepares flash array programming enables reprogrammability flash array. Before array erased, bits must programmed This procedure programming array locations preparation erase called clearing array. During erase, bits array changed from After erase finished, depletion mode test made determine whether bits have been over-erased. over-erased bits detected, they must recovered with flash-write algorithm, clear erase algorithms must repeated. erase pulse time during erase operation between setting clearing SEG_CTR). During erase pulse, level array bits modified erase mechanism. Erasing flash array block operation. During erase pulse, array bits affected simultaneously. (See Figure 2-1, Flash Memory Logic Levels During Programming Erasing, page illustration this mechanism.) Multiple erase pulses required fully erase bits array, application erase pulses controlled erase algorithm. erase operation uses VER1 read mode determine when erasure complete. After erasure complete, inverse-erase read mode used determine bits over-erased. more information about these read modes, section 2.4, Read Modes, page 2-12.
2-14
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PRELIMINARY
Recovering From Over-Erasure (Flash-Write Operation)
Recovering From Over-Erasure (Flash-Write Operation)
Generally, bits flash array have same amount charge removed with each erase pulse. time bits have reached VER1 read margin (and erase complete), some bits array overerased. They said depletion mode. even single flash cell over-erased into depletion mode, always read logic corrupt reading other bits. This condition must detected corrected, because also inhibits reprogramming flash array. 'F20x/F24x flash array employs flash-write operation recover bits that erased into depletion mode. flash-write operation similar erase operation that affects bits array simultaneously. This enables recovery multiple bits from depletion mode, requires flashwrite operation followed clear erase operations restore erase margin bits. flash-write pulse time during flash-write operation between setting clearing (bit SEG_CTR). During flash-write pulse, array bits affected simultaneously. (See Figure 2-1, Flash Memory Logic Levels During Programming Erasing, page illustration this mechanism.) Multiple flash-write pulses required fully recover bits array, application flash-write pulses controlled flash-write algorithm. flash-write operation uses inverse-erase read mode inverseerase reference level detect bits that depletion mode. more information about inverse-erase read mode, section 2.4, Read Modes, page 2-12.
PRELIMINARY
Flash Operations Control Registers
2-15
Reading From Flash Array
PRELIMINARY
Reading From Flash Array
Once array programmed, read same manner other memory devices memory interface. flash module operates with zero wait states. When reading flash module, flash segment control register (SEG_CTR) bits should flash array must arrayaccess mode.
Protecting Array
After flash memory array programmed, desirable protect array against corruption. flash module 'F20x/F24x DSPs includes several protection mechanisms prevent unintentional modification array. Flash programming facilitated supply voltage connected VCCP pin. this grounded, program operation will modify flash array. Note, that grounding VCCP does prevent erase operation; other protection mechanisms erase operation discussed below. control registers provide following mechanisms protecting flash array from unintentional modification.
Segment enable bits EXE, KEY0, KEY1 bits WDATA register
array segment prevented from being programmed when corresponding segment enable SEG_CTR cleared zero. Additionally, segment enable bits cleared reset, making unintentional programming less likely. Even segment enable bits one, program, erase, flash-write operations initiated unless appropriate values EXE, KEY0, KEY1 bits SEG_CTR. start operation, KEY1 KEY0 bits must written same write access that sets EXE. When program pulse, erase pulse, flash-write pulse finished, must cleared same write that clears KEY1 KEY0. data address latches locked whenever set, attempts read from write array ignored (read data indeterminate). Once set, register bits latched protected. must clear modify SEGx bits. This protects array from inadvertent change. Unprotected segments cannot masked same register load with deactivation EXE. Additional security provided function WDATA register prevent unintentional erasure. WDATA register must loaded with FFFFh before erase operation initiated. register loaded with this value, array will modified.
2-16
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PRELIMINARY
Chapter
Algorithm Implementations Software Considerations
This chapter discusses implementations algorithms performing operations described previous chapter. also discusses items must consider when incorporating algorithms into your 'F20x/F24x application code.
Topic
Page
Algorithms Into Program-Erase-Reprogram Flow Programming Clear) Algorithm Erase Algorithm 3-10 Flash-Write Algorithm 3-14
PRELIMINARY
Algorithms Into Program-Erase-Reprogram Flow
PRELIMINARY
Algorithms Into Program-Erase-Reprogram Flow
algorithms discussed this chapter used reprogram 'F20x/F24x flash module multiple times. clear algorithm, erase algorithm, flash-write algorithm used prepare flash memory programming, while programming algorithm used write desired pattern array (program array). programming algorithm clear algorithm both implementations program operation. difference between data that written: programming algorithm programs user data, while clear algorithm uses algorithms viewed portions single flow diagram, shown Figure 3-1. Note that algorithm flowcharts, variable represents number attempts depletion recovery using flash-write algorithm. been shown that flash-write successful depletion recovery after attempts, depletion recovery possible, device failure occurred. Therefore, flash-write attempts depletion recovery successful, algorithm returns device failure error message.
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PRELIMINARY
Algorithms Into Program-Erase-Reprogram Flow
Figure 3-1. Algorithms Overall Flow
Initialization flow Start
Clear algorithm
Clear array Flash-write algorithm Recover using flash-write Bits depletion?
Reprogram?
Erase array Erase algorithm
Done/Stop
Fail
Program array
Programming algorithm
PRELIMINARY
Algorithm Implementations Software Considerations
Programming Clear) Algorithm
PRELIMINARY
Programming Clear) Algorithm
programming algorithm sequentially writes number addresses with specified pattern.This algorithm used program application code data into flash array. With slight modification, same algorithm performs clear portion initialization flow (i.e., programs bits zero). this role, algorithm called clear algorithm. clear algorithm, values programmed always 0000h, while values application code combination Figure highlights programming clear algorithms' place overall flow.
Figure 3-2. Programming Algorithm Overall Flow
Initialization flow Start
Clear algorithm
Clear array Flash-write algorithm Recover using flash-write Bits depletion?
Reprogram?
Erase array Erase algorithm
Done/Stop
Fail
Program array
Programming algorithm
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PRELIMINARY
Programming Clear) Algorithm
main feature program/clear algorithm concept programming entire bits group. 'F20x/F24x flash array organized rows words. That addresses 0000h through 001Fh physically located same flash memory array. array designed that there dependence between charge levels adjacent (even-odd) addresses during programming. Programming bits address reduces charge margin programmed bits (the preceding adjacent (even) address within row. Similarly, programming bits even address reduces charge margin programmed bits next adjacent (odd) address within row. Because this dependence, each address programmed individually, charge levels among programmed bits uniform. programming algorithm improves uniformity charge levels programmed bits programming words group. example, contents address 0000h compared with data programmed program pulse applied necessary. same procedure performed addresses 0001h through 001Fh. procedure repeats starting address 0000h until more program pulses required address row. number iterations this loop equals maximum number program pulses required program bits row. flow programming algorithm shown Figure 3-3, assembly code given Appendix important consideration programming flash array frequency range application. Because actual implementation flash memory circuitry, most easily read high frequency; programmed bits have less margin when read lower frequency. application requires variable clock rate, programming should performed lowest frequency range. similar condition exists erase operation, which requires execution erase algorithm highest frequency range. section 3.3, page 3-10.) Only read portion program operation must performed lower frequency, because read used determine margin. read operation extended sequentially executing multiple reads same location. Because same address selected entire time internal control signals maintained between reads, final read equivalent slow read. example, core executing programming algorithm CLKOUT rate ns), sequentially reading location three times equivalent reading once 6.67 (150 ns). This important, because facilitates execution program erase algorithms same CLKOUT rate.
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Algorithm Implementations Software Considerations
Programming Clear) Algorithm
PRELIMINARY
Figure 3-3. Programming Clear Algorithm Flow
Start Save start address Same Current address start address; row_done true
Verify contents current address
Steps Table
Step Table Program pulse required?
Steps 7-25 Table Apply program pulse; row_done false
Increment address
row?
Pulsecount =max?
Row_done true?
Current address address?
device data sheet timing parameter values.
Continue Device failure
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PRELIMINARY
Programming Clear) Algorithm
Another important consideration total amount time required programming. number programming pulses required completely program flash memory cell increases ambient temperature increases and/or supply voltage decreases. More programming pulses required when minimum supply voltage used than when nominal maximum supply voltage used. number program pulses required also increases throughout life device, more program-erase cycles carried out. device data sheet specifies maximum number program pulses under operating conditions; this number when calculate maximum amount time required programming. algorithm incorporates steps applying program pulse (outlined Table 3-1) along with some other techniques ensure margin. general, flash bits require same number program pulses reach programmed margin level. this reason, programming algorithm applies series short program pulses until memory location programmed. However, understand series program pulses works, must first understand algorithm applies single program pulse. Table outlines steps involved verifying programmed bits applying single pulse each upper lower bytes single location. This process corresponds steps enclosed dashed flowchart Figure 3-3.
Table 3-1. Steps Verifying Programmed Bits Applying Program Clear Pulse
Step Action Power VCCP pin. Activate VER0 mode. Description VCCP VDD. VCCP flash module programmed VDD, then array will programmed. VER0 SEG_CTR (load SEG_CTR with 0010h).
Delay VER0 reference executes delay loop td(VERIFY-SETUP) time period. voltage stabilization. Read flash array contents reads addressed location. flash module must verification. array-access mode (see section 2.2, Accessing Flash Module, page 2-5). Deactivate VER0 mode. Clear VER0 SEG_CTR (load SEG_CTR with 0000h).
Compare contents flash verification passes (i.e., data read step equal delocation bits) with sired data value), then further program pulses required. flash word been programmed with desired data value. program sired data. clear function completed this algorithm exited. verification fails (i.e., data read step equal desired data value), then proceed step
PRELIMINARY
Algorithm Implementations Software Considerations
Programming Clear) Algorithm
PRELIMINARY
Table 3-1. Steps Verifying Programmed Bits Applying Program Clear Pulse (Continued)
Step Action Description
Mask data program Mask bits lower byte that require programming (are allower byte. ready read zero), mask upper byte. Recall that algorithm should mask byte while programming other because maximum eight bits programmed simultaneously. Load WADRS WDATA flash module array access mode, write data proregisters. grammed address. flash module register access mode, load individual registers directly. Activate WRITE/ERASE WRITE/ERASE field SEG_CTR correspondfield enable segments. segment enable bits (SEG0-SEG7) segments where programmed word resides.
device data sheet timing parameter values.
Wait internally generated executes delay loop td(PGM-MODE) time period. supply voltage stabilization time. Initiate program pulse. Load EXE, KEY1, KEY0 bits with respectively. three bits must loaded same write cycle. segment enable bits WRITE/ERASE field must also maintained.
16-25
Delay program pulse executes delay loop td(PGM) time period. time. Terminate pulse. program Clear WRITE/ERASE field SEG_CTR (e.g., load SEG_CTR with 0000h).
Delay array stabilization executes delay loop td(BUSY) time period. time. Program upper byte nec- Repeat steps 7-15 upper byte. Mask lower byte when essary. programming upper byte.
device data sheet timing parameter values.
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PRELIMINARY
Programming Clear) Algorithm
Before each program pulse applied, read byte performed determine which bits have reached programmed level. bits that have reached programmed level masked (set WDATA register). This method programming provides uniform charge levels among programmed bits, whereas using single, long program pulse could result some bits having much more charge than others. uniformity charge levels among bits primary effect reducing programming time secondary effect reducing time subsequent erase operation. assure that bits programmed with enough margin, reads associated with programming VER0 read mode.
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Algorithm Implementations Software Considerations
Erase Algorithm
PRELIMINARY
Erase Algorithm
erase algorithm follows clear algorithm executing entire initialization flow. Figure highlights erase algorithm's place overall flow.
Figure 3-4. Erase Algorithm Overall Flow
Initialization flow Start
Clear algorithm
Clear array Flash-write algorithm Recover using flash-write Bits depletion?
Reprogram?
Erase array Erase algorithm
Done/Stop
Fail
Program array
Programming algorithm
erase algorithm consists multiple iterations loop with erase pulse applied each iteration. Table outlines steps involved applying single erase pulse.
3-10
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PRELIMINARY
Table 3-2. Steps Applying Erase Pulse
Step Action Power VCCP pin. Description
Erase Algorithm
VCCP VDD. VCCP flash module erased VDD, then array will erased properly.
Load WDATA register with This load overrides erase protection mechanism. FFFFh. Activate erase mode WRITE/ERASE field SEG0-SEG7 bits enable segments. SEG_CTR register. flash module must register-access mode (see section 2.2). Wait internally generated executes delay loop td(ERASE-MODE) time period. supply voltage stabilization time. Initiate erase pulse. Load EXE, KEY1, KEY0 bits with respectively. three bits must loaded same write cycle. segment enable bits WRITE/ERASE field must also maintained.
Delay erase pulse time. Terminate erase pulse.
executes delay loop td(ERASE) time period. Clear WRITE/ERASE field SEG_CTR register (load SEG_CTR with 0000h clear bits).
Delay mode deselect executes delay loop td(BUSY) time period. time.
device data sheet timing parameter values.
beginning each iteration, read operation performed bits array determine erase pulse required. Erasure complete when array locations read FFFFh. assure that flash array erased with enough margin, reads associated with erase VER1 read mode. Additional margin gained during erase operation reads performed using address complementing. When array read with address complementing, following sequence used each address read: bits address read complemented. contents resulting address read. value read complemented address discarded.
PRELIMINARY
Algorithm Implementations Software Considerations
3-11
Erase Algorithm
PRELIMINARY
actual address restored. contents restored address read. advantage this approach that forces worst-case switching condition flash addressing logic during reads, thus improving margin erase. Address complementing 'F20x/F24x accomplished easily using instruction complement bits address. important consideration erasing flash array frequency range application. Because actual implementation flash memory circuitry, logic most easily read frequency; erased bits have less margin when read higher frequency. Accordingly, application requires variable clock rate, erase should performed highest frequency range. similar condition exists programming operation, which requires execution programming algorithm lowest frequency range. section 3.2, page 3-4.) Another important consideration total amount time required erase array. number erase pulses required completely erase flash memory cell increases ambient temperature increases decreases relative nominal temperature supply voltage decreases. More erase pulses required when ambient temperature toward extremes operating range. Also, more erase pulses required when minimum supply voltage used than when nominal maximum supply voltage used. number erase pulses required also increases throughout life device, more program-erase cycles carried out. device data sheet specifies maximum number erase pulses under operating conditions; this number when calculate maximum amount time required erase algorithm. complete erase algorithm including depletion check shown flowchart Figure 3-5.
3-12
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Figure 3-5. Erase Algorithm Flow
Start (all words=0000h)
Erase Algorithm
VER1 SEG_CTR
Wait td(BUSY-VERIFY) Read locations using address complementing Clear bits SEG_CTR
Verify erase
words FFFFh Apply erase pulse flash array (see Table 3-2)
device data sheet timing parameter values.
Device failure
Depletion recovery
Program array
PRELIMINARY
Algorithm Implementations Software Considerations
words 0000h?
Erase pulse count
VER0 VER1 bits SEG_CTR Wait td(BUSY-INVERSE) Read first words Depletion check
3-13
Flash-Write Algorithm
PRELIMINARY
Flash-Write Algorithm
flash-write operation recovers bits depletion mode, which caused over-erasure. flash-write algorithm's place overall flow highlighted Figure 3-6.
Figure 3-6. Flash-Write Algorithm Overall Flow
Initialization flow Start
Clear algorithm
Clear array Flash-write algorithm Recover using flash-write Bits depletion?
Reprogram?
Erase array Erase algorithm
Done/Stop
Fail
Program array
Programming algorithm
flash-write pulse time during flash-write operation between setting clearing (bit SEG_CTR). Charge added bits flash memory array flash-write mechanism. flashwrite algorithm require multiple flash-write pulses. steps required apply flash-write pulse outlined Table 3-3.
3-14
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PRELIMINARY
Flash-Write Algorithm
Table 3-3. Steps Applying Flash-Write Pulse
Steps Action Power VCCP pin. Description VCCP VDD. VCCP flash module recovered VDD, then flash-write operation will effective.
Activate flash-write WRITE/ERASE field SEG0-SEG7 mode enable seg- SEG_CTR register. flash module must register access ments. mode (see section 2.2). Wait internally gener- executes delay loop td(FLW-MODE) time period. ated supply voltage stabilization time. Initiate flash-write pulse. Load EXE, KEY1, KEY0 bits with respectively. three bits must loaded same write cycle. segment enable bits WRITE/ERASE field must also maintained.
Delay flash-write executes delay loop td(FLW) time period. pulse time. Terminate pulse. flash-write Clear bits SEG_CTR register (load SEG_CTR with 0000h).
Delay mode deselect executes delay loop td(BUSY) time period. time.
device data sheet timing parameter values.
flash-write algorithm consists multiple iterations loop with flashwrite pulse applied each iteration. beginning each iteration, depletion test performed determine flash-write pulse required. Figure shows flow flash-write algorithm. flash-write operation uses inverse-erase read mode detect bits that depletion mode. more information about inverse-erase read mode, section 2.4, Read Modes, page 2-12.
PRELIMINARY
Algorithm Implementations Software Considerations
3-15
Flash-Write Algorithm
PRELIMINARY
Figure 3-7. Flash-Write Algorithm Flow
Start
VER0 VER1 bits SEG_CTR
Wait td(RD-VERIFY) Depletion check Read first words
words 0000h? Apply flash-write pulse flash array (see Table 3-3)
Flash-write pulse count
device data sheet timing parameter values.
Device failure
clear
3-16
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PRELIMINARY
Flash-Write Algorithm
frequency range application important consideration depletion test, well program erase operations. Because actual implementation flash memory circuitry, depletion mode most easily detected frequency. Accordingly, application requires variable clock rate, depletion test should performed lowest frequency range. Only read portion depletion test must performed lower frequency, because read that used detect depletion. effective duration read operation extended sequentially executing multiple reads same location. Because same address selected entire time internal control signals maintained between reads, final read equivalent slow read. example, core executing programming algorithm CLKOUT rate ns), sequentially reading location three times equivalent reading once 6.67 (150 ns). erase flash-write algorithm implementations given Appendix three reads check depletion.
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Algorithm Implementations Software Considerations
3-17
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Appendix Appendix
Assembly Source Listings Program Examples
flash array erased programmed code running core. This code originate from off-chip memory loaded into on-chip RAM. available flash programming tools 'F20x/F24x allow program on-chip flash module without having knowledge visibility algorithms. scheme uses scan emulation feature 'F20x/F24x load algorithms onto control execution, another scheme relies boot loader code preprogrammed into flash memory factory. find more information about these stand-alone flash programming tools Texas Instruments page http://www.ti.com. This appendix explains algorithm source files program flash module. need this information create flash programming tools such features remote reprogrammability design.
Topic
Page
Assembly Source Algorithms C-Callable Interface Flash Algorithms A-27 Sample Assembly Code Erase Reprogram TMS320F206 A-32 Sample Code Erase Reprogram TMS320F206 A-37 Sample Assembly Code Erase Reprogram TMS320F240 A-40 Using Algorithms with Code Erase Reprogram TMS320F240 A-47
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Assembly Source Algorithms
PRELIMINARY
Assembly Source Algorithms
algorithm source files implement flows given Chapter Each algorithm written assembly language subroutine, beginning with label entry point ending with return instruction. algorithms share relocatable variables which pointers defined header file, SVAR20.H. variables defined beginning RAM, uninitialized section should declared link time reserve this space. Also, data page pointer (DP) should initialized point this space before call made algorithms. addition these variables, each algorithm references parameters that should declared globally calling code. These parameters listed introduction each algorithm source files below. source files given are:
SVAR20.H: header file that defines variables constants SCLR20.ASM: clear algorithm SERA20.ASM: erase algorithm SFLW20.ASM: flash-write algorithm SPGM20.ASM: programming algorithm SUTILS20.ASM: subroutines common four algorithms
same algorithm files used TMS320F206 TMS320F240/1/3 devices. conditional assembly variable provided header file, SVAR20.H, assembling algorithms correct device. more details this conditional assembly variable, A.1.1.
A.1.1 Header File Constants Variables, SVAR20.H
This header file included each algorithm files using .include directive. constants used flash programming defined this file. Also, conditional assembly constant, F24x, defined here allow reuse algorithms multiple device types. This constant should modified select correct device when algorithms assembled. SVAR20.H header file also included calling code, allow visibility variable names.
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Assembly Source Algorithms
Variable declaration file TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.1, 1/31/98 Filename: svar20.asm *Note: *DLOOP delay loop variable used flash algorithms. *This function CLKOUT1. F206 device runs *any CLKOUT1 speed other than MHz, DLOOP value should *redefined equation explained below. *current DLOOP flash programming speeds other than recommended. .mmregs BASE .set 0300h ;Base address variables ;can changed relocate ;variable space RAM. BASE_0 .set BASE+0 ;Scratch registers. BASE_1 .set BASE+1 BASE_2 .set BASE+2 BASE_3 .set BASE+3 BASE_4 .set BASE+4 BASE_5 .set BASE+5 BASE_6 .set BASE+6 SPAD1 .set BASE+7 SPAD2 .set BASE+8 FL_ADRS .set BASE+10 ;Flash load address. FL_DATA .set BASE+11 ;Flash load data. ERROR .set BASE+15 ;Error flag register. *Variables ERASE CLEAR RPG_CNT .set BASE+12 ;Program pulse count. FL_ST .set BASE+13 ;Flash start addr/Seg Cntrl Reg. FL_END .set BASE+14 ;Flash address.
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Assembly Source Listings Program Examples
Assembly Source Algorithms
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*CONSTANTS *Conditional assembly variable F24X F206. F24X then assemble F24X; otherwise, *assemble F206. F24X .set ;Assemble F206 ;F24X .set ;Assemble F24X Delay variables CLEAR,ERASE PROGRAM .set delay .set delay D100 .set ;100 delay .set delay .set 1399 delay *DLOOP constant proportional CLKOUT1 *Calculate DLOOP decimal using following equation: DLOOP=FLOOR{(5us/tCLKOUT1)-6}; *Examples MHz, DLOOP= 9.8304 MHz, DLOOP= 16.384 MHz, DLOOP= ;DLOOP .set ;5-us delay loop 4.032 MIPs ;DLOOP .set ;5-us delay loop MIPs ;DLOOP .set ;5-us delay loop MIPs ;DLOOP .set ;5-us delay loop 16.384 MIPs ;DLOOP .set ;5-us delay loop MIPs ************************* On-chip registers ************************* F_ACCESS0 .set 0FFE0h ;F206 ACCESS CNTRL REGISTER F_ACCESS1 .set 0FFE1h ;F206 ACCESS CNTRL REGISTER PMST .set 0FFE4h ;Defines SARAM PM/DM MP/MC bit. F24X_ACCS .set 0FF0Fh ;F240 ACCESS CNTRL REGISTER. ;Register Declarations F240 Peripherals ;Watch-Dog(WD)/Real Time Int(RTI)/Phase-Locked Loop (PLL) ;Registers RTI_CNTR .set 07021h ;RTI Counter WD_CNTR .set 07023h Counter WD_KEY .set 07025h RTI_CNTL .set 07027h ;RTI Control WD_CNTL .set 07029h Control PLL_CNTL1 .set 0702Bh ;PLL control PLL_CNTL2 .set 0702Dh ;PLL control
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A.1.2 Clear Algorithm, SCLR20.ASM
Assembly Source Algorithms
This code implementation clear (programming) algorithm described section page 3-4. Recall that clear algorithm identical programming algorithm with data forced 0000h flash addresses. Memory section: fl_clr Entry point: GCLR Parameters declared initialized calling code are:
PROTECT defines values bits 8-15 SEG_CTR during clear
algorithm.
SEG_ST defines start address flash array cleared. SEG_END defines address flash array cleared.
Return value: ERROR (@BASE+15); Pass, Fail
CLEAR Subroutine TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.1, 1/31/98 Filename: sclr20.asm Called c2xx_bcx.asm flash application programs. !!CAUTION INITIALIZE BEFORE CALLING THIS ROUTINE!! Function: Clears more contiguous segments array specified following variables. SEG_ST Segment start address SEG_END Segment address PROTECT Sector protect enable algorithm used "row-horizontal", which means that entire flash words) programmed parallel.* This method provides better uniformity programming levels between adjacent bits than each address were programmed independently. algorithm also uses 3-read check VER0 margin (i.e.,the flash location read three times first values discarded.)* This provides low-frequency read-back margin
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Assembly Source Listings Program Examples
Assembly Source Algorithms
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programmed bits. example, flash programmed using CLKOUT period flash read back reliably over CLKOUT period range (6.67 MHz-20 MHz). programming pulse-duration maximum pulses applied row. following resources used temporary storage: Used comparisons Used pulse count Used banz loop. Parameter passed Delay FL_ADRS Used flash address FL_DATA Used flash data. FL_ST Used flash start address BASE_0 Used row-done flag BASE_1 Used start address SPAD1 Flash commands SPAD2 Flash commands .include "svar20.h" MAX_PGM .set ;Only allow pulses row. VER0 .set 010h ;VER0 command. WR_CMND .set ;Write command. WR_EXE .set 045h ;Write EXEBIN command. STOP .set ;Reset command. .def GCLR .ref PROTECT,SEG_ST,SEG_END .ref DELAY,REGS,ARRAY .sect "fl_clr" GCLR: This routine performs clear operation flash array defined FL_ST variable. segments cleared defined SEG_ST, SEG_END, PROTECT variables. following resources used temp storage: Used comparisons Used pulse count Used banz loop FL_ADRS Used flash address FL_DATA Used flash data BASE_0 Used row-done flag BASE_1 Used start address BASE_2 Used byte mask. GCLR: SETC IN;Disable ints. CLRC ;Disable sign extension. SPLK #0,ERROR ;Reset error flag LACL SEG_ST ;Get segment start address. SACL FL_ADRS ;Save current address. #04000h ;Get array start address.
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PRELIMINARY
SACL LACL
Assembly Source Algorithms
FL_ST ;Save array start address. FL_ADRS ;Get segment start address. NEWROW ;********Begin row.* SACL BASE_1 ;Save start address. AR1,#0 ;Init pulse count zero. SAMEROW ;********Same row, next pulse.* SPLK #1,BASE_0 ;Set done flag 1(True). LACL BASE_1 ;Get start address. SACL FL_ADRS ;Save current address. AR2,#31 ;Init index. ********Repeat following code times until row.* LOBYTE ;********First, byte.* SPLK #0FFh,BASE_2 ;Get lo-byte mask. CALL PRG_BYTE ;Check/Program lo-byte SPLK #0FF00h,BASE_2 ;Get hi-byte mask. CALL PRG_BYTE ;Check/Program hi-byte. NEXTWORD ;********Next word row. LACL FL_ADRS ;Load address next word. ;Increment address. SACL FL_ADRS ;Save current address. *,AR2 ;Point index. BANZ LOBYTE next word,and AR2. ********Reached row. Check done.* BASE_0,15 ;Get row_done flag. BCND ROW_DONE,TC then done. *,AR1 ;Else, done, ;inc pulse count. AR0,#MAX_PGM ;Check passed allowable max. CMPR AR1>MAX_PGM, then BCND EXIT,TC ;fail, don't continue. SAMEROW ;else, beginning same row. ********If done, then check Array done.* ROW_DONE ;Check array. SEG_END ;Subtract segment address. BCND DONE,GEQ then done. ********Else, next row.* LACL FL_ADRS ;Get current address. NEWROW ;Start row. ********If here, then done. DONE CALL ARRAY ;Access flash array mode. ********If here, then unit failed program.* EXIT SPLK #1,ERROR ;Update error flag. DONE ;Get outa here. .page THIS SECTION PROGRAMS VALUE STORED FL_DATA INTO FLASH ADDRESS DEFINED FL_ADRS. following resources used temporary storage: Parameter passed Delay. SPAD1 Flash program STOP commands.
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Assembly Source Listings Program Examples
Assembly Source Algorithms
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SPAD2 Flash program command. EXE_PGM CALL ARRAY ;ACCESS ARRAY *LOAD WADRS WDATA LACL FL_ADRS ;ACC PROGRAM ADRS TBLW FL_DATA ;LOAD WADRS WDATA CALL REGS ;ACCESS FLASH REGS *SET WRITE COMMAND WORDS LACL PROTECT ;GET SEGMENT PROTECT MASK #WR_CMND WRITE COMMAND SACL SPAD1 ;SPAD1 WRITE COMMAND #WR_EXE EXEBIN COMMAND SACL SPAD2 ;SPAD2 WRITE COMMAND LACL FL_ST ;ACC (FLASH0) ACTIVATE WRITE TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT EXEBIN TBLW SPAD2 ;EXECUTE COMMAND AR6,#D100 ;SET DELAY CALL DELAY,*,AR6 ;WAIT STOP WRITE OPERATION SPLK #0,SPAD1 ;SHUTDOWN WRITE OPERATION TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT ;RETURN CALLING SEQUENCE* .page ACTIVATE VER0 FLASH READS LOADS FLASH WORD ADDR FL_ADRS FL_DATA. Uses SPAD1 temporary storage flash commands. SET_RD_VER0 CALL REGS ;ACCESS FLASH REGISTERS LACL FL_ST ;ACC FLASH SPLK #VER0,SPAD1 ;ACTIVATE VER0 TBLW SPAD1 ;EXECUTE COMMAND* AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY LACL FL_ADRS ;POINT ADRS TBLR FL_DATA ;GET FLASH WORD read TBLR FL_DATA read TBLR FL_DATA read CALL REGS ;ACCESS FLASH REGISTERS LACL FL_ST ;ACC FLASH SPLK #STOP,SPAD1 ;DEACTIVATE VER0
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Assembly Source Algorithms
TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY ;RETURN CALLING SEQUENCE* PRG_BYTE: Programs byte depending byte mask (BASE_2). PRG_BYTE: CALL SET_RD_VER0 ;Read word VER0 level. LACL BASE_2 ;Get lo/hi byte mask. FL_DATA ;Xor with read-back value. BCND PB_DONE,EQ zero, then done. #0FFFFh ;else, mask good bits. SACL FL_DATA ;New data. CALL EXE_PGM ;PGM Pulse. SPLK #0,BASE_0 ;Set done flag 0(False). PB_DONE .end
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Assembly Source Listings Program Examples
Assembly Source Algorithms
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A.1.3 Erase Algorithm, SERA20.ASM
This code implementation erase algorithm described section page 3-10. Memory section: fl_ers Entry point: GERS Parameters declared initialized calling code are:
PROTECT defines values bits 8-15 SEG_CTR during erase
algorithm.
SEG_ST defines start address flash array erased. SEG_END defines address flash array erased.
Return value: ERROR (@BASE+15); Pass, Fail
ERASE subroutine TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.1, 1/31/98 Filename: sera20.asm Called c2xx_bex.asm flash application programs. !!CAUTION INITIALIZE BEFORE CALLING THIS ROUTINE!! Function: Erases more contiguous segments flash array specified following variables. SEG_ST Segment start address SEG_END Segment address PROTECT Sector protect enable algorithm used XOR-VER1, which means that addition VER1 read mode, readback used gain more margin. During read portion erase, reads performed each address; first read, address bits complemented using logical with array address. data read during first read discarded, second read performed actual address. This scheme simulates worst-case branching condition code executing from flash array. A-10
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Assembly Source Algorithms
erase pulse duration 7ms, maximum 1000 pulses applied array. following resources used temporary storage: Used comparisons Used erase pulse count Used main banz loop Parameter passed DELAY BASE_0 Parameter passed Set_mode BASE_1 Used flash address. BASE_2 Used flash data BASE_3 Used flash checksum BASE_4 Used segment size BASE_5 Flash Erase command BASE_6 Flash Erase+EXE command .include "svar20.h" ;defines variables flash0 flash1 array MAX_ER .set 1000 ;Allow only 1000 erase pulses. VER1 .set ;VER1 command. ER_CMND .set ;ERASE COMMAND WORD ER_EXE .set 043h ;ERASE EXEBIN COMMAND WORD INV_ER .set 018h ;INVERSE ERASE COMMAND WORD FL_WR .set ;FLASH WRITE COMMAND WORD FLWR_EX .set 047h ;FLASH WRITE EXEBIN COMMAND WORD STOP .set ;RESET REGISTER COMMAND WORD .def GERS .ref PROTECT,SEG_ST,SEG_END .ref DELAY,REGS,ARRAY .sect "fl_ers" GERS: This routine performs erase xorver1 level. erase defined vars SEG_ST SEG_END. following resources used temporary storage: Used comparisons Used erase pulse count Used main banz loop BASE_0 Parameter passed Set_mode BASE_1 Used flash address. BASE_2 Used flash data BASE_3 Used flash checksum BASE_4 Used segment size GERS: Code initialization section Initialize test loop counters: number ERASE pulses. SETC IN;Disable maskable ints. SETC ;Enable sign extension.
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Assembly Source Listings Program Examples
A-11
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CLRC ;Disable overflow mode. LACL SEG_ST ;Get segment start address. #04000h ;Get array start address. SACL FL_ST ;Save array start address. #03FFFh ;Get array address. SACL FL_END ;Save array address. SPLK #0,ERROR ;Reset error flag AR1,#0 ;Set erase count SPLK #STOP, BASE_0 ;Stop command. CALL SET_MODE ;Disable flash cmds. XOR_ERASE Compute checksum flash, using address complementing.** LACC SEG_END SEG_ST BASE_4 ;Segment length-1. AR2,BASE_4 ;load loop times. SACL BASE_4 ;Segment length. SPLK #VER1,BASE_0 ;VER1 command. CALL SET_MODE ;Set VER1 mode. *,AR2 BLDD #SEG_ST,BASE_1 ;Segment start address. SPLK #0,BASE_3 ;Clear checksum. RD1_LOOP ;For SEG_ST SEG_END. LACC BASE_1 ;ACC CURRENT ADDR. FL_END ;XOR addr with flash addr. TBLR BASE_2 ;Dummy Read. LACC BASE_1 ;Get actual addr again. TBLR BASE_2 ;True Read. ;Increment flash addr. SACL BASE_1 ;Store next read. LACC BASE_3 ;Get check sum. BASE_2 ;ACC=>ACC+FL_DATA. SACL BASE_3 ;Save check sum. BANZ RD1_LOOP,*- BASE_4 ;Should make ;erased array. BCND XOR_ERFIN,EQ BASE_3 finished. ***** erased, apply erase pulse. CALL ERASE_A ;Else, pulse again. *,AR1 ;ARP->AR1 (Erase pulse count) ;Increment Erase count. AR0,#MAX_ER CMPR2 AR1>MAX_ER then BCND EXIT,TC ;fail, don't continue erasing. XOR_ERASE ;Else, check again. ***** here, then erase passed; check depletion. XOR_ERFIN SPLK #STOP, BASE_0 ;Stop command. CALL SET_MODE ;Disable flash cmds. CALL INV_ERASE ;Check depletion. DONE ;Return calling code. A-12
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***** here, then error occurred. EXIT SPLK #1,ERROR ;Update error flag SPLK #STOP,BASE_0 ;Stop command. CALL SET_MODE ;Disable flash cmds. DONE ;Get outa here. .page SET_MODE: This routine sets flash mode specified contents BASE_0. This used VER0,VER1,INVERASE, STOP. AR6: Parameter passed DELAY. SET_MODE CALL REGS ;ACCESS FLASH REGS LACL FL_ST ;ACC SEG_CTR. TBLW BASE_0 ;Activate MODE. AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY INV_ERASE: This routine used check depletion flash array. Used main banz loop BASE_0 Parameter passed Set_mode BASE_1 Used flash address BASE_2 Used flash data INV_ERASE SPLK #INV_ER,BASE_0 CALL SET_MODE ;Set inverse-erase mode. BLDD #FL_ST,BASE_1 ;Array start address. AR2,#31 ;Loop count. *,AR2 NEXT_IVERS LACL BASE_1 ;Get address. TBLR BASE_2 ;Dummy read. TBLR BASE_2 ;Read data. ;Increment address. SACL BASE_1 ;Save address. BASE_2 ;Add data. BCND EXIT,NEQ ACC<>0, then fail. *Else continue, until until done with row. BANZ NEXT_IVERS ;Loop times. SPLK #STOP,BASE_0 ;Stop command. CALL SET_MODE ;Disable flash cmds. here then test passed. .page ERASE_A: This subroutine applies erase pulse flash array.
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Assembly Source Listings Program Examples
A-13
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following resources used temporary storage: BASE_0 Flash STOP command, FFFF WDATA. BASE_5 Flash erase command. BASE_6 Flash erase command. ERASE_A FLASH ERASE COMMANDS PROTECT MASK. LACL PROTECT ;GET SEGMENT PROTECT MASK #ER_CMND ERASE COMMAND SACL BASE_5 ;BASE_5 ERASE COMMAND #ER_EXE EXEBIN COMMAND SACL BASE_6 ;BASE_6 ERASE COMMAND MUST LOAD WDATA WITH FFFF. SPLK #0FFFFh,BASE_0 ;WDATA VALUE ERASE LACC FL_ST ;ACC FLASH TBLW BASE_0 ;SET WDATA FFFF THIS SECTION ACTIVATES WRITE COMMAND. SPLK #STOP,BASE_0 ;Stop command. CALL SET_MODE ;Disable flash cmds. CALL REGS ;ACCESS FLASH REGS LACC FL_ST ;ACC FLASH TBLW BASE_5 ;ACTIVATE ERASE AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT THIS SECTION ACTIVATES EXEBIN COMMAND. TBLW BASE_6 ;START ERASURE AR6,#D7K ;SET DELAY CALL DELAY,*,AR6 ;WAIT SPLK #STOP,BASE_0 ;STOP COMMAND CALL SET_MODE ;STOP ERASE ;RETURN CALLING CODE .end
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A.1.4 Flash-Write Algorithm, SFLW20.ASM
Assembly Source Algorithms
This code implementation flash-write algorithm described section page 3-14. Memory section: fl_wrt Entry point: FLWS Parameters declared initialized calling code are:
PROTECT defines values bits 8-15 SEG_CTR during flash-
write algorithm.
SEG_ST defines start address flash array recovered. SEG_END defines address flash array recovered.
Return value: ERROR (@BASE+15) 0=Pass, 1=Fail
FLASH-WRITE subroutine TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.1, 1/31/98 Filename: sflw20.asm Called c2xx_bfx.asm flash application programs. !!CAUTION INITIALIZE BEFORE CALLING THIS ROUTINE!! Function: Performs flash writes flash array specified following vars: SEG_ST Array segment start address PROTECT Sector protect enable flash-write pulse duration used maximum 10000 pulses applied until device passes depletion test. following resources used temp storage: Used comparison Flash-Write Pulse Count Used main BANZ loop Parameter passed DELAY BASE_0 Parameter passed SET_MODE BASE_1 Used flash address BASE_2 Used flash data
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BASE_3 Used .include "svar20.h" ;defines variables flash0 flash1 array MAX_FLW .set 10000 ;Allow only 10000 pulses. INV_ER .set 018h ;INVERSE ERASE COMMAND WORD FLWR .set ;FLASH WRITE COMMAND WORD FLWR_EX .set 047h ;FLASH WRITE EXEBIN COMMAND WORD STOP .set ;RESET REGISTER COMMAND WORD .def FLWS .ref PROTECT,SEG_ST,SEG_END .ref DELAY,REGS,ARRAY .sect "fl_wrt" FLWS: This routine used check bits depletion mode. found, flash- write used recover. Flash-write pulse count. Used main banz loop. BASE_0 Parameter passed Set_mode. BASE_1 Used flash address. BASE_2 Used flash data. FLWS: Code initialization section Initialize test loop counters: number flash-write pulses. SETC IN;Disable maskable ints. LACL SEG_ST ;Get segment start address. #04000h ;Get array start address. SACL FL_ST ;Save array start address. SPLK #0,ERROR ;Reset error flag. AR1,#0 ;Set count SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. INV_ERASE SPLK #INV_ER,BASE_0 CALL SET_MODE ;Set inverse-erase mode. BLDD #FL_ST,BASE_1 ;Array start address. AR2,#31 ;Loop count. *,AR2 NEXT_IVERS LACL BASE_1 ;Get address. TBLR BASE_2 ;Dummy read. TBLR BASE_2 ;Dummy read. TBLR BASE_2 ;Read data. ;Increment address. SACL BASE_1 ;Save address. BASE_2 ;Add data. A-16
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Assembly Source Algorithms
BCND FL_WRITE, ACC<>0, then flwrite. *Else, continue until until done with row. BANZ NEXT_IVERS ;Loop times. SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. here then test passed. DONE ;Return calling code. here, then error occurred. EXIT SPLK #1,ERROR ;Update error flag SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. CALL ARRAY ;ACCESS FLASH ARRAY DONE ;Get outa here. .page FL_WRITE: This routine performs fl_write flash until maximum reached. array defined variable FL_ST segment(s) defined PROTECT mask. following resources used temporary storage: Used comparison Used pulse count (Global) Parameter passed DELAY BASE_0 Parameter passed SET_MODE BASE_2 Used BASE_3 Used FL_WRITE SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. LACL PROTECT ;Get sector_prot mask. #FLWR fl_write cmd. SACL BASE_2 ;BASE_2 fl_write cmd. #FLWR_EX fl_write cmd. SACL BASE_3 ;BASE_3 fl_write cmd. *Set flash-write command. CALL REGS ;Access flash regs. LACC FL_ST ;ACC SEG_CTL. TBLW BASE_2 ;Initiate fl_write. AR6,#D10 ;Set delay. CALL DELAY,*,AR6 ;Wait,10US stabilization time. *Set (start flash-write pulse). TBLW BASE_3 ;Start pulse. AR6,#D7K ;Set delay CALL DELAY,*,AR6 ;WAIT,7 AR6,#D7K ;Set delay CALL DELAY,*,AR6 ;WAIT 14-mS flash write pulse been applied. SPLK #STOP,BASE_0 ;Flash STOP command. CALL SET_MODE ;Disable flash commands. *,AR1 ;Increment count.
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AR0,#MAX_FLW CMPR AR1>MAX_FLW then BCND EXIT,TC ;Fail, don't continue recovery. INV_ERASE ;Else, perform iverase again. SET_MODE: This routine sets flash mode specified contents BASE_0. This used VER0,VER1,INVERASE,or STOP. SET_MODE CALL REGS ;ACCESS FLASH REGS LACL FL_ST ;ACC SEG_CTR. TBLW BASE_0 ;Activate MODE. AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY .end
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A.1.5 Programming Algorithm, SPGM20.ASM
Assembly Source Algorithms
This code implementation program algorithm described section page 3-4. Memory section: fl_prg Entry point: GPGMJ Parameters declared initialized calling code are:
PRG_bufaddr defines destination start address. PRG_length defines source buffer length. PRG_paddr defines source buffer start address (data space). PROTECT defines values bits 8-15 SEG_CTR during pro-
gramming algorithm. Return value: ERROR (@BASE+15); Pass, Fail
PROGRAM Subroutine TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.0b, 12/5/97 Revision: 2.1, 1/31/98 Filename: spgm20.asm Called c2xx_bpx.asm flash application programs. !!CAUTION INITIALIZE BEFORE CALLING THIS ROUTINE!! Function: This routine programs part flash specified variables: PRG_paddr Destination start address PRG_length Source buffer length PRG_bufaddr Source buffer start address algorithm used "row-horizontal", which means that entire flash words) programmed parallel.* This method provides better uniformity programming levels between adjacent bits than each address were programmed independently. algorithm also uses 3-read check VER0 margin (i.e., flash location read three times first values discarded.)* This provides low-freq read-back margin programmed
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bits. example, flash programmed using CLKOUT period flash reliably read back over CLKOUT period range (6.67MHz-20 MHz). programming pulse duration maximum pulses applied row. following variables used temp storage: Used comparisons Used pulse count Used banz loop Used buffer addr index Used flash address. Parameter passed Delay SPAD1 Flash program STOP commands SPAD2 Flash program command FL_ADRS Used flash address FL_DATA Used flash data BASE_0 Used row-done flag BASE_1 Used start address BASE_2 Used length-1 BASE_3 Used buffer/row start addr BASE_4 Used destination addr BASE_5 Used byte mask .include "svar20.h" MAX_PGM .set ;Allow only pulses row. VER0 .set 010h ;VER0 command. WR_CMND .set ;Write command. WR_EXE .set 045h ;Write EXEBIN command. STOP .set ;Reset command. .def GPGMJ .ref .ref PROTECT,DELAY,REGS,ARRAY .sect "fl_prg" GPGMJ: This routine programs part flash specified variables: PRG_paddr Destination start address PRG_length Source buffer length PRG_bufaddr Buffer start address following variables used temp storage: Used comparisons Used pulse count Used banz loop Used buffer addr index FL_ADRS Used flash address FL_DATA Used flash data BASE_0 Used row-done flag BASE_1 Used start address BASE_2 Used length-1 A-20
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Assembly Source Algorithms
BASE_3 Used buffer/row start addr BASE_4 Used destination addr BASE_5 Used byte mask GPGMJ: SPLK #0,IMR ;MASK INTERRUPTS SETC IN;GLOBALLY MASK INTERRUPTS SPLK #0,ERROR ;Initialize error flag error). LACL PRG_paddr ;Get destination start address. SACL FL_ADRS ;Save current address. PRG_length ;Determine destination addr. SACL BASE_4 ;Save destination addr. LACL PRG_paddr ;Get destination start addr. AR3,PRG_bufaddr ;Get buffer start address. ********Begin row.* NEWROW SACL BASE_1 ;Save start address. AR3,BASE_3 ;Save buffer/row start address. AR1,#0 ;Init pulse count zero. SPLK #31,BASE_2 ;Init length-1 #001Fh start addr boundary? ADJ_ROW,NEQ then adjust length. LACL BASE_1 ;Get start address. #001Fh ;Get address. BASE_4 address boundary? ADJ_ROW,GT then adjust length. ********Same row, next pulse.* SAMEROW SPLK #1,BASE_0 ;Set done flag 1(True). LACL BASE_1 ;Get start address. SACL FL_ADRS ;Save current address. AR3,BASE_3 ;Get buffer/row start addr. AR2,BASE_2 ;Init index. Repeat following code times until row.* LOBYTE ;********First, byte.* CALL SET_MODULE,AR4 ;Determine which flash module. SPLK #0FFh,BASE_5 ;Set lo-byte mask. CALL PRG_BYTE ;Check/Program lo-byte. SPLK #0FF00h,BASE_5 ;Set hi-byte mask. CALL PRG_BYTE ;Check/Program hi-byte. NEXTWORD ;********Next word row. LACL FL_ADRS ;Load address next word. ;Increment address. SACL FL_ADRS ;Save current address. *,AR3 ;ARP buffer addr index. *+,AR2 ;Inc, index. BANZ LOBYTE next word,and AR2. Reached row. Check done. BASE_0,15 ;Get row_done flag. BCND ROW_DONE,TC then done. *,AR1 ;Else, done, ;inc pulse count. AR0,#MAX_PGM ;Check passed allowable max. CMPR AR1>MAX_PGM then
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BCND EXIT,TC SAMEROW
;fail, don't continue. ;else, beginning same row. done, then check Array done. ROW_DONE LACL FL_ADRS ;Check array. BASE_4 ;Subtract addr. BCND DONE, then done. Else, next row. LACL FL_ADRS NEWROW ;Start row. here, then done. DONE CALL ARRAY ;Access flash array mode. ;Return calling program. here, then unit failed program. EXIT SPLK #1,ERROR ;Update error flag (error). DONE ;Get outa here. .page ADJ_ROW: This routine used adjust length, start address code being programmed does fall boundary. length passed BASE_2 variable, adjustment value subtracted passed accumulator. ADJ_ROW ;Take twos complement. BASE_2 ;Add length. SACL BASE_2 ;Save length. SET_MODULE: This routine used point appropriate flash array control register This only important 'F2XX devices with multiple flash modules like 320F206. variable FL_ST returned with correct register address. following resources used temporarily: Used comparisons Used flash address SET_MODULE AR4,FL_ADRS ;AR4 current address. SPLK #0,FL_ST ;FL_ST FLASH0 CTRL REGS AR0,#4000H ;AR0 compare value. CMPR then ;FL_ADRS 4000H; BCND FL0,TC ;Address FL0. ;Else address FL1. A-22
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SPLK #04000h,FL_ST ;FL_ST FLASH1 CTRL REGS .page THIS SECTION PROGRAMS VALUE STORED FL_DATA INTO FLASH ADDRESS DEFINED FL_ADRS. following resources used temporary storage: Parameter passed Delay SPAD1 Flash program STOP commands SPAD2 Flash program command. EXE_PGM CALL ARRAY ;ACCESS ARRAY LOAD WADRS WDATA LACL FL_ADRS ;ACC PROGRAM ADRS TBLW FL_DATA ;LOAD WADRS WDATA CALL REGS ;ACCESS FLASH REGS WRITE COMMAND WORDS LACL PROTECT ;GET SEGMENT PROTECT MASK #WR_CMND WRITE COMMAND SACL SPAD1 ;SPAD1 WRITE COMMAND #WR_EXE EXEBIN COMMAND SACL SPAD2 ;SPAD2 WRITE COMMAND LACL FL_ST ;ACC (FLASH) ACTIVATE WRITE TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT EXEBIN TBLW SPAD2 ;EXECUTE COMMAND AR6,#D100 ;SET DELAY CALL DELAY,*,AR6 ;WAIT STOP WRITE OPERATION SPLK #0,SPAD1 ;SHUT DOWN WRITE OPERATION TBLW SPAD1 ;EXECUTE COMMAND TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT ;RETURN CALLING SEQUENCE .page ACTIVATE VER0 FLASH READS LOADS FLASH WORD ADDR FL_ADRS FL_DATA. Uses SPAD1 temporary storage flash commands. SET_RD_VER0 CALL REGS ;ACCESS FLASH REGISTERS
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LACL FL_ST ;ACC FLASH SPLK #VER0,SPAD1 ;ACTIVATE VER0 TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY LACL FL_ADRS ;POINT ADRS TBLR FL_DATA ;GET FLASH WORD read TBLR FL_DATA read TBLR FL_DATA read CALL REGS ;ACCESS FLASH REGISTERS LACL FL_ST ;ACC FLASH SPLK #STOP,SPAD1 ;DEACTIVATE VER0 TBLW SPAD1 ;EXECUTE COMMAND AR6,#D10 ;SET DELAY CALL DELAY,*,AR6 ;WAIT CALL ARRAY ;ACCESS FLASH ARRAY ;RETURN CALLING SEQUENCE .page PRG_BYTE: Programs byte depending byte mask (BASE_5). PRG_BYTE: CALL SET_RD_VER0 ;Read word VER0 level. *,AR3 ;ARP buffer addr index. LACL ;Get word program. FL_DATA ;Xor with read-back value. BASE_5 ;Mask hi/lo byte. BCND PB_END,EQ zero then done. #0FFFFh ;else, mask good bits. SACL FL_DATA ;New data. CALL EXE_PGM ;PGM Pulse. SPLK #0,BASE_0 ;Set done flag 0(False). PB_END .end
A-24
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A.1.6 Subroutines Used Four Algorithms, SUTILS20.ASM
This assembly file includes subroutines that change flash module access mode subroutine that performs software delays. More details individual functions given comments.
Delay Access Mode Subroutines TMS320F2XX Flash Utilities. Revision: 2.0, 9/10/97 Revision: 2.1, 1/31/98 Filename: sutils20.asm Called These utilities used CLEAR,ERASE, PROGRAM algorithms written F2xx devices. Function: DELAY Delay loop specified AR6. REGS Clears MODE F_ACCESS0/1 access flash module control registers. ARRAY Sets MODE F_ACCESS0/1 access flash array. .include "svar20.h" .def DELAY,REGS,ARRAY .sect "DLY" *Delays follows: AR6,#N Cycles CALL DELAY Cycles #DLOOP 2*(N+1) Cycles DLOOP*(N+1) Cycles BANZ DLY_LP 4*N+2 Cycles Cycles ------------------------ DLOOP(N+1)+6*N+14 Cycles DLOOP appropriately desired delay. DELAY ;AR6 OUTER LOOP COUNT DLY_LP #DLOOP ;APPROX DELAY BANZ DLY_LP,*- ;LOOP UNTIL DONE ;RETURN CALLING SEQUENCE .page REGS Clears MODE F_ACCESS0/1 access flash module control registers. .sect "REG" REGS
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SPLK #0000h,SPAD2 ***********The next instruction F240 only************* F24X ;Assemble F24X only. SPAD2,F24X_ACCS ;Enable F240 flash mode. ;SPAD1 dummy value. .endif F24X ;Assemble F206 only. LACC FL_ST #4000h BCND reg1,geq address>= 4000h,set ;set mode flash1 array SPAD2,F_ACCESS0 ;Change mode flash0. reg1 SPAD2,F_ACCESS1 ;Change mode flash1. .endif ;RETURN CALLING SEQUENCE .page ARRAY Sets MODE F_ACCESS0/1 access flash array. .sect "ARY" ARRAY SPLK #0001h,SPAD2 ***********The next instruction F240 only************* F24X ;Assemble F240 only. SPAD1,F24X_ACCS ;Enable F240 flash array mode. ;SPAD1 dummy value. .endif F24X ;Assemble F206 only. LACC FL_ST #4000h BCND ary1,geq address>= 4000h,set ;set mode flash1 array SPAD2,F_ACCESS0 ;Change mode flash0. ary1 SPAD2,F_ACCESS1 ;Change mode flash1. .endif ;RETURN CALLING SEQUENCE
.end
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C-Callable Interface Flash Algorithms
C-Callable Interface Flash Algorithms
functions erase() program() intended in-application programming 'F20x/F24x flash module. These functions were written callable, they also called from assembly long stack calling convention used.
This file contains C-callable functions: program(), erase() These functions used programming erasing on-chip flash EEPROM 'F2XX product family. functions provide C-callable, interface standard 'F2XX flash algorithms. They also used from assembly code, long stack calling convention used. Since standard flash algorithms actually used perform various flash operations, they must must combined with this code link time. erase function includes operations (clear+erase+flw) required prepare flash programming. addition providing C-callable interface, this function very useful since provides single call erase flash memory. Since programming device requires single algorithm, only purpose program() function provide C-callable interface. program() function transfers specified block data memory into specified, erased flash array. parameters each function described detail below. Note these functions cannot reside same flash module that they meant modify. 10/29/97 Ruben Perez Applications Team Texas Instruments, Inc. 03/20/98 Updated inclusion flash technical reference. .title "C-callable Interface 'F2XX Flash Algorithms**" ;**C-callable functions defined this file. .global _erase, _program
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;**Variables included from flash algorithms. .include "svar20.h" ;Variable declarations .ref GCLR ;References clear algo. .ref GPGMJ ;References program algo. .ref GERS ;References erase algo. .ref FLWS ;References flash-write algo. ;**Parameters used flash algorithms. .def PRG_bufaddr, PRG_paddr .def PRG_length, PARMS .def SEG_ST,SEG_END,PROTECT VARS: .usect "PRG_data",16 ;This uninitialized data ;section required standard ;flash algos temporary ;variables. Pointers this ;space hardcoded SVAR20.H, ;and variables init'd ;run time. PARMS: .usect "PRG_parm",10 ;This uninitialized data ;section used temporary ;variables passing ;parameters flash ;algorithms. PROTECT .set PARMS ;Segment enable bits. ***** Parameters needed Programming algorithm. ******** PRG_bufaddr .set PARMS+1 ;Addr buffer data PRG_paddr .set PARMS+2 ;First flash addr program PRG_length .set PARMS+3 ;Length block program Parameters needed CLEAR, ERASE, algorithms. SEG_ST .set PARMS+4 ;Segment start address. SEG_END .set PARMS+5 ;Segment address. **** Other misc variables. **** ERS_COUNT .set PARMS+6 ;Used erase fail count. SV_AR1 .set PARMS+7 ;Used save AR1. .sect "PRG_text" function erase(PROTECT,SEG_ST,SEG_END) Status returned accumulator. Fail,1 Pass This function performs clear erase operation 'F2XX flash. erase operation fails, flash-write operation used recover from depletion. array recovers, entire process (clr+ers+flw) repeated maximum times. return value indicates status. this function A-28
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C-Callable Interface Flash Algorithms
passes, flash ready reprogrammed. operations performed segments flash module described parameter list: 1)PROTECT-defines which flash segments protect.* 2)SEG_ST -start address segment erased. 3)SEG_END-end address segment erased. erase flash0 erase(0xff00,0x0000,0x3fff). erase flash1 erase(0xff00,0x4000,0x7fff). CAUTION: Erasing individual segments allowed. PROTECT parameter should always enable segments, SEG_ST SEG_END should start address array erased. _erase: ERS_PARAMS .set AR_STACK .set AR_PROTECT .set AR_SEG_ST .set AR_SEG_END .set ;Begin Preprocessing POPD ;pop return address, push software stack ar0,*+ ;save ar6,* ;save sbrk ;get arguments place them properly take them from ;the software stack place them into their correct ;positions AR_PROTECT,*- AR_SEG_ST,*- AR_SEG_END,*- adrk #ERS_PARAMS+4 ;ar1 next empty point stack (SP) ;End Preprocessing #PARMS AR1,SV_AR1 ;Save AR1. SPLK #0,ERS_COUNT ;Set erase fail count SPLK #0,ERROR ;Set algo error flag errors). **********Put parameters where they belong.********** AR_PROTECT,PROTECT AR_SEG_ST,SEG_ST AR_SEG_END,SEG_END ***********Next Setup clear flash ************ ers_loop: CALL GCLR ;Clear flash. LACL ERROR ;Check CLEAR/ERASE error BCND ers_error,neq error, then hard fail. ***********Next Setup erase flash ************ CALL GERS ;Erase flash. LACL ERROR ;Check CLEAR/ERASE error BCND depletion,neq error, Flash-write. LACL ;Else, errors erasing. ers_done ;Restore registers return. depletion: LACL ERS_COUNT ;Get erase fail count.
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;Increment fail count. SACL ERS_COUNT ;Save count. ;CHECK BCND ers_error,GT ers_cout>10 then hard fail. CALL FLWS ;Else, recover from depletion. LACL ERROR ;Check FLASH-WRITE error. BCND ers_error,neq couldn't recover, then hard fail. ers_loop ;Else, erase again. ers_error: LACL ;Error while erasing. ers_done: AR1,SV_AR1 ;Restore AR1. CLRC ;Disable overflow. ;Begin Post Processing *,ar1 sbrk ar6,*- ;save ar0,*- ;save pshd ;pop return address, push stack ;End Post Processing *****************END function PRG_length) Status will returned accumulator. Fail, Pass This function performs program operation 'F2XX flash. values programmed will read from buffer data memory. function program* words flash single call; restricted only data buffer size. function passes, flash programmed correctly. function controlled following parameter list: 1)PROTECT -flash segments protect. 2)PRG_bufaddr -Start address program buffer data memory. 3)PRG_paddr -Start address flash locations programmed. 4)PRG_length -Number words programmed. program words flash1 starting address 0x4020, from buffer 0x0800@data this: _program: PRG_PARAMS .set AR_STACK .set ;**Parameters popped from stack. AR_PROTECT .set AR_bufaddr .set AR_paddr .set AR_length .set A-30
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C-Callable Interface Flash Algorithms
;Begin Preprocessing POPD return address, push stack ar0,*+ save ar6,* save sbrk Local variables (and parameters) follows: ;get arguments place them properly take them from ;the software stack place them into their correct ;positions AR_PROTECT,*- AR_bufaddr,*- AR_paddr,*- AR_length,*- adrk #PRG_PARAMS+4 next empty point stack (SP) Preprocessing #PARMS AR1,SV_AR1 ;Save AR1. SPLK #0,ERROR ;Set algo error flag ;(no errors). **********Put parameters where they belong.********** AR_PROTECT,PROTECT AR_bufaddr,PRG_bufaddr AR_paddr,PRG_paddr AR_length,PRG_length ***********Next, program flash ************ CALL GPGMJ ;Program flash from buffer. LACL ERROR ;Check program error. BCND prg_error,neq error then clear ACC. LACL ;Else, errors programming. prg_done prg_error: LACL ;Error while programming. prg_done: AR1,SV_AR1 ;Restore AR1. CLRC ;Disable overflow. ;Begin Post Processing *,ar1 sbrk ar6,*- ;save ar0,*- ;save pshd ;pop return address, push stack ;End Post Processing *****************END
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Assembly Source Listings Program Examples
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Sample Assembly Code Erase Reprogram TMS320F206
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Sample Assembly Code Erase Reprogram TMS320F206
algorithm files used from assembly straightforward manner. general, algorithms reside anywhere program space. However, algorithms cannot executed from flash module that being modified, algorithms must execute with zero wait states. assembly code linker command file this section provide working example 'F206. this example, algorithms reside SARAM, flash1 erased reprogrammed.
A.3.1 Assembly Code TMS320F206
Filename: ASMEXAMP.ASM Description: This file contains example erase program TMS320F206 flash from assembly code using standard flash algorithm modules. example erases 'F206 flash modules, then programs first three words. Since standard flash algorithms actually used perform various flash operations, they must must combined with this code link time. 03/20/98 Updated inclusion flash technical reference. .title "**Example Using 'F2XX Flash Algorithms**" ;**Variables included from flash algorithms. .include "svar20.h" ;Variable declarations .ref GCLR ;References clear algo. .ref GPGMJ ;References program algo. .ref GERS ;References erase algo. .ref FLWS ;References Flash-write algo. ;**Parameters used flash algorithms. .def PRG_bufaddr, PRG_paddr .def PRG_length, PARMS .def SEG_ST,SEG_END,PROTECT VARS: .usect "PRG_data",16 ;This uninitialized ;data section required ;the standard flash algos ;for temporary variables. ;Pointers this space ;are hardcoded SVAR20.H, ;and variables ;init'd time. PARMS: .usect "PRG_parm",10 ;This uninitialized
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Sample Assembly Code Erase Reprogram TMS320F206
;data section used ;temporary variables, ;for passing parameters flash algorithms. PROTECT .set PARMS ;Segment enable bits. ***Parameters needed Programming algorithm. PRG_bufaddr .set PARMS+1 ;Address buffer ;program data. PRG_paddr .set PARMS+2 ;First flash address ;program. PRG_length .set PARMS+3 ;Length block program. Parameters needed CLEAR, ERASE, algorithms. SEG_ST .set PARMS+4 ;Segment start address. SEG_END .set PARMS+5 ;Segment address. **** Other misc variables. **** ERS_COUNT .set PARMS+6 ;Used erase fail count. .text First, erase flash1 invoking clear erase algorithms. Note: three parameters must initialized before calling algorithms. #PARMS SPLK #0,ERS_COUNT ;Set erase fail count **********Put parameters where they belong.********** SPLK #0ff00h,PROTECT SPLK #04000h,SEG_ST SPLK #07FFFh,SEG_END ***********First clear flash ************ ers_loop: CALL GCLR ;Clear flash. LACL ERROR ;Check CLEAR error BCND ers_error,neq error, then hard fail. ***********Next erase flash ************ CALL GERS ;Erase flash. LACL ERROR ;Check CLEAR error BCND depletion,neq error, then ;flash-write. ers_done ;Else, errors erasing. depletion: LACL ERS_COUNT ;Get erase fail count. ;Increment fail count. SACL ERS_COUNT ;Save count.
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Assembly Source Listings Program Examples
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Sample Assembly Code Erase Reprogram TMS320F206
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BCND ers_error,GT CALL LACL BCND
;CHECK ers_cout>10 then hard ;fail. FLWS ;Else, recover from ;depletion. ERROR ;Check FLASH-WRITE error. ers_error,neq couldn't recover, then ;hard fail. ers_loop ;Else, erase again.
ers_error: here, then unrecoverable error occurred during erase. actual application, system** takes some action indicate that service required. ers_error ;Error while erasing. ers_done: here, then flash erased ready reprogrammed. This good place example breakpoint that erasure verified (i.e., flash bits should this point, actual application fills buffer with data programmed. simulate this example, three SARAM locations initialized. AR1, #0c00h ;Using last SARAM ;buffer. *,AR1 SPLK #0AAAAh,*+ ;Use dummy data buffer. SPLK #05555h,*+ SPLK #0AAAAh,* that data programmed ready, programming algorithm invoked. Note that four parameters must initialized before calling algorithm. #PARMS **********Put parameters where they belong.********** splk #0ff00h,PROTECT splk #0c00h,PRG_bufaddr splk #04000h,PRG_paddr splk #3,PRG_length ***********Next program flash ************ CALL GPGMJ ;Program flash from buffer. LACL ERROR ;Check program error. BCND prg_error,neq error then clear ACC. prg_done ;Else, errors programming.
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Sample Assembly Code Erase Reprogram TMS320F206
prg_error: here, then error occurred during programming. actual application, system takes some action indicate that service required. prg_error ;Error while programming. prg_done: ********* here, then flash been successfully programmed. prg_done ;Done programming.
A.3.2 Linker Command File TMS320F206 Sample Assembly Code
Filename: ASMEXAMP.CMD Description: Linker command file 'F206 example on-chip flash programming from assembly. This command file links example addr 0x8000 on-chip SARAM that debugger used breakpoints. Another benefit linking example SARAM that code modified operate either flash module0, module1, both. Notes: This example expects 'F206 SARAM mapped both data space program space (DON=PON=1). object modules standard flash algos expected subdirectory (ALGOS) path this file. Rev1.0 3/98 Line .text asmexamp.out asmexamp.map asmexamp.obj /*User assembly code that calls flash algos. algos\spgm20.obj /*Standard Programming algorithm. algos\sclr20.obj /*Standard Clear algorithm. algos\sera20.obj /*Standard Erase algorithm. algos\sflw20.obj /*Standard Flash-write algorithm. algos\sutils20.obj /*Subroutines used standard algos. MEMORY PAGE Program memory FLASH0: origin 0x0000, length 0x3fff FLASH1: origin 0x4000, length 0x3fff PSARAM: origin 0x8000, length 0x400 /*Use SARAM PROGRAM origin 0xff00, length 0x1ff
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Assembly Source Listings Program Examples
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Sample Assembly Code Erase Reprogram TMS320F206
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PAGE
Data memory /*BLOCK /*Use SARAM data DON=1 /*External data /*B1 (Used algo vars
BLK_B2: origin 0x60,length 0x20 DSARAM: origin 0xc00, length 0xC00 EX1_DM: origin 0x4000, length 0x4000 origin 0x300, length 0x1ff
SECTIONS .text PSARAM PAGE asmexamp.asm /*All fl_prg fl_clr fl_ers fl_wrt PRG_data these sections flash programming.*/ PSARAM PAGE /**Programming Algorithm*****/ PSARAM PAGE /******Clear Algorithm*******/ PSARAM PAGE /******Erase Algorithm*******/ PSARAM PAGE /****Flash-write Algorithm***/ PSARAM PAGE /******Delay Subroutine******/ PSARAM PAGE /*******Regs Subroutine******/ PSARAM PAGE /******Array Subroutine******/ PAGE /*Reserved asmexamp.asm /*for flash algo variables.**/ PRG_parm PAGE /*Reserved asmexamp.asm /*for param passing algos*/ /*End sections flash programming.
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Sample Code Erase Reprogram TMS320F206
Sample Code Erase Reprogram TMS320F206
Because algorithm implementations follow C-calling convention 'C2000 environment, they cannot used directly from assembly code section A.2, C-Callable Interface Flash Algorithms, provided C-callable interface programming algorithms. following source file linker command file provide working example 'F206. this example, algorithms reside on-chip SARAM, either flash0 flash1 reprogrammed. code relocated anywhere program space, with exceptions described section A.3, Using Algorithms With Assembly Code.
A.4.1 Code That Calls Interface Flash Algorithms TMS320F206
Filename: sample.c Description: This example program 'F2XX flash from code. C-callable interface standard flash algorithms used. This interface defined file <flash.asm>, C-callable functions: erase(), program() link time, this example must combined with code <flash.asm> well with object modules standard algos. This example TMS320F206, uses SARAM buffer programming data. code first erases module1, then programs first three locations. Rev1.0 10/97 extern erase(); Declare external func flash erase. extern program(); Declare external func flash programming. main() (erase(0xff00,0x4000,0x7fff)) /*Flash erased, let's program it.*/ Init program buffer. a=(int *)0xC00; /*Use last SARAM data buffer*/ a[0]=0x7A80; a[1]=0x0FDF; a[2]=0x7A80; /*Program flash from buffer*/ /*Flash programmed ok.*/ while(1){} /*Spin here forever*/ else
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Assembly Source Listings Program Examples
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Sample Code Erase Reprogram TMS320F206
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/*Flash fails programming, EXIT*/ while(1){} /*Spin here forever*/ else /*Flash fails erase, EXIT*/ while(1){} /*Spin here forever*/
A.4.2 Linker Command File TMS320F206 Sample Code
Filename: F206_SA.CMD Description: Linker command file 'F206 example on-chip flash programming from code. This command file links example addr 0x8000 on-chip SARAM that debugger used breakpoints. Another benefit linking example SARAM that code modified operate either flash module0, module1, both. Notes: This example expects 'F206 SARAM mapped both data space program space (DON=PON=1). object modules standard flash algos expected subdirectory (ALGOS) path this file. Rev1.0 10/97 Line /*Use init model. -heap /*No heap needed this example. -stack 0x96 /*150-word stack enough this example. /*Force rereading libraries. c:\dsptools\rts2xx.lib sample_S.out sample_S.map sample.obj /*User code with calls erase() program() flash.obj /*C-callable interface standard algorithms. algos\spgm20.obj /*Standard Programming algorithms. algos\sclr20.obj /*Standard Clear algorithm. algos\sera20.obj /*Standard Erase algorithm. algos\sflw20.obj /*Standard Flash-write algorithm. algos\sutils20.obj /*Subroutines used standard algorithms. MEMORY PAGE Program memory A-38
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FLASH0: FLASH1: PSARAM: origin origin origin origin 0x0000, 0x4000, 0x8000, 0xff00,
Sample Code Erase Reprogram TMS320F206
length length length length
0x3fff 0x3fff 0x400 /*Use SARAM PROGRAM*/ 0x1ff
PAGE Data memory BLK_B2: DSARAM: EX1_DM: origin origin origin origin 0x60, 0xc00,
length length length length
0x4000, 0x300,
0x20 /*BLOCK 0xC00 /*Use SARAM data /*DON=1*/ 0x4000 /*External data 0x1ff /*B1 (Used algo vars
SECTIONS .text PSARAM PAGE sample.c /*All these sections flash programming.*/ PRG_text PSARAM PAGE /**erase() program()*****/ /*****from flash.asm file****/ fl_prg PSARAM PAGE /**Programming Algorithm*****/ fl_clr PSARAM PAGE /******Clear Algorithm*******/ fl_ers PSARAM PAGE /******Erase Algorithm*******/ fl_wrt PSARAM PAGE /****Flash-write Algorithm***/ PSARAM PAGE /******Delay Subroutine******/ PSARAM PAGE /*******Regs Subroutine******/ PSARAM PAGE /******Array Subroutine******/ PRG_data PAGE /*Reserved flash.asm for**/ /***flash algo variables.****/ PRG_parm PAGE /*Reserved flash.asm for**/ /*parameter passing algos*/ /*End sections flash programming. .bss .cinit .const .data .stack PAGE PAGE PAGE PAGE PAGE
stack.
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Assembly Source Listings Program Examples
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Sample Assembly Code Erase Reprogram TMS320F240
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Sample Assembly Code Erase Reprogram TMS320F240
algorithm files used from assembly straightforward manner. general, algorithms reside anywhere program space. However, algorithms cannot executed from flash module that being modified, algorithms must execute with zero wait states. assembly code linker command file this section provide working example 'F240. Note: This actual application example since boot mechanism required load external SRAM powerup. This example uses 'C2xx Csource Debugger download code external SRAM. addition, reset interrupt vectors initialized. system requirements F240 target board with external program space SRAM located 0x8000 minumum words.
A.5.1 Assembly Code TMS320F240
Filename: ASMEXA24.ASM Description: This file contain
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