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TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Hansbauer/Rebecca Digital Signal Processing Solutions
Abstract
This document describes multi-channel buffered serial ports (McBSPs) Texas Instruments TMS320C6000 digital signal processor (DSP) digital controller audio codec 1997 device. McBSP connected stereo audio codec 1997 device. This application report uses TLC320AD90 audio codec (AD90) example. audio codec 1997 (AC'97) standard specifies five-signal digital connection between McBSP AD90. These five signals SYNC, BIT_CLK, SDATA_OUT, SDATA_IN, RESET signals AC'97 device. this AC'97 interface, McBSP operates audio codec controller. This application report discusses configuration these signals detail. hardware schematic discussed this document possible solution AC'97 interface been tested.
Contents
Design Problem Overview Solution Hardware Interface McBSP Register Configuration Timing Diagram.6 McBSP Initialization Sample Functions.8 Conclusion References.8 Appendix Sample Source Code AD90 Interface.9
Figures
Figure Figure Figure Figure Figure Figure Figure AC'97 System Architecture Digital Interface Between McBSP AC'97 Device.3 Receive Control Register (RCR) Transmit Control Register (XCR) Sample Rate Generator Register (SRGR) Control Register (PCR) Timing Diagram AC'97 Dual-Phase Frame Format
Digital Signal Processing Solutions
April 1999
Design Problem
multi-channel buffered serial port (McBSP) TMS320C6000 used digital controller audio codec 1997 (AC'97) device?
Overview
McBSP operate digital controller audio codec device that compliant audio codec 1997 (AC'97) component specification. AC'97 standard specifies 5-wire digital serial link, "AC-Link", between audio codec device digital controller. Figure shows block diagram AC'97 system architecture. AC'97 device perform digital-to-analog conversion, analog-to-digital conversion, analog input mixing. supports different analog audio inputs/outputs communicate with digital controller through AC-Link, mentioned above. This application report discusses digital interface between AC'97 device TLC320AD90C McBSP TMS320C6000 digital controller. Analog input/output descriptions within scope this application report. (See TLC320AD90C Data Manual information concerning analog input/output audio codec.) Because TLC320AD90C interface 3.3-V digital controller, voltage translation necessary interface McBSP AD90. digital supply voltage, DVDD2, AD90 must
Figure AC'97 System Architecture
'C6201 McBSP Digital Controller AC'97 Device AC-Link
Analog Analog Mixer Digital Interface
Analog Input
Analog Output
Solution
Hardware Interface
successfully McBSP audio codec digital controller, must configure five AC'97 signals: SYNC, SDATA_OUT, RESET, BIT_CLK, SDATA_IN. audio codec AD90 generates these AC'97 signals, BIT_CLK SDATA_IN, which connected McBSP CLKS pins, respectively. McBSP generates remaining three AC'97 signals, SYNC, SDATA_OUT, RESET. Table summarizes signals this 5-wire digital serial link, "AC-Link".
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
audio codec device generates clock AC'97 interface. 24.576-MHz crystal connected audio codec TLC320AD90. AD90 internally divides down this fixed-rate clock signal produce 12.288-MHz clock signal output BIT_CLK pin. shown Figure this BIT_CLK signal connected CLKS McBSP used drive McBSP's sample rate generator. McBSP also derives frame sync signal from BIT_CLK. connected input SYNC AD90. compliant with AC'97 protocol specification, must period McBSP sample rate generator BIT_CLK cycles generate frame sync signal every CLKS cycles, fixed rate kHz. width frame sync signal BIT_CLK cycles. period width frame sync signal defined FPER FWID fields sample rate generator register (SRGR) McBSP. SDATA_OUT, SDATA_IN pins AD90 connected pins McBSP, respectively. McBSP receives transmits data dual-phase frames. each case, first phase consists 16-bit element; second phase consists twelve 20-bit elements. user configure receive transmit operation McBSP receive transmit control registers (RCR XCR). name implies, RESET signal AD90 resets audio codec brings TLC320AD90 power-down mode. AC'97 standard specifies kinds reset-"Cold AC'97 Reset" "Warm AC'97 Reset". Depending application, user freedom configure general-purpose output `C6000 drive RESET input AD90. This application report shows TOUT0 generalpurpose output McBSP RESET signal AD90. Figure shows 5-pin hardware interface between McBSP AC'97 audio codec. Table describes these AC-Link signals.
Figure Digital Interface Between McBSP AC'97 Device
McBSP AC'97 Compliant Controller CLKS TOUT0 SYNC BIT_CLK SDATA_OUT SDATA_IN RESET TLC320AD90C Digital Interface (AC-Link)
AC-Link
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Table McBSP AD90 Interface Description
`C6x McBSP (output) CLKS (input) (output) (input) TOUT0 (output) AD90 SYNC (input) BIT_CLK (output) SDATA_OU (input) SDATA_IN (output) RESET (input) Description marks beginning each frame. generated McBSP fixed rate kHz. AD90 generates BIT_CLK fixed rate 12.288 MHz. CLKS input clock McBSP's sample rate generator. Serial data goes from McBSP AD90 device. Data captured AD90 codec every falling edge BIT_CLK. Serial data goes from AD90 codec McBSP. Data transmitted AD90 codec every rising edge BIT_CLK. Reset signal generated McBSP wakes AD90 codec from power down mode.
McBSP Register Configuration
setup programmable control registers McBSP McBSP AD90 interface shown Figure through Figure Table lists describes register values interface. Note that although used hardware interface, FSRM field control register still must indicate that receive frame synchronization signals generated internally sample rate generator.
Figure Receive Control Register (RCR)
RPHASE Reserved 1011b RFRLEN2 RFRLEN1 010b RWDLEN1 011b RWDLEN2 RCOMPAND Reserved RFIG RDATDLY
Figure Transmit Control Register (XCR)
XPHASE Reserved 1011b XFRLEN2 XFRLEN1 010b XWDLEN1 011b XWDLEN2 XCOMPAND Reserved XFIG XDATDLY
Figure Sample Rate Generator Register (SRGR)
GSYNC CLKSP CLKSM FSGM 1111 1111b FPER
1111b FWID
CLKGDV
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Figure Control Register (PCR)
0x0000 Reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Table Bit-Field Values McBSP Registers
Register (Bit-Field RCR[31] XCR{31] RCR{30:24] XCR{30:24] RCR[23:21] XCR[23:21] RCR[17:16] XCR{17:16] RCR[14:8] XCR[14:8] RCR[7:5] XCR[7:5] SRGR[31] SRGR[29] SRGR[28] SRGR[27:16] SRGR[15:8] SRGR[7:0] PCR[11] PCR[10] PCR[3] PCR[2] Bit-Field Name RPHASE XPHASE RFRLEN2 XFRLEN2 RWDLEN2 XWDLEN2 RDATDLY XDATDLY RFRLEN1 XFRLEN1 RWDLEN1 XWDLEN1 GSYNC CLKSM FSGM FPER FWID CLKGDV FSXM FSRM FSXP FSRP 1011b 1011b 011b 011b 010b 010b 1111 1111b 1111b Value binary) Dual phase receive frame Dual phase transmit frame Phase Receive frame length elements Phase Transmit frame length elements Phase Receive elements bits Phase Transmit elements bits 1-bit receive data delay. phase data begins after BIT_CLK delay 1-bit transmit data delay. phase data begins after BIT_CLK delay Phase Receive frame length element Phase Transmit frame length element Phase Receive elements bits Phase Transmit elements bits Sample rate generator clock free running, driven external clock CLKS Sample rate generator clock derived from external clock source CLKS driven sample rate generator frame sync signal Frame period CLKS(12.288 MHz) periods 48-kHz FSX) Frame sync signal width BIT_CLK CLKG same frequency sample rate generator input clock CLKS Frame synchronization generated internally Frame synchronization generated internally active high active high Function Description
NOTE: bit-fields registers listed Table assume their default values. user responsible some register fields initial state different from default.
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Timing Diagram
AC-Link architecture TLC320AD90C audio codec employs dual-phase frame format. divides each 256-bit frame (both transmit receive) into phases. first phase 16-bit Phase. shown Figure audio output frame (SDATA_OUT) where data goes from McBSP codec, first Phase "Valid Frame" bit. When "Valid Frame" one, indicates that there least slot containing valid data this frame. audio input frame (SDATA_IN) where data goes from codec McBSP, first Phase indicates whether codec ready. next twelve bits Phase indicate there valid data corresponding slot second phase. second phase DATA Phase. DATA Phase consists twelve 20-bit slots, total transmission bits. These slots contain control audio data. (Refer TLC320AD90C Data Manual complete description frame contents.) Figure shows timing diagram this AC'97 dual-phase frame format.
Figure Timing Diagram AC'97 Dual-Phase Frame Format
Phase bits DATA Phase Slots Bits Bits
12.288MHz BIT_CLK (CLKS) SYNC (FSX)
cycle delay from SYNC
SDATA_OUT (DX) SDATA_IN (DR)
valid
Slot
Slot
Slot
Slot
Slot
Slot
Slot
previous Audio Frame Transmission Phase data begins here Transmission DATA Phase data begins here
Slot
Slot
Slot
signal generated McBSP synchronized rising edge BIT_CLK sampled AD90 falling edge BIT_CLK. phase data transfer begins immediately rising edge next BIT_CLK signal. this reason, RDATDLY XDATDLY bits registers, respectively, indicate BIT_CLK delay from rising edge beginning data transfer.
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
McBSP Initialization
Typically services McBSP controlling internal data flow from McBSP. following steps describe procedures necessary initializing DMA, McBSP, interrupts.
Reset audio codec asserting AD90 RESET signal minimum 1us. this application report, `C6000's general purpose output TOUT0 used reset signal. Program sample rate generator register (SRGR), serial port control register (SPCR), control register (PCR), receive control register (RCR) values shown above Table /GRST SPCR this step. Take sample rate generator reset setting /GRST=1 SPCR. Enabling Interrupts: interrupts, must global interrupt enable (GIE), non-maskable interrupt enable (NMIE) bits IER. Select channel(s) want use. Enable interrupts that correspond channel that will used service McBSP. default mapping channel-complete interrupts follows: channel channel channel channel
interrupt interrupt interrupt interrupt
initialization: Program channel required operation. following typical set-up: Source address Destination address internal memory required. Transfer counter number elements transferred. Receive synchronization event, RSYNC REVT from McBSP
interrupt bit, TCINT enabled Priority bit, optional, recommended. Instruct channel(s) run. example, START=01b
channel's primary control register start without auto-initialization. will start first transfer upon receiving first read/write sync event.
Wake AD90 codec setting AD90 RESET signal inactive high. BIT_CLK
AD90 starts running after some delay. BIT_CLK drives McBSP's sample rate generator clock CLKG.
/XRST=/RRST=1 wake McBSP. /FRST=1 start frame sync
generator McBSP. first frame sync signal (FSX) generated McBSP after CLKG clocks. This signal captured AD90 codec falling edge BIT_CLK. SDATA_IN SDATA_OUT transmitted next rising edge BIT_CLK.
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Sample Functions
Appendix contains sample code that sets `C6000 digital controller audio codec 1997 device. This sample code been tested. (See TMS320C6x Peripheral Support Library Programmer's Reference detailed description header files used this code.)
Conclusion
McBSP function AC'97 digital controller correctly connecting just five signals. This AC'97 interface runs fixed sample rate kHz. McBSP generates this 48-kHz SYNC signal FSX) dividing down 12.288-MHz BIT_CLK input 256. Each audio frame conists phases. first phase 16-bit phase that defines portion AC'97 signal. second phase, which consists twelve 20-bit elements, defines 240-bit DATA Phase. With signals configured described this application report, TMS320C6000 operates AC'97 digital controller.
References
Audio Codec Component Specification, Revision 1.02, Intel Corporation, May, 1996. TLC320AD90C Stereo Audio Codec Data Manual, Texas Instruments, Literature number SLAS173, March 1998. URL: TMS320C6201 Digital Signal Processor data sheet, Texas Instruments, Literature number SPRS051C, March 1998. URL:
TMS320C6201/C6701 Peripherals Reference Guide, Texas Instruments, Literature number SPRU190B, March 1998.
TMS320C6x Peripheral Support Library Programmer's Reference, Texas Instruments, Literature number SPRU273B, July 1998.
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Appendix Sample Source Code AD90 Interface
codec.c V1.00 Copyright 1998 Texas Instruments Incorporated 3/5/98: Rebecca codec.c: This program sets McBSP1 digital controller Audio Codec 1997 Device. channel service McBSP. CLKX, CLKR generated using CLKS clock. output that drive codec's frame syncs. #include <dma.h> #include <intr.h> #include <timer.h> #include <mcbsp.h> #include <regs.h> #include <stdio.h> #include <stdlib.h> #define #define #define #define #define BUFFER_SIZE CLKGDV1 FPER1 FWID1 CLKSM1 clock period long SYNC signal-TAG Phase CLK_MODE_CLKS clock derived from CLKS source
#define XFER_ELEMENT_CNT13 number DMA-transferred elements frame #define XFER_FRAME_CNT total frames transferred-for setup only #define FALSE #define TRUE #define #define 0x80003000 0x80000000
volatile xmit1_done; volatile recv1_done; void void void void void void init_m1(void); init_M1_srgr(void); start_dma(void); c_int11(void); c_int08(void); set_interrupts(void);
void main(void) recv1_done FALSE; xmit1_done FALSE; User responsible initialize data transferred Reset AC97 device TOUT_ENABLE(0); TOUT0 general purpose output TOUT_VAL(0, TOUT0 need least SRGR values needed init_M1_srgr(); Now, initialize other control registers McBSP operation init_m1(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(1);
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Reset channels dma_reset(); Interrupt Service Routines set_interrupts(); Start transfers-which wait McBSP synchronization event start_dma(); Take AC97 device reset BIT_CLK will start after some delay 200; i++); make sure TOUT0 TOUT_VAL(0,1); take codec reset: TOUT0 i++); wait BIT_CLK start Take SET_BIT SET_BIT SET_BIT McBSP receiver/transmitter reset. (MCBSP_SPCR_ADDR(1), RRST); (MCBSP_SPCR_ADDR(1), XRST); (MCBSP_SPCR_ADDR(1), FRST); Start frame sync
wait interrupt indicating transfer completion while (!xmit1_done !recv1_done); After interrupt, program continues here
void init_m1(void) subroutine initialize mcbsp1 setup Transmit LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSXP, LOAD_FIELD (MCBSP_PCR_ADDR(1), CLK_MODE_INT, CLKXM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSXM, SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(1), FSX_FSG, FSGM, setup LOAD_FIELD (MCBSP_XCR_ADDR(1), DUAL_PHASE, XPHASE, LOAD_FIELD (MCBSP_XCR_ADDR(1), WORD_LENGTH_16, XWDLEN1, XWDLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), XFRLEN1, XFRLEN1_SZ); Phase1: element LOAD_FIELD (MCBSP_XCR_ADDR(1), DATA_DELAY1, XDATDLY, XDATDLY_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), COMPAND_ULAW, XCOMPAND, XCOMPAND_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), WORD_LENGTH_20, XWDLEN2, XWDLEN2_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), XFRLEN2, XFRLEN2_SZ); /*Phase2: elements setup Receive LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSRP, LOAD_FIELD (MCBSP_PCR_ADDR(1), CLK_MODE_INT, CLKRM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSRM, setup LOAD_FIELD (MCBSP_RCR_ADDR(1), DUAL_PHASE, RPHASE, LOAD_FIELD (MCBSP_RCR_ADDR(1), WORD_LENGTH_16, RWDLEN1, RWDLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), RFRLEN1, RFRLEN1_SZ); Phase1: element LOAD_FIELD (MCBSP_RCR_ADDR(1), DATA_DELAY1, RDATDLY, RDATDLY_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), COMPAND_ULAW, RCOMPAND, RCOMPAND_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), WORD_LENGTH_20, RWDLEN2, RWDLEN2_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), RFRLEN2, RFRLEN2_SZ); Phase2: elements SPCR LOAD_FIELD (MCBSP_SPCR_ADDR(1), RXJUST_RJZF, RJUST, RJUST_SZ); void init_M1_srgr(void) subroutine initialize mcbsp1 SRGR LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKGDV1, CLKGDV, CLKGDV_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), FWID1, FWID, FWID_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), FPER1, FPER, FPER_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKSM1, CLKSM, LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKS_POL_RISING, CLKSP, LOAD_FIELD (MCBSP_SRGR_ADDR(1), GSYNC_OFF, GSYNC,
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
void start_dma(void)
xfer_element_cnt XFER_ELEMENT_CNT; xfer_frame_cnt XFER_FRAME_CNT;
channel receive DMA0_SRC_ADDR MCBSP_DRR_ADDR(1); DMA0_DEST_ADDR LOAD_FIELD (DMA0_XFER_COUNTER_ADDR, xfer_element_cnt, ELEMENT_COUNT, ELEMENT_COUNT_SZ); LOAD_FIELD (DMA0_XFER_COUNTER_ADDR, xfer_frame_cnt, FRAME_COUNT, FRAME_COUNT_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA0_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, SEN_REVT1, RSYNC, RSYNC_SZ); DMA_START(DMA_CH0); channel transmit DMA2_SRC_ADDR OUT; DMA2_DEST_ADDR MCBSP_DXR_ADDR(1); LOAD_FIELD (DMA2_XFER_COUNTER_ADDR, xfer_element_cnt, ELEMENT_COUNT, ELEMENT_COUNT_SZ); LOAD_FIELD (DMA2_XFER_COUNTER_ADDR, xfer_frame_cnt, FRAME_COUNT, FRAME_COUNT_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT1, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); void set_interrupts(void) subroutine setup interrupts intr_init(); INTR_MAP_RESET(); Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); intr_hook (c_int08, CPU_INT8); enable NMIE, default interrrupt correponding channel INTR_ENABLE(CPU_INT_NMI);/* Enable NMIE INTR_GLOBAL_ENABLE(); CSR*/ INTR_ENABLE(11); default interrrupt correponding channel INTR_ENABLE(8); return; DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit1_done TRUE; interrupt indicates done transmitting data return; interrupt void c_int08(void) recv1_done TRUE; interrupt indicates done receiving data return;
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
Contact Numbers
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TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty, endorsement thereof. Copyright 1999 Texas Instruments Incorporated
TMS320C6000 McBSP: AC'97 Codec Interface (TLC320AD90)
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