Shaku Anjanaiah Digital Signal Processing Solutions This document

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Shaku Anjanaiah Digital Signal Processing Solutions This document

Datasheet Thumbnail

Top Searches for this datasheet

TMS320C6000 McBSP Interface ST-bus Device
Shaku Anjanaiah Digital Signal Processing Solutions
This document describes multi-channel buffered serial ports (McBSP) Texas Instruments (TITM) TMS320C6201 digital signal processor (DSP) used communicate ST-bus compliant device. McBSP receives framing signal, clock, data from ST-bus device processes them generate internal frame syncs clocks correct data reception. highly programmable features McBSP make easy interface ST-bus signals. This application report focuses single rate ST-bus wherein ST-bus system clock data rate (number bits sec) equal. Hence name single rate, which applies only 2.048 system clock. usage McBSP registers sample code perform above function described this document.
Digital Signal Processing Solutions
July 1999
Contents
TMS320C6000 McBSP Interface ST-bus Device Design Problem. ST-bus Requirements McBSP Operation ST-bus. McBSP Register Configuration McBSP Initialization Sample Code Setup. Functions Overview. Appendix Appendix Appendix Appendix Appendix
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure McBSP Connection 2.048 Single Rate ST-bus. Single Rate ST-bus Example Double Rate ST-bus Timing Diagram Receive Control Register (RCR) Sample Rate Generator Register (SRGR). Control Register (PCR). Serial Port Control Register (SPCR). ST-bus emulator McBSP Timing Diagram Example Single Rate ST-bus Setup
Tables
Table Bit-Field Values McBSP Registers.
TMS320C6000 McBSP Interface ST-bus Device
TMS320C6000 McBSP Interface ST-bus Device
Design Problem
multi-channel buffered serial port TMS320C6201 communicate single rate Serial Telecom(ST) compliant device?
ST-bus Requirements
ST-bus synchronous serial with data transfer rates 2.048, 4.096, 8.192 Mbps. interface ST-bus device comprises clock, frame, data signals. These signals available McBSP programmable, thereby making glue-less interface. ST-bus data stream comprises frames with period 125µs frame rate 8000 frames sec. This 8kHz sampling rate (twice highest signal frequency order retain information stream) corresponds 4kHz voice band frequency. frame signal indicates start frame each frame carries blocks 8-bit data. clocks ST-bus data 2.048, 4.096, 8.192, 16.384 MHz. Note that these clocks always twice data rate except 2.048 MHz. Since 2.048 ST-bus clock rate also data rate, referred Single Rate ST-bus. example Double rate ST-bus would 2.048Mbps data stream clocked 4.096MHz clock. following sections describe hardware software interface `C6000 McBSP single rate ST-bus device.
McBSP Operation ST-bus
ST-bus compliant device that McBSP interfacing master frames clock. This means that ST-bus device should provide 2.048 clock, which becomes external clock source McBSP CLKS pin. Also, framing signal, /F0, generated ST-bus device used receive frame sync (FSR) input McBSP. data transmitted ST-bus device received McBSP. These connections shown Figure
Mitel Semiconductor Reference: Mitel Application Note MSAN-126, ST-BUS Generic Device Specification (Rev. recommended that reader familiar with features `C6000 McBSP reading TMS320C6201/C6701 Peripheral Reference Guide, especially Section 8.5.4
TMS320C6000 McBSP Interface ST-bus Device
Figure McBSP Connection 2.048 Single Rate ST-bus
Compliant Device `C6x McBSP
CLKS
order McBSP recognize ST-bus data stream, GSYNC Sample Rate Generator Register set. ST-bus-provided frame sync active signal that half CLKS period. GSYNC causes external frame sync that arrives sampled rising edge CLKS turn generates internal frame sync McBSP that active high CLKS clock period. This internal frame sync, FSR_int, used reference data reception. This shown Figure 2.048MHz single rate ST-bus example shown Figure data stream comprises elements 8-bits each each frame. Each frame starts with frame sync signal /F0. Since McBSP receiver does know when first frame will arrive FSR, therefore does know when reset receive data, special interrupts should used. This made easy with frame sync interrupt that available McBSP which works even when receiver reset. receive interrupt (RINT) programmed detect frame sync pulse, after which safely take receiver reset. Further initialization details discussed McBSP Initialization section this document.
Figure Single Rate ST-bus Example
C4=4.096MHz sampled C2=CLKS=2.048MHz external FS(R/X)_int, CLK(R/X)_int (first FSR) D(R/X) (first FSR) CLK(R/X)_int(subsequent FSR) D(R/X) (subsequent FSR) E32B0 E1B7 E1B6 E1B5 E1B0 E2B7 E1B7 E1B6 E1B5 E1B0 E2B7
ExBy ementx
TMS320C6000 McBSP Interface ST-bus Device
Figure Double Rate ST-bus Timing Diagram
sampled CLKS=4.096/8.192/16.384MHz external FS(R/X)_int, CLK(R/X)_int (first FSR) D(R/X) (first FSR) CLK(R/X)_int (subsequent FSR) D(R/X) (subsequent FSR) E32B0 E1B7 E1B6 E1B5 E1B0 E2B7 E1B7 E1B6 E1B5 E1B0 E2B7
ExBy ementx
case double rate ST-bus clock, 4.096, 8.192, 16.384 clocks supported with data rates equal half ST-bus clock rate. ST-bus clock drives CLKS McBSP. frame sync provided ST-bus (/F0) active ST-bus clock period drives McBSP. This external frame sync sampled McBSP falling edge CLKS generate required internal frame sync. timing diagram double rate STbus clock shown McBSP register double rate operation same single rate with following exceptions: CLKGDV=1 that data rate half clock rate (CLKS). CLKSP=1 ensures that internal clocks CLKG, CLKR_int, CLKX_int generated falling edge CLKS,; same edge that generates FSG, FSR_int, FSX_int.
McBSP Register Configuration
shown Figure FSR, CLKS, inputs.
Framing Signal: polarity incoming frame sync signal (/F0) inverted provide necessary active high input signal McBSP. external frame sync pulse dictates arrival frame therefore frame period (FPER) frame width (FWID) used/programmed.
Although treated input, FSRM /FRST SPCR /FRST enable frame sync signal generation. FSRM=1 indicates that internally generated FSR_int will used detect arrival data, will output because GSYNC=1 disables output buffer. Since single phase frame with each frame comprising elements 8-bits each, FRLEN1=31, WDLEN1=0.
Data Delay: Since there delay between arrival first data generation internal frame sync FSR_int, receiver should data delay zero.
TMS320C6000 McBSP Interface ST-bus Device
Clocks: Although CLKR McBSP used this necessary configure output. Another important parameter polarity CLKS signal. CLKS polarity determines edge that samples incoming frame sync signal also edge that generates internal clocks CLKG, CLKR_int, CLKX_int, internal frame sync signal FSG, FSR_int, FSX_int. Single Rate ST-bus case, rising edge CLKS does above function.
various settings above requirements shown Figure Figure Figure Figure Table
Figure Receive Control Register (RCR)
RPHASE reserved RFRLEN2 RFRLEN1 RWDLEN1 RWDLEN2 RCOMPAND reserved RFIG RDATDLY
Figure Sample Rate Generator Register (SRGR)
GSYNC CLKSP CLKSM FSGM FWID FPER 0x00 CLKGDV
Figure Control Register (PCR)
0x0000 reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Figure Serial Port Control Register (SPCR)
0x00 FRST22 GRST6 reserved XINXSYNCERR XEMPTY4 RIN3 RSYNCERR RFULL XRDY RRDY XRST0 RRST-
RJUST CLKSTP reserved reserved
TMS320C6000 McBSP Interface ST-bus Device
Table
Bit-Field Values McBSP Registers
Register [bit-field
RCR[17:16] SPCR[5:4] SPCR[23] SPCR[22] SRGR[31] SRGR[29] SRGR[7:0] PCR[10] PCR[8] PCR[2]
Bit-field Name
RDATDLY RIN/FRST /GRST GSYNC CLKSM CLKGDV FSRM CLKRM FSRP
Value binary) Slave (Receiver)
0(default) 0(default) 0(default)
McBSP Initialization
Typical applications service McBSP. Please refer application note, "TMS320C6000 McBSP Initialization" program McBSP control registers registers proper serial port operation. addition this, following step required since frame sync interrupt used wake McBSP. After START state, first frame sync that arrives will wake receiver. This done corresponding CPU_INT13. should also disable this interrupt that subsequent frame syncs cause unnecessary enabling receiver that already been taken reset. when next frame sync arrives, receiver provides read sync event DMA, which causes transfer data from specified destination address. receiver will continue receive data until required number frames been received.
Sample Code Setup
example code Appendix through tested `C6201 devices, CPU0 CPU1, single board. block diagram this test setup shown Figure
TMS320C6000 McBSP Interface ST-bus Device
Figure ST-bus emulator McBSP
CPU1- McBSP0 Emulator FSX0 CLKS0 CPU0- McBSP1 Compliant FSR1 CLKS1
fsx_in fsx_out clks 4.096 2.048 clks2
McBSP0 CPU1 configured ST-bus transmitter (master) which provides frame sync data. ST-bus clock this example 2.048 which derived from 4.096 clock PAL. uses FSX0 (fsx_in) generate active frame sync signal, fsx_out, appropriate rising edge CLKS(0/1). Signal fsx_out equivalent FSR_ext signal shown Figure equations VHDL listed Appendix resulting signals above shown Figure
TMS320C6000 McBSP Interface ST-bus Device
Figure Timing Diagram Example Single Rate ST-bus Setup
CLKS2 FSR1 sampled CLKS FSX0/fsx_in FSR1/fsx_out FSR1_int/FSG1_int RDATDLY1=0 XDATDLY0=1 E1B7 E1B6
DX0/DR1
E1B5
Functions Overview
sample code that initializes `C6x interface ST-bus device enclosed Appendices through brief description some routines described below: init_M1_srgr(); init_M0_srgr(); SRGR values McBSP0/1 needed init_m0to1(); init_m1to0(); SPCR0/1, PCR0/1, XCR0, RCR1 registers CPU0_McBSP1 CPU1_McBSP0 set_interrupts(); Maps interrupt sources interrupts. Hooks relevant interrupt. Enables GIE, NMIE, CPU_INT8, CPU_INT13. reg_dump(); Dumps value McBSP registers data transfer. following Interrupt Service Routines interrupt void c_int08(void) This entered when McBSP1 (ST-bus slave) completed data reception. Sets `recv1_done'flag. interrupt void c_int11(void)
TMS320C6000 McBSP Interface ST-bus Device
This entered when McBSP0 (ST-bus emulator) completed transmitting data. Sets `xmit0_done'flag. interrupt void c_int13(void) This executed when first frame sync arrives. Wakes receiver (/RRST=1), sets `new_fsr' flag, disables this interrupt prevent unnecessary setting /RRST bit.
Appendix
STB1_MASTER.C V1.00 Copyright 1998 Texas Instruments Incorporated 04/15/98: Shaku Anjanaiah stb1_master.c: McBSP0 (defined stb1_master.c) acts ST-bus emulator McBSP1 (defined stb1_slave.c) acts single rate ST-bus device. This test verify Single rate ST-bus operation using C6201s. This tcase configures CPU0_McBSP1 ST-bus master VDB. generated master delayed (this done PAL) that detected rising edge CLKS. CLKS drives both master slave ST-bus devices. #include "common.h" #define M0TO1 TRUE McBSP0 transmits McBSP1 #define M1TO0 FALSE McBSP1 transmits McBSP0 #define CLKGDV0 #define FPER0 #define FWID0 #define XFER_SIZE #define XFER_TYPE DMA_STB #define CLKSM0 CLK_MODE_CLKS #define CLKSM1 CLK_MODE_CLKS #define M0TO1_MSTR TRUE #define M1TO0_MSTR TRUE void init_m0to1(void); void init_M0_srgr(void);
TMS320C6000 McBSP Interface ST-bus Device
void main(void) xfer_size; xfer_type; mcsp0to1_rate; mcsp1to0_rate; xmit1_done recv0_done xmit0_done recv1_done mcsp1to0 mcsp1to0 mcsp0to1 mcsp0to1 FALSE FALSE FALSE FALSE TRUE; TRUE; TRUE; TRUE;
mcsp1to0 M1TO0; mcsp0to1 M0TO1; xfer_size XFER_SIZE; xfer_type XFER_TYPE; SRGR values needed init_M0_srgr(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(0); Now, initialize other control registers McBSP operation (mcsp0to1) init_m0to1(); (mcsp1to0) (;;); Reset channels switch (xfer_type) case DMA_STB: dma_reset(); set_interrupts(); Initialize service McBSP (mcsp0to1) uses xmit DMA2_SRC_ADDR (unsigned int) out0; DMA2_DEST_ADDR MCBSP_DXR_ADDR(0); REG_WRITE (DMA2_XFR_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT0, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); (mcsp1to0) (;;); take transmitter (stb1 master) reset SET_BIT (MCBSP_SPCR_ADDR(0), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); while (!xmit0_done); break;
TMS320C6000 McBSP Interface ST-bus Device
reg_dump(); 0x00007000;
PowerDown shut MCSP
void init_m0to1(void) setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_POL_LOW, FSXP, inverted LOAD_FIELD (MCBSP_PCR_ADDR(0), M0TO1_MSTR, CLKXM, clkx0 LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_MODE_INT, FSXM, fsx0 SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(0), FSX_FSG, FSGM, setup LOAD_FIELD (MCBSP_XCR_ADDR(0), SINGLE_PHASE, XPHASE, LOAD_FIELD (MCBSP_XCR_ADDR(0), WORD_LENGTH_8, XWDLEN1, XWDLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(0), XFRLEN1, XFRLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(0), DATA_DELAY1, XDATDLY, XDATDLY_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(0), NO_COMPAND_MSB_1ST, XCOMPAND, XCOMPAND_SZ);
void init_M0_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0),
CLKGDV0, CLKGDV, CLKGDV_SZ); FWID0, FWID, FWID_SZ); FPER0, FPER, FPER_SZ); CLK_MODE_CLKS, CLKSM, CLKS_POL_RISING, CLKSP, GSYNC_OFF, GSYNC,
void reg_dump(void) (int MCBSP_ADDR(0); (int MCBSP_ADDR(1); i++) regdump0[i] m0[i]; regdump1[i] m1[i];
void set_interrupts(void)
TMS320C6000 McBSP Interface ST-bus Device
intr_init(); Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); enable NMIE, default interrrupt correponding channel INTR_ENABLE(CPU_INT_NMI);/* Enable NMIE INTR_GLOBAL_ENABLE; CSR*/ INTR_ENABLE(11);
DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit0_done TRUE; return;
Appendix
STB1_SLAVE.C V1.00 Copyright 1998 Texas Instruments Incorporated 04/15/98: Shaku Anjanaiah stb1_slave.c: McBSP0 acts ST-bus emulator McBSP1 (defined stb1_slave.c) acts single rate ST-bus device. This test verify Single rate ST-bus operation using C6201s. This tcase configures CPU1_McBSP0 ST-bus slave VDB. External derived from FSX0 some glue logic that detected rising edge CLKS. CLKS drives both master slave ST-bus devices. #include "common.h" #define M0TO1 TRUE McBSP0 transmits McBSP1 #define M1TO0 FALSE McBSP1 transmits McBSP0 #define CLKGDV1 #define FPER1
TMS320C6000 McBSP Interface ST-bus Device
#define FWID1 #define XFER_SIZE #define XFER_TYPE DMA_STB #define CLKSM0 CLK_MODE_CLKS #define CLKSM1 CLK_MODE_CLKS #define M0TO1_MSTR TRUE #define M1TO0_MSTR TRUE void init_m0to1(void); void init_M1_srgr(void); volatile new_fsr; void main(void) xfer_size; xfer_type; xmit1_done mcsp1to0 recv0_done mcsp1to0 xmit0_done mcsp0to1 recv1_done mcsp0to1 new_fsr FALSE; FALSE FALSE FALSE FALSE TRUE; TRUE; TRUE; TRUE;
mcsp1to0 M1TO0; mcsp0to1 M0TO1; xfer_size XFER_SIZE; xfer_type XFER_TYPE; SRGR values needed init_M1_srgr(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(1); Now, initialize other control registers McBSP operation (mcsp0to1) init_m0to1(); (mcsp1to0) (;;);
Reset channels switch (xfer_type) case DMA_STB: dma_reset(); set_interrupts(); Initialize service McBSP (mcsp0to1) uses recv DMA0_SRC_ADDR MCBSP_DRR_ADDR(1); DMA0_DEST_ADDR (unsigned int) in1; REG_WRITE (DMA0_XFR_COUNTER_ADDR, xfer_size);
TMS320C6000 McBSP Interface ST-bus Device
LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA0_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, SEN_REVT1, RSYNC, RSYNC_SZ); DMA_START(DMA_CH0); (mcsp1to0) (;;); wait first frame sync enable receiver while (!new_fsr); wait until data received while (!recv1_done); break; reg_dump(); 0x00007000; PowerDown shut MCSP void init_m0to1(void) setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_LOW, FSRP, 1);/* inverted LOAD_FIELD (MCBSP_PCR_ADDR(1), M1TO0_MSTR, CLKRM, clkr1 LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSRM, fsx0 setup LOAD_FIELD (MCBSP_RCR_ADDR(1), SINGLE_PHASE, RPHASE, LOAD_FIELD (MCBSP_RCR_ADDR(1), WORD_LENGTH_8, RWDLEN1, RWDLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), RFRLEN1, RFRLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), DATA_DELAY0, RDATDLY, RDATDLY_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), NO_COMPAND_MSB_1ST, RCOMPAND, RCOMPAND_SZ); SPCR LOAD_FIELD (MCBSP_SPCR_ADDR(1), RXJUST_RJZF, RJUST, RJUST_SZ); LOAD_FIELD (MCBSP_SPCR_ADDR(1), INTM_FRAME, RINTM, RINTM_SZ); Very important enable FRST that internal FSR_int generated when GSYNC SET_BIT (MCBSP_SPCR_ADDR(1), FRST); void init_M1_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1), LOAD_FIELD (MCBSP_SRGR_ADDR(1),
CLKGDV1, CLKGDV, CLKGDV_SZ); FWID1, FWID, FWID_SZ); FPER1, FPER, FPER_SZ); CLKSM1, CLKSM, CLKS_POL_RISING, CLKSP, GSYNC_ON, GSYNC,
TMS320C6000 McBSP Interface ST-bus Device
void reg_dump(void) (int MCBSP_ADDR(0); (int MCBSP_ADDR(1); i++) regdump0[i] m0[i]; regdump1[i] m1[i];
void set_interrupts(void) intr_init(); INTR_MAP_RESET; intr_map(CPU_INT13, ISN_RINT1); Hook interrupt service routine interrupt intr_hook (c_int08, CPU_INT8); intr_hook (c_int13, CPU_INT13); Enable NMIE INTR_ENABLE(CPU_INT_NMI); INTR_GLOBAL_ENABLE; default interrrupt correponding channel INTR_ENABLE(8); enable frame sync interrupt McBSP1) INTR_ENABLE(13);
DATA TRANSFER COMPLETION ISRS interrupt void c_int08(void) recv1_done TRUE; return; frame sync interrupt wakes receiver interrupt void c_int13(void) new_fsr TRUE; SET_BIT (MCBSP_SPCR_ADDR(1), RRST); INTR_DISABLE(13); return;
TMS320C6000 McBSP Interface ST-bus Device
Appendix
COMMON.H V1.00*/ Copyright 1997 Texas Instruments Incorporated #include #include #include #include #include #include #include #include #include #include #include <dma.h> <emif.h> <intr.h> <timer.h> <cache.h> <hpi.h> <mcbsp.h> <regs.h> <stdio.h> <trgcio.h> <stdlib.h>
variables used tcase mcsp0to1; mcsp1to0; volatile xmit1_done; volatile recv0_done; volatile xmit0_done; volatile recv1_done;
#define FALSE #define TRUE
BUFFERS DEFINED data6201.asm #define BUFFER_SIZE #define COMPAND_SIZE 4096 extern extern extern extern extern extern extern extern extern extern extern extern extern in0[BUFFER_SIZE]; in1[BUFFER_SIZE]; out0[BUFFER_SIZE]; out1[BUFFER_SIZE]; regdump0[10]; regdump1[10]; ulawenc[BUFFER_SIZE]; volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned AMR; CSR; IFR; ISR; ICR; IER;
cregister cregister cregister cregister cregister cregister
TMS320C6000 McBSP Interface ST-bus Device
extern extern extern extern extern extern extern extern extern extern extern extern extern
interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt
void void void void void void void void void void void void void
c_nmi01(void); c_int04(void); c_int05(void); c_int06(void); c_int07(void); c_int08(void); c_int09(void); c_int10(void); c_int11(void); c_int12(void); c_int13(void); c_int14(void); c_int15(void);
#define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define
DMA_XFER POLL_XFER INT_XFER GPIO DLB1 DLB2 SPLIT_XFER HW_BYTE DMA_SPI DMA_STB DMA_MCM_FLY DMA_NEW_FRAMESYNC AUTO_INIT DMA_SORT SPLIT_SORT DMA_SYNCERR
#define DMA_BYTE #define DMA_HALFWORD extern void set_interrupts(void); extern void reg_dump(void);
Appendix
DATA6201.ASM V1.00*/ Copyright 1997 Texas Instruments Incorporated .global _in0, _in1, _out0, _out1 .global _regdump0, _regdump1, _ulawenc .data _out0: .eval .loop .word 0x80888880) sets bits check sign extension .word sign extension .eval
TMS320C6000 McBSP Interface ST-bus Device
.endloop _out1: .eval 127, .loop .word 0x80888880) sets bits check sign extension .word sign extension .eval .endloop _in0: .loop .word 0xDEADFACE .endloop _in1: .loop .word 0xDEADFACE .endloop _regdump0: .loop .word 0xDEADFACE .endloop _regdump1: .loop .word 0xDEADFACE .endloop _ulawenc: .eval .loop .word .eval i+1, .endloop
Appendix
Copyright: Texas Instruments, Inc. Proprietary Information -Internal Data stb1b.vhd Description Generate clean using clks clks
TMS320C6000 McBSP Interface ST-bus Device
times (clks2) signal. Added test bench. Assumptions: Operation: Disclaimers: Issues: Revision 5/11/98 Shaku Anjanaiah Generate delayed single rate ST-bus emulation -LIBRARY IEEE; IEEE.std_logic_1164.ALL; WORK.std_arith.ALL; entity stb1b_fsx port( clks2: std_logic; fsx_in: std_logic; clks: std_logic; fsx_out: std_logic); stb1b_fsx; architecture stb1b_fsx signal clks_q: std_logic; signal clks_int: std_logic; begin clks_q (clks_int); DIVIDER PROCESS Generate divide-by-2 clock BEGIN wait until clks2'event clks2 '1'; wait rising edge clks_int clks_q; PROCESS DIVIDER; clks clks_int; LATCH PROCESS Generate fsx_out which external that sampled rising edge CLKS. Therefore, rising edge clks2 used latch fsx_in. BEGIN wait until clks2' event clks2 '1'; fsx_out fsx_in; PROCESS LATCH; bhv;
TMS320C6000 McBSP Interface ST-bus Device
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty, endorsement thereof. Copyright 1999 Texas Instruments Incorporated
TMS320C6000 McBSP Interface ST-bus Device

Shaku Anjanaiah Digital Signal Processing Solutions This document

Top Searches for this datasheet

Other recent searches