Claire Monnet Digital Signal Processor Solutions Abstract Te

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Claire Monnet Digital Signal Processor Solutions Abstract Te

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Understanding Controller TMS320C24x Controller
Claire Monnet Digital Signal Processor Solutions
Abstract
Texas Instruments TMS320F241, TMS320C241 TMS320F243 digital signal processor (DSP) controllers contain on-chip Control Area Network (CAN) module. This module FullCAN controller (Specification 2.0B). This application report describes TMS320X241/3 module. Software examples included different modes operation on-chip module along with application example controlling speed three-phase induction motor using bus.
Contents
TMS320X241/TMS320F243 Module Presentation Different Modes Operation Application Motor Control.31 Conclusion: Appendix Header File: CAN.h.36 Appendix Abbreviations Appendix Programs Used Motor Control Application
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Bus.2 Node TMS320X241/3 Module Block Diagram TMS320X241/3 Module Memory Space Time Configuration Register (BCR) Programming Flow Chart.8 Extended Data Frame.8 Mailbox Initialization Flow Chart Transmit Flow Chart Acceptance Filter Receive Flow Chart Extended Remote Frame.25 Remote Frame Principle (with Auto Answer Set) Remote Request.27 Auto Answer Interrupt Flag Register Error Status Register (ESR) Error Counter Register Master Control Register (MCR) Motor Control Application Send_frequence.asm Flow Chart
Digital Signal Processing Solutions
December 1998
TMS320X241/TMS320F243 Module Presentation
About
Controller Area Network (CAN) multi-master serial that uses broadcast transmit nodes. protocol provides advantages over other communication protocols. example, protocol offers very good price/performance ratio. allows moving data with fast transmission speed Mbit/s) implemented real-time systems. Furthermore, data very reliable error detection sophisticated robust. very flexible offers swaps.
Figure
Sensor speed
Sensor temperature
Motor
Node message:
Node message: Temp
Node messages: rpm, Temp
CAN_H
CAN_L
protocol does address nodes with physical addresses instead sends messages with identifier that recognized different nodes. This identifier functions: used both message filtering determining message priority. determines transmitted message will received particular module also determines priority message when more nodes want transmit same time. controller needs connection transceiver attached Bus. made with twisted pair. transmission rate depends length. smaller than meters transmission rate Mbit/s. controllers connected SN75LBC031, TPIC8233 TPIC82501 transceivers.
Understanding Controller TMS320C24x Controller
Figure Node
F241/3 on-chip module
Transceiver
SN75LBC031
There different types message frames:
data frame moves data bytes) from transmitter receiver(s) remote frame used request transmission data frame associated with specified identifier.
frames standard extended. Standard contains 11-bit extended 29-bit
TMS320C241,TMS320F241 TMS320F243 Module
TMS320x241 TMS320F243 module FullCAN Controller. contains message handler (for transmission reception management frames storage) needs less overhead than with BasicCAN Controller. specification 2.0B Active, meaning module send accept standard (11-bit identifier) extended frames (29-bit identifier) peripheral bit. access control/status registers mailboxes both bit. controller contains mailboxes objects bytes data length:
receive mailboxes (mailboxes transmit mailboxes (mailboxes configurable transmit/receive mailboxes (mailboxes
Understanding Controller TMS320C24x Controller
Figure TMS320X241/3 Module Block Diagram
F241/243 module
Control/Status registers Interrupt logic
transmit buffer
interface/ Memory management unit
control
Core
Transceiver
mailbox mailbox mailbox mailbox mailbox mailbox
temporary receive buffer data
matchid
24x32
Control logic
Acceptance filter
module contains different 16-bit registers:
Control registers
MDER: Mailbox Direction/Enable Register, enable disable mailboxes configure mailboxes TCR: Transmission Control Register used transmit messages RCR: Receive Control Register used receive messages MCR: Master Control Register, change timing configuration, write configure chip self test mode instance BCR1 BCR2: Configuration Register, configure timing
Status Registers ESR: Error Status Register, display errors GRS: Global Status Register CEC: Error Counter Register
Interrupt Registers IFR: Interrupt Flag Register IMR: Interrupt Mask Register
Local Acceptance Mask Register LAM0H LAM0L: local acceptance mask registers mailboxes LAM1H LAM1L: local acceptance mask registers mailboxes
These registers located data memory from address 0x7100h 0x710Fh (see Figure
Understanding Controller TMS320C24x Controller
Figure TMS320X241/3 Module Memory Space
Data Space
0000 7100
REGISTERS
710F Reserved
7100
7230
CANMDER CANRCR CANBCR1 CANESR CANCEC CANIMR CANLAM0L CANLAM1L
CANTCR CANMCR CANBCR2 CANGSR CANIFR CANLAM0H CANLAM1H Reserved
7200
FFFF
Mailbox Mailbox Mailbox Mailbox Mailbox 7230 Mailbox
CANMSGIDL CANMSGIDH CANMSGCTRL Reserved DATA DATA DATA DATA
module contains mailboxes. Each mailbox divided into several parts:
MSGIDL MSIDH contain Identifier mailbox. MSGCTRL (Message control field) contains length message transmit receive) (Remote Transmission Request used send remote frames). DATA_A DATA_D contain data. data divided into four words into eight bytes.
Different Modes Operation
Initialize Module
module, registers must initialized.
Timing Synchronization
nominal time programmable each node bus. must equal each node. When node receives frame, necessary receiver synchronize with transmitter. types synchronization exist:
Hard Synchronization: when Start Frame received
Understanding Controller TMS320C24x Controller
Resynchronization: compensate oscillator drift phase difference between transmitter receiver oscillators. TSEG1 lengthened TSEG2 shortened move sample point position. maximum amount (Synchronization jump width).
Figure Time
Nominal Time SYNCSEG Transmit point PROPSEG TSEG1 TSEG2
Sample point
SYNCSEG: segment used synchronize nodes bus. edge expected during this segment. PROPSEG: period time used compensate physical delay time within network. nominal time divided time quanta: time (TSEG1 TSEG2 Length_of_1_time_quantum
Lenght time quantum
BRP= Baud rate prescaler ICLK= frequency clock 20MHz transmission rate 1Mbit/s (bit length ms), following settings correct: BRP=0 TSEG1=5 TSEG2=4 BRP=1 TSEG1=12 TSEG2=7 These parameters configurable user register).
Figure Configuration Register (BCR)
Notes: BRP: Baud Rate Prescaler SBG: Synchronization falling edge
TSEG1
TSEG2
Understanding Controller TMS320C24x Controller
SJW: Synchronization jump width SAM: Sample point setting
change timing configuration:
Step
Change configuration Request register.
CANMCR 0001000000000000b Change configuration request
Step
register (Bit Configuration Register). nodes must have same nominal time same baud rate prescaler. TSEG1 TSEG2 cannot activated.
TSEG1 TSEG
CANBCR2 0000000000000000b baud rate prescaler CANBCR1 0000000101010111b Synchronization falling edge Synchronization jump width module samples only once TSEG1 1010 TSEG2
Step
Request normal mode.
CANMCR 0000000000000000b
Understanding Controller TMS320C24x Controller
Figure Programming Flow Chart
Request Configuration Mode CCR=1 (MCR)
CCE=1?
Change Timing parameters register
Request Normal Mode CCR=0 (MCR)
CCE=0?
CCE= Change Configuration Enable (Global Status Register)
Mailboxes Initialization
Figure Extended Data Frame
Arbitration Field 11-bit Identifier 18-bit Identifier Control Field Data Field
Bytes Data
Each data frame divided several fields:
arbitration field contains Identifier (Remote Transmit Request) bit. control field contains (data length).
data field
user setting mailboxes content program these fields:
Understanding Controller TMS320C24x Controller
MSGIDL MSIDH contain Identifier mailbox. MSGCTRL (message control field) contains length message (Remote Transmission Request used send remote frames). four words eight bytes.
DATA_A, DATA_B, DATA_C DATA_D contain data. data divided
initialize mailboxes:
Step
Disable mailboxes writing CANMDER.
CANMDER 0000000000000000b
Step
Change Data Field Request CANMCR.
CANMCR 0000000100000000b
Step Step
Change mailbox contents (data, control identifier fields). data only transmit mailboxes (2,3,4 Return normal mode.
CANMCR 0000000000000000b
Step
Enable mailboxes.
CANMDER 0000000000000100b ME2= mailbox enable MD2= mailbox configured transmit mailbox
Figure Mailbox Initialization Flow Chart
Disable mailbox: ME=0 (MDER)
Change Data Field Request: CDR=1 (MCR)
Change mailbox (ID, control data)
Request Normal Mode: CDR=0 (MCR)
Enable mailbox: ME=1 (MDER)
Understanding Controller TMS320C24x Controller
Example
;************ Registers configuration ****************
SPLK
#0001000000000000b,CANMCR FEDCBA9876543210
Master Control Reg.
Change configuration request
W_CCE
BITCANGSR, #0Bh BCND W_CCE,
Wait Change ;Configuration request
SPLK
#0000000000000000b,CANBCR2 FEDCBA9876543210
Configuration register
8-15
Baud rate prescaler Reserved
SPLK
#0000000001010111b,CANBCR1 FEDCBA9876543210
Configuration register
TSEG1 TSEG2 Sample point setting times, once) Synchronization jump width Synchronization falling edge Reserved
SPLK
#0000000000000000b,CANMCR FEDCBA9876543210
Master Control register
;bit
Normal mode requested
W_NCCE
BITCANGSR,#0Bh BCND W_NCCE,TC
Wait normal mode
Understanding Controller TMS320C24x Controller
;************* Configure before writing *************
SPLK
#0E2h #0000000000000000b,CANMDER FEDCBA9876543210
7100h Mailbox Direction /Enable Register
disable mailboxes mailbox configured transmit reserved
SPLK
#0000000100000000b,CANMCR FEDCBA9876543210
Master Control register
CDR: Change data field request
;************* Write Mailboxes *************
SPLK #0E4h #1111111111111111b,CANMSGID3H FEDCBA9876543210 7200h message identifier
0-12
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK
#1111111111111111b,CANMSGID3L FEDCBA9876543210
0-15
Lower part extended identifier
SPLK
#0000000000001000b,CANMSGCTRL3 control field FEDCBA9876543210
;bit ;bit
Data length code: 1000 bytes data frame
Understanding Controller TMS320C24x Controller
SPLK SPLK SPLK SPLK
#0123h,CANMBX3A #4567h,CANMBX3B #89ABh,CANMBX3C #0CDEFh,CANMBX3D
Message transmit
;************** parameters after writing **************
SPLK #0E2h #0000000000000000b,CANMCR FEDCBA9876543210 Normal mode requested 7100h Master Control register
SPLK
#0000000001001100b,CANMDER FEDCBA9876543210
Mailbox Direction /Enable Register
disable mailbox disable mailbox enable mailbox enable mailbox disable mailbox disable mailbox mailbox configured receive(1) mailbox
mailbox configured transmit(0) mailbox reserved
Understanding Controller TMS320C24x Controller
Transmit Message
Transmit Message
Step
Initialization transmit mailbox: Disable mailboxes writing CANMDER.
CANMDER 0000000000000000b
Change Data Field Request writing CANMCR.
CANMCR 0000000100000000b
message transmit mailbox. Writing CANMSGIDxH CANMSGIDnL with 2,3,4
CANMSGIDnH 1110000000000000b message sent extended identifier bits) corresponding acceptance mask used register) Auto answer mode set. this mailbox receive remote frame, will answer sending back contents 12-0 upper part identifier. CANMSGIDnL 0000000000001111b lower part identifier.
message control field. Writing CANMSGCTRLn with
2,3,4 message send remote frame will length message will chosen here.
CANMSGCTRLn 0000000000001000b data frame will sent (not remote frame) 1000 data length bytes
Create message data frame only). message will written CANMBXnA, CANMBXnB, CANMBXnC CANMBXnD (with 2,3,4
CANMBXnA 0ABCDh CANMBXnB 0123h CANMBXnC 0EF32h CANMBXnD 6789h
Request Normal operation resetting CANMCR.
CANMCR 0000000000000000b
Enable mailbox writing CANMDER register. mailboxes have been chosen, they will have configured transmit mailboxes (CANDER register).
CANMDER 0000000000000100b ME2= mailbox enable MD2= mailbox configured transmit mailbox
Step
Request transmit message setting register.
Understanding Controller TMS320C24x Controller
0000000000010000b TRS2 Transmission request mailbox
Step Step
Wait transmit acknowledge Register) and/or mailbox flag (CANIFR register). reset transmit flag, need written (TCR register).
0001000000000000b reset interrupt flag mailbox
Figure Transmit Flow Chart
message control data transmit (see mailbox initialization)
Enable transmit mailbox with MDER mailbox direction)
Transmission Request TRS=1 (TCR)
Interrupt Flag?
Reset Transmit acknowledge flag TA=1 (TCR)
Example
;************ Configure Shared Pins ***********
SPLK #225 #0FFFFH,OCRA
Understanding Controller TMS320C24x Controller
SPLK
#0FFF3H,OCRB
;************ Configure before writing ***********
SPLK #0E2h #0000000000000000b,CANMDER FEDCBA9876543210 disable mailboxes 7100h Mailbox Direction /Enable Register
SPLK
#0000000100000000b,CANMCR FEDCBA9876543210
Master Control Reg.
CDR: Change data field request
;************ Write Mailboxes *************
SPLK #0E4h #1111111111111111b,CANMSGID5H FEDCBA9876543210 7200h message identifier
;bit 0-12 ;bit ;bit ;bit
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK
#1111111111111111b,CANMSGID5L FEDCBA9876543210
0-15
Lower part extended identifier
SPLK
#0000000000001000b,CANMSGCTRL5 control field FEDCBA9876543210
Data length code: 1000 bytes data frame
SPLK SPLK
#0123h,CANMBX5A #4567h,CANMBX5B
Message transmit
Understanding Controller TMS320C24x Controller
SPLK SPLK
#89ABh,CANMBX5C #0CDEFh,CANMBX5D
;************ parameters after writing *************
SPLK
#0E2h #0000000000000000b,CANMCR FEDCBA9876543210
7100h Master Control Reg.
Normal mode requested
SPLK
#0000000001100000b,CANMDER FEDCBA9876543210
Mailbox Direction /Enable Register
disable mailboxes enable mailbox
;************** Mailbox Transmission **************
SPLK
#0080h,CANTCR
Transmit request mailbox
W_TA
BITCANTCR,0 BCND W_TA,NTC
Wait transmission
W_FLAG
BITCANIFR,2 BCND SPLK W_FLAG,NTC #2000h,CANTCR
Wait mailbox interrupt flag Reset mailbox flag
Understanding Controller TMS320C24x Controller
Receive message
Acceptance Filter Works
Figure Acceptance Filter
Message
Message Mailbox Comparison
Accepted?
Mailbox
Acceptance Mask Reg.
bits that masked local Acceptance Mask register need identical received message receive mailbox this case, message neither accepted stored. local acceptance mask disabled fixing (Acceptance Mask Enable bit) message Identifier high word (MSGIDn). Then identifier bits must match store message.
Example:
Message 0000 0000 0000 0000 0000 1111 0000 Mailbox 0000 0000 0000 0000 0000 0000 0000 Acceptance mask 0000 0000 0000 0000 0000 1111 0000 masked bit) message accepted Acceptance mask 0000 0000 0000 0000 0000 0000 1111 message refused
Program Module
Step
local acceptance mask register. LAM1 used mailboxes LAM0 used mailboxes
LAM1H 1000000000000000b LAMI standard extended frames received 12-0 corresponding masked. these bits received message same than mailbox LAM1L= 1111111111111111b 15-0 masked
Step
mailbox Identifier Control. Disable mailboxes writing MDER.
Understanding Controller TMS320C24x Controller
CANMDER 0000000000000000b
Change Data Field Request writing register.
CANMCR 0000000100000000b
message transmit mailbox. Writing MSGIDxH MSGIDnL with 2,3,4
CANMSGIDnH 1110000000000000b received message extended identifier bits) corresponding acceptance mask used register) influence receiver. CANMSGIDnL 0000000000001110b Lower part identifier.
message control field. Writing MSGCTRLn with 2,3,4 message send remote frame will length message will chosen here.
CANMSGCTRLn 0000000000001000b data frame requested. 1000 data length bytes
Request Normal operation resetting MCR.
CANMCR 0000000000000000b
Enable mailbox writing MDER register. mailbox chosen, will have configured receive mailbox (MDER register).
CANMDER 0000000001000100b ME2= mailbox enable MD2= mailbox configured receive mailbox
Step Step
Wait receive acknowledge (RMP register) mailbox interrupt flag CANIFR. reset receive flag, must written Receive Control Register).
CANRCR 0000000001000000b RMP2 reset RMP2 mailbox interrupt flag
data stored MBXnA, MBXnB, MBXnC MBXnD.
Understanding Controller TMS320C24x Controller
Figure Receive Flow Chart
Local Acceptance Mask disable
mailbox (See mailbox initialization)
Enable receive mailbox (MDER) mailbox direction.
RMP? Interrupt flag?
Reset Receive Message Pending interrupt flag.
Example
;************* Configure Shared Pins **************
LDPK SPLK SPLK
#225 #0FFFFH,OCRA #0FFF3H,OCRB
;************** Local Acceptance Mask **************
SPLK
#0E2h
7100h
#1001111111111110b,CANLAM0H local acceptance
Understanding Controller TMS320C24x Controller
;mask mailboxes SPLK #1111111111111111b,CANLAM0L 1:don't care
;*********** Configure before writing ************
SPLK
#0000000000000000b,CANMDER FEDCBA9876543210
Mailbox Direction /Enable Register
disable mailboxes
SPLK
#0000000100000000b,CANMCR FEDCBA9876543210
Master Control Reg.
CDR: Change data field request
;**************** Write Mailboxes **************
SPLK
#0E4h #1111111111111111b,CANMSGID0H FEDCBA9876543210
7200h mailbox identifier
;bit 0-12 ;bit ;bit ;bit
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK
#1111111111111111b,CANMSGID0L FEDCBA9876543210
;bit 0-15
Lower part extended identifier
;************ parameters after writing ************
SPLK
#0E2h #0000000000000000b,CANMCR
7100h Master Control Reg.
Understanding Controller TMS320C24x Controller
FEDCBA9876543210 Normal mode requested
SPLK
#0000000000000001b,CANMDER FEDCBA9876543210
Mailbox Direction /Enable Register
enable mailbox disable mailbox
;***************** RECEIVE ****************
W_RA
BITCANRCR,11 BCND W_RA,NTC
Wait receive
W_FLAG
BITCANIFR, BCND W_FLAG,NTC
Wait mailbox interrupt flag
SPLK
#0010h,CANRCR
Reset CANIFR
Self-Test Mode
What Self-Test Mode?
TMS320F241/3 module operate loop-back mode. receive transmitted message. module generates acknowledge signal. This mode operates without connected module, making convenient test programs.
Self-Test Mode
After module initialization, user request Self-Test Mode setting Self-Test Mode register.
CANMCR 00000000010000000b module self-test mode.
messages transmitted will received stored appropriate receive mailbox.
Self-Test Mode Limitation
remote frame handling with Auto Answer Mode implemented SelfTest mode. This mode cannot used remote frame testing.
Understanding Controller TMS320C24x Controller
Self-Test Mode Example
;************ Timing Configuration *************
SPLK
#0001000000000000b,CANMCR
Change configuration request
W_CCE
BITCANGSR,#0Bh BCND W_CCE,NTC
Wait Change configuration enable
SPLK
#0000000000000000b,CANBCR2
Baud rate prescaler SPLK #0000010101010111b,CANBCR1 TSEG1 TSEG2 Sample point setting times, once) Synchronization jump width Synchronization falling edge Reserved
SPLK
#0000000000000000b,CANMCR
W_NCCE
BITCANGSR,#0Bh BCND W_NCCE,TC
Wait Change configuration disable
;*********** Configure before writing ************
SPLK
#0E2h #0000000000000000b,CANMDER FEDCBA9876543210
7100h Mailbox Direction /Enable Register
disable mailboxes
SPLK
#0000000100000000b,CANMCR
Master Control Reg.
CDR: Change data field request
Understanding Controller TMS320C24x Controller
;*************** Write Mailboxes ****************
SPLK
#0E4h #1111111111111111b,CANMSGID2H FEDCBA9876543210
7200h message identifier
;bit 0-12 ;bit ;bit ;bit
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK
#1111111111111010b,CANMSGID2L Lower part extended identifier
;bit 0-15
SPLK
#0000000000001000b,CANMSGCTRL2 control field FEDCBA9876543210
;bit ;bit
Data length code: 1000 bytes data frame
SPLK
#1111111111111111b,CANMSGID3H FEDCBA9876543210
message identifier
;bit 0-12 ;bit ;bit ;bit
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK
#1111111111111111b,CANMSGID3L Lower part extended identifier
;bit 0-15
SPLK
#0000000000001000b,CANMSGCTRL3 control field FEDCBA9876543210
;bit ;bit
Data length code: 1000 bytes data frame
Understanding Controller TMS320C24x Controller
SPLK SPLK SPLK SPLK
#0123h,CANMBX3A #4567h,CANMBX3B #89ABh,CANMBX3C #0CDEFh,CANMBX3D
Message transmit
;********** parameters after writing ***********
SPLK ;bit
#0E2h #0000000001000000b,CANMCR FEDCBA9876543210 Self mode test
7100h Master Control Reg.
SPLK
#0000000001001100b,CANMDER FEDCBA9876543210
Mailbox Direction /Enable Register
disable mailbox disable mailbox enable mailbox enable mailbox disable mailbox disable mailbox mailbox receive mailbox transmit
;*********** TRANSMIT ************
SPLK
#0020h,CANTCR
;Transmit request mailbox
W_TA
BITCANTCR,2 BCND W_TA,NTC
Wait transmission acknowledge
Understanding Controller TMS320C24x Controller
W_FLAG3
BITCANIFR,4 BCND SPLK W_FLAG3,NTC #2000h,CANTCR
Wait interrupt flag
Reset CANIFR
;************ RECEIVE ************
W_FLAG2
BITCANIFR,5 BCND W_FLAG2,NTC
Wait interrupt flag
W_RA
BITCANRCR,9 BCND SPLK W_RA,NTC #0040h,CANRCR
Wait receive acknowledge
reset CANIFR
Remote Frame
Remote frames have same shape data frames contain data. (Remote Transmission Request) remote frame Similar data frames, they standard extended (11-bit 29-bit ID).
Figure Extended Remote Frame
Control Field
Arbitration Field
11-bit Identifier 18-bit Identifier
Remote frames usually requesting information. Node sends remote frame node node message transmit with same identifier remote frame, will answer, sending corresponding data frame bus.
Figure Remote Frame Principle (with Auto Answer Set)
Node
Node
Understanding Controller TMS320C24x Controller
Program Remote Frame
Send Remote Frame:
mailbox Mailboxes configured either transmit mailboxes receive mailboxes. (Remote Transmission Request) MSGCTRLn field. (Transmission Request Set) remote frame will sent bus. remote frame sent from receive mailbox (Transmit Acknowledge) mailbox flag after successful transmission. then reset.
Automatic Answer Remote Frame:
mailbox that receives remote frame answers automatically sending data frame.
Only mailbox configured transmit mailbox Auto Answer Mode (AAM) MSGIDn. node receives remote frame with same than mailbox will automatically answer sending data frame (for local acceptance mask disabled).
Sending Remote Frame Receive Mailbox:
Example:
Only mailboxes configured receive mailboxes message handled like data frame. (Receive Message Pending) (Remote Frame Pending) set. handles situation.
Step
Sending remote frame from mailbox (node (Remote Transmission Request) mailbox set. Mailbox will send remote frame when requested. Then, when corresponding (Transmission Request Set) register (Transmit Control Register) set, remote frame sent bus. local acceptance mask disabled (MSGID2H 14), transmitted bits (mailbox node receive mailbox bits (mailbox node must match accept frame. Node recognizes remote frame Mailbox (node mailbox (node have same 29-bit identifier.
Understanding Controller TMS320C24x Controller
Figure Remote Request
Node Node
TCR=0080h RTR=1
Mailbox Mailbox
Mailbox
AAM=1
MAILBOX Settings: MSGID5H=1101001100001111b Extended Acceptance mask enable Auto Answer Mode 12-0: Identifier MSGID5L=1111111111111111b 15-0: Identifier MSGCTRL5=0000000000011000b Remote Transmission Request
MAILBOX Settings: MSGID2H=1011001100001111b Extended Acceptance mask disable Auto Answer Mode 12-0: Identifier MSGID2L=1111111111111111b 15-0: Identifier MSGCTRL2=0000000000001000b 3-0: 1000 data length=8 bytes
Step
Node Auto-answer node (Auto Acceptance Mode) set, mailbox answers automatically sending corresponding data frame bus. node local acceptance mask enabled mailbox (MSGID0H, 14). non-masked bits data frame sent node match with mailbox bits, data frame accepted stored mailbox
Figure Auto Answer
Node Node
RCR=0010h
Mailbox Mailbox Mailbox
Understanding Controller TMS320C24x Controller
MAILBOX Settings: LAM0H=1000000000000000b Extended Standard accepted 12-0:0 Transmitted mailbox must match identically LAM0L=1111111111111111b 15-0: Accept
MSGID0H=1101001100001111b Extended Acceptance mask enable Auto Answer Mode 12-0: Identifier MSGID0L=1010101011110000b 15-0: Identifier MSGCTRL5=0000000000001000b 3-0: 1000 data length=8 bytes
Interrupts
module contains interrupts registers:
CANIFR: Interrupt Flag register CANIMR: Interrupt Mask register
There different types interrupts: Interrupts generated mailbox, mailbox receives transmits message. Each mailbox interrupt flag CANIFR interrupt mask CANIMR. Interrupts generated error. Several events generate error interrupts:
Abort acknowledge Write denied Wake Receive message lost Error Passive
Warning Level
Understanding Controller TMS320C24x Controller
Figure Interrupt Flag Register
Mailbox Interrupt Flags
Error Interrupt Flags
These interrupts assert either high priority request priority request. Bits CANIMR used select priority. interrupt requests sent Peripheral Interrupt Expansion (PIE):
mailbox interrupt (high priority) error interrupt (high priority)
Error Handling
module includes error detection, internal error handling mechanism error signaling. This provides reliable robust data handling mechanism. module detects following error types:
error transmitted received different. Stuffing error. After five consecutive equal bits, sender supposed insert stuff with complementary value into stream, which removed receivers. error, received (Cyclic redundancy check) code does match transmitted code. error, transmitting node receives from receiver(s). Form error, violation frame format occurs.
These errors recorded Error Status Register:
Figure Error Status Register (ESR)
Form Error Flag
Stuck Dominant
Stuff Error Status Error
Warning Status
Error Flag
Error
Error Passive Status
Understanding Controller TMS320C24x Controller
Each node that detects error, increments error counter (transmit receive). These counters Error Counter Register (CEC).
Figure Error Counter Register
TEC: Transmit Error Register
REC: Receive Error Register
module three different states:
Error Active State: transmit receive error counters below 128. counters reach flag CANIFR register (bit warning flag) Error Status Register equal Error Passive State: transmit error counter receive error counter between 255. flag CANIFR (bit Error Status Register equal State: transmit error counter greater than 255. Then node automatically disconnected from bus. flag CANIFR (bit Error Status Register equal 1.The (MCR register) (MCR register).
Figure Master Control Register (MCR)
Change Configuration Request
Auto
reconnect module after bus-off condition, different solutions exist:
(Auto register. module will back bus-on state after 128*11 consecutive recessive bits.
clear (Change Configuration Request) register.
Understanding Controller TMS320C24x Controller
Application Motor Control
General Description
goal this application send speed command motor drive vary motor speed. implement this application, twisted pair bus), SN75LBC031 transceivers TMS320F243 DSPs, used. motor controlled threephase induction motor.
Figure Motor Control Application
Motor
Power Supply 0-5V
S320F243
controller
TMS320F243 including controller
transceiver SN75LBC031
CAN_H
transceiver SN75LBC031
CAN_L
power supply connected ADC0 input TMS320F243 controller. This value read frequency target motor control. first (node converts this value digital value using module then scales Volts corresponds frequency Volts rpm. data stored mailbox then sent second (node bus. This controls motor using frequency target received. motor speed changed real time varying input voltage. implement this application, different programs needed. first node, software handles transmission frequency target bus. second node, program handles reception frequency also performs motor control.
Understanding Controller TMS320C24x Controller
Node From Power Supply
connected power supply (ADC0 input) transceiver. program running this called send_frequency.asm. This program handles module initialization, analog-to-digital conversion, scaling frequency, storage inside mailbox sends bus. Figure describes process. this program used three times:
initialization (mailbox timing) Storage frequency mailbox Transmission message
initialization mailbox timing described details part this application report. storage frequency follows same principle mailbox initialization. Before updating data value, mailbox needs disabled (Change configuration request) Master Control Register must set. After changing frequency, this must cleared mailbox enabled.
Code:
SPLK ;bit #DP_CAN #0000000000000000b,CANMDER
Disable each mailbox
SPLK ;bit
#0000000100000000b,CANMCR |||||||||||||||| FEDCBA9876543210
CDR: Change data field request
LACL SACL SPLK ;bit ;bit
#04h GPR0 #DP_CAN2 CANMBX3A #DP_CAN #0000010000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 Load frequency value inside mailbox
CDR: Change data field request Data byte order. First sent:0,1
Understanding Controller TMS320C24x Controller
SPLK ;bit ;bit
#0000000001001000b,CANMDER |||||||||||||||| FEDCBA9876543210
Enable mailbox mailbox =transmit
transmit message, (Transmit request set) Transmit Control register set. After transmission Transmit Acknowledge flag mailbox interrupt flag appear.
Code:
SPLK #0020h,CANTCR Transmit request mailbox
W_TA
BCND
CANTCR,2 W_TA,NTC
Wait transmission acknowledge
W_FLAG
BCND SPLK
CANIFR,4 W_FLAG,NTC #2000h,CANTCR
Wait interrupt flag
Reset flag
Understanding Controller TMS320C24x Controller
Figure Send_frequence.asm Flow Chart
Mailbox Initialization Identifier control fields Initialization Timing Initialization
Initialization
Start Conversion
flag?
Scale result Frequency ADC/80 Store frequency mailbox data field
Request transmission
Transmission flag?
Node Motor Control
second handles motor control using target frequency value received from bus.
Understanding Controller TMS320C24x Controller
this example application, open loop control program motor used. detail description main motor control software found application report, Induction Motor Control using Constant V/HZ Principle Space Vector Technique with TMS320C240, Literature number SPRA284A. motor control program works with interrupt system. contains important parts: main program interrupt service routine (ISR). main program, different initializations made, such module initialization initialization. main program, underflow interrupt event manager enabled. interrupt service routine, factors calculated adjust frequency target received bus. Inside this ISR, value frequency target updated value received different older value. code divided into parts: first part initialization where timing mailbox initialized (Control field identifier). This part main program. second part inside interrupt service routine. case successful reception message from bus, this part will handle copy this message variable FREQ_TRGT this value changed. FREQ_TRGT value subtracted value received. result zero, FREQ_TRGT updated. section program reading follows:
CAN_RD #0e2h Load registers data page (7100h)
W_FLAG
BCND
CANIFR,7 CAN_RD_END,NTC
wait mailbox interrupt flag
W_RA
BCND
CANRCR,11 CAN_RD_END,NTC
Wait receive acknowledge
SPLK
#0010h,CANRCR
reset CANIFR
LACL BCND LACL SACL
#0E4h CANMBX0A #04h FREQ_TRGT CAN_RD_END,EQ #0E4h CANMBX0A #04h FREQ_TRGT
Load mailboxes data page (7200h) Load data received Accumulator Load data page
value doesn't change
Freq_trgt updated load data page (200h) Change FREQ_TRGT
Understanding Controller TMS320C24x Controller
CAN_RD_END:
When successful reception from occurs, mailbox interrupt flag Receive Message Pending bits set. program tests these bits (BIT instruction). these bits set, they cleared next instruction. data received then copied into accumulator FREQ_TRGT variable, this value been changed. mailbox flag received there message pending (RMP bit), branch CAN_RD_END occurs. program used this application found Appendix
Remarks
This example describes application motor control using CAN. goal this application demonstrate that using controller simple does require large memory space. initialization (that used only once) requests words reading part needs words. course, highest protocol, such CANopen, SDS, DeviceNet Kingdom, needs more memory space than this basic example application. Applications with higher number nodes also implemented. user decides priority each message different nodes exchange information using bus.
Conclusion:
TMS320F241, TMS320C241 TMS320F243 chips contain on-chip controller. multi-master serial that allows efficient transmission data between different nodes. flexible, reliable, robust standardized protocol with real-time capabilities. controllers improve efficiency electrical motors with higher performance lower costs, offering preferred solution traditional microcontrollers allowing more sophisticated control algorithms. This application report shows program controller include this program motor control application.
Appendix Header File: CAN.h
Registers.
CANMDER CANTCR
.set 7100h .set 7101h
Mailbox Direction/Enable register Transmission Control Register
Understanding Controller TMS320C24x Controller
CANRCR CANMCR CANBCR2 CANBCR1 CANESR CANGSR CANCEC CANIFR CANIMR CANLAM0H CANLAM0L CANLAM1H CANLAM1L
.set 7102h .set 7103h .set 7104h .set 7105h .set 7106h .set 7107h .set 7108h .set 7109h .set 710ah .set 710bh .set 710ch .set 710dh .set 710eh
Receive Control Register Master Control Register Configuration Register Configuration Register Error Status Register Global Status Register Transmit Receive counters Interrupt Flag Registers Interrupt Mask Registers Local Acceptance Mask MBx0/1 Local Acceptance Mask MBx0/1 Local Acceptance Mask MBx2/3 Local Acceptance Mask MBx2/3
Mailboxes
CANMSGID0L bits) CANMSGID0H bits)
.set 7200h .set 7201h
Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox
CANMSGCTRL0 .set 7202h CANMBX0A CANMBX0B CANMBX0C CANMBX0D .set 7204h .set 7205h .set 7206h .set 7207h
CANMSGID1L bits) CANMSGID1H bits)
.set 7208h .set 7209h
Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox
CANMSGCTRL1 .set 720Ah CANMBX1A CANMBX1B CANMBX1C CANMBX1D .set 720Ch .set 720Dh .set 720Eh .set 720Fh
Understanding Controller TMS320C24x Controller
CANMSGID2L bits) CANMSGID2H bits)
.set 7210h .set 7211h
Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox
CANMSGCTRL2 .set 7212h CANMBX2A CANMBX2B CANMBX2C CANMBX2D CANMSGID3L bits) CANMSGID3H bits) .set 7214h .set 7215h .set 7216h .set 7217h .set 7218h .set 7219h
CANMSGCTRL3 .set 721Ah CANMBX3A CANMBX3B CANMBX3C CANMBX3D .set 721Ch .set 721Dh .set 721Eh .set 721Fh
CANMSGID4L bits) CANMSGID4H bits)
.set 7220h .set 7221h
Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox
CANMSGCTRL4 .set 7222h CANMBX4A CANMBX4B CANMBX4C CANMBX4D .set 7224h .set 7225h .set 7226h .set 7227h
CANMSGID5L bits) CANMSGID5H bits)
.set 7228h .set 7229h
Message mailbox (lower Message mailbox (upper bytes Mailbox bytes Mailbox bytes Mailbox bytes Mailbox
CANMSGCTRL5 .set 722Ah CANMBX5A CANMBX5B CANMBX5C CANMBX5D .set 722Ch .set 722Dh .set 722Eh .set 722Fh
Understanding Controller TMS320C24x Controller
Appendix Abbreviations
Notation: AAIF: AAIM: AAM: ABO: ACKE: AME: BEF: BOIF: BOIM: BRP: CCE: CCR: CDR: CRCE: DBO: DLC: EIL: EPIF: EPIM: FER: IDE: LAMI: MBNR: MIF: MIL: MIM: OPC: PDA: PDR: REC: RFP: RML: RMLIF: RMLIM: RMP: RTR: SA1: SAM: SBG: SER: Signification: Abort Acknowledge Abort Acknowledge Interrupt Flag Abort Acknowledge Interrupt Mask Auto Answer Mode Auto Acknowledge Error Acceptance Mask Enable Error Flag Status Interrupt Flag Interrupt Mask Baud Rate Prescaler Change Configuration Enable Change Configuration Request Change Data Field Request Error Data Byte Order Data Length Code Error Interrupt Priority Level Error Passive Status Error Passive Interrupt Flag Error Passive Interrupt Mask Warning Status Form Error Flag Identifier Extension Local Acceptance Mask Identifier Mailbox Number Mailbox Enable Mailbox Direction Mailbox Interrupt Flag Mailbox Interrupt Priority Level Mailbox Interrupt Mask Overwrite Protection Control Power Down Mode Acknowledge Power Down Mode Request Receive Error Counter Remote Frame Pending Receive Mode Receive Message Lost Receive Message Lost Interrupt Flag Receive Message Lost Interrupt Mask Receive Message Pending Remote Transmission Request Stuck dominant Error Sample Point Setting Synchronization Both Edge Stuff Error Register: MSGIDn MSGIDn BCR2 MSGCTRLn MSGIDn MDER MDER MSGCTRLn BCR1 BCR1 11:8 13:8 13:8 15:12 11:8
Understanding Controller TMS320C24x Controller
SJW: SMA: STM: SUSP: TEC: TRS: TRR: WDIF: WDIM: WLIF: WLIM: WUBA: WUIF: WUIM:
Synchronization Jump Width Suspend Mode Acknowledge Self Test Mode Action Emulator Suspend Transmission Acknowledge Transmit Error Counter Transmit Mode Transmission Request Transmission Request Reset Write Denied Interrupt Flag Write Denied Interrupt Mask Warning Level Interrupt Flag Warning Level Interrupt Mask Wake Activity Wake Interrupt Flag Wake Interrupt Mask
BCR1
15:12 15:8
Appendix Programs Used Motor Control Application
NODE Send_Frequence.asm
File Name: Originator: Target Sys: Description: 29th 1998 Send_Frequence.asm Claire Monnet TMS320F243 voltage sent F243 EVM, transformed (Texas Instruments)
ADC, scaled between store mailbox before sent bus.
;*************** .def .bss
Debug directives GPR0 GPR0,1
********************
;General purpose register
;***************
Peripheral Registers .include "X24x.h"
********************
;*************** DP_PF1 DP_CAN DP_CAN2 .set .set .set
Constant definitions 0E0h 0E2h 0E4h
*******************
Page peripheral file (7000h/80h Registers page (7100h)
page (7200h)
Understanding Controller TMS320C24x Controller
;*************** KICK_DOG
Definitions .macro SPLK SPLK .endm #00E0h #05555h, WDKEY #0AAAAh, WDKEY
*******************
Watchdog reset macro
;**************
Vector address declarations
***************
.global _c_int0 .sect ".vectors"
RSVECT INT1 INT2 INT3 INT4 INT5 INT6 RESERVED SW_INT8 SW_INT9 SW_INT10 SW_INT11 SW_INT12 SW_INT13 SW_INT14 SW_INT15 SW_INT16 TRAP EMU_TRAP SW_INT20 SW_INT21 SW_INT22
_c_int0
Reset Vector
PHANTOM level PHANTOM level PHANTOM level PHANTOM level PHANTOM level PHANTOM Cint level PHANTOM (Analysis Int) PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM
User User User User User User User User User Trap vector
maskable Emulator Trap User User User
Understanding Controller TMS320C24x Controller
SW_INT23
PHANTOM
User
starts here
.text _c_int0: SETC CLRC CLRC INSXM Disable interrupts Clear Sign Extension Mode Reset Overflow Mode
LACC SACL KICK_DOG
#DP_PF1 #006Fh WDCR control reg. 7028h
;*************
Configure Wait State Generator
**************
SPLK
#0,61h 61h,0ffffh
;**************
Configure shared pins
***************
LDPK SPLK SPLK
#225 #0FFFFH,OCRA #0FFF3H,OCRB
;*************
Mailbox Initialization
**************
SPLK SPLK
#DP_CAN #0000000000000000b,CANMDER #0000000100000000b,CANMCR |||||||||||||||| FEDCBA9876543210 disable each mailbox
Understanding Controller TMS320C24x Controller
;bit
CDR: Change data field request
SPLK
#DP_CAN2 #1111111111111111b,CANMSGID3H |||||||||||||||| FEDCBA9876543210
;bit 0-12 ;bit ;bit ;bit
Upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK ;bit 0-15
#1111111111111111b,CANMSGID3L
lower part extended identifier
SPLK ;bit ;bit
#0000000000000010b,CANMSGCTRL3 |||||||||||||||| FEDCBA9876543210
Data length code. 0010 bytes data frame
#DP_CAN
SPLK
#0000000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210
;bit
CDR: Change data field request
SPLK
#0000000001001000b,CANMDER |||||||||||||||| FEDCBA9876543210
;bit ;bit
Enable mailbox mailbox configured transmit mailbox
Understanding Controller TMS320C24x Controller
;*************
Timing Configuration
**************
SPLK ;bit
#0001000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210
Change configuration register
W_CCE
BCND
CANGSR,#0Bh W_CCE,NTC
Wait Change configuration enable
SPLK
#0000000000000000b,CANBCR2
Baud rate prescaler
SPLK TSEG1 TSEG2
#0000010101010111b,CANBCR1 |||||||||||||||| FEDCBA9876543210
Sample point setting times, once) Synchronization jump width Synchronization falling edge Reserved
SPLK
#0000010000000000b,CANMCR |||||||||||||||| FEDCBA9876543210
data Byte order: first normal mode
W_NCCE
BCND
CANGSR,#0Bh W_NCCE,TC
Wait Change configuration Disable
;************
Configure Control register
************
SPLK
#DP_PF1 #0000000000000000b, ADCTRL2 ||||||||||||||||
Understanding Controller TMS320C24x Controller
FEDCBA9876543210 Prescaler value FIFO2 status Reserved FIFO1 status Reserved Mask external input Mask input
Reserved
Beginning loop
LOOP
SPLK
#1101000110000001b, ADCTRL1 Start conversion |||||||||||||||| FEDCBA9876543210
Start conversion
Channel address convert Interrupt flag write clear Interrupt mask enable with mask Continuous mode disabled Enable ADC1 Immediate start action Free ignore suspend Soft applicable with
READ_ADC
LACL
ADCTRL1 #0000000100000000B
wait until conversion flag
Interrupt flag #0000000100000000B READ_ADC,
BCND
Understanding Controller TMS320C24x Controller
;***************
Scale
value
*******************
result conversion scaled between volt) volt) Frequence_target ADC_value/80h
SACL #200h #04h GPR0 result stored GPR0 shift times (division 80h) 200h
;**********
Store frequency mailbox
**********
SPLK ;bit
#DP_CAN #0000000000000000b,CANMDER
Disable each mailbox
SPLK ;bit
#0000000100000000b,CANMCR |||||||||||||||| FEDCBA9876543210
CDR: Change data field request
LACL SACL SPLK ;bit
#04h GPR0 #DP_CAN2 CANMBX3A #DP_CAN #0000010000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 Load frequency value inside mailbox
CDR: Change data field request
Understanding Controller TMS320C24x Controller
;bit
Data byte order. First sent:0,1
SPLK ;bit ;bit
#0000000001001000b,CANMDER |||||||||||||||| FEDCBA9876543210
Enable mailbox mailbox =transmit
;***********
Transmit data
**********
SPLK
#0020h,CANTCR
Transmit request mailbox
W_TA
BCND
CANTCR,2 W_TA,NTC
Wait transmission acknowledge
W_FLAG
BCND SPLK
CANIFR,4 W_FLAG,NTC #2000h,CANTCR
Wait interrupt flag
Reset flag
LOOP
Branch beginning loop.
MAIN CODE ends here
ISR: PHANTOM TYPE:
PHANTOM
return
Understanding Controller TMS320C24x Controller
NODE CAN_application.asm
File Name: Originator: Target Sys: Description: Last Update: CAN_application.ASM David Figoli (Texas Instruments) updated Claire Monnet (Texas Instruments) TMS320F243 Board Spectrum digital's Inverter Open loop program This implementation phase Space vector running F243 device. External frequency control provided bus. 1998
Debug directives ;-.def .def .def .def .def .def .def .def .def .def .def .def GPR0 GPR1 GPR2 ALPHA STEP_ANGLE FREQ_SETPT ENTRY_NEW ENTRY_OLD ;General purpose registers.
Understanding Controller TMS320C24x Controller
.def .def .def .def .def .def .def .def
SPEED_HI SPEED_LO SPEED_fb SPEED_sp BCAVG PCNT_SETPT
.include
x24x.h
Constant Declarations Used SBIT0 SBIT1 Macro B15_MSK .set B14_MSK .set B13_MSK .set B12_MSK .set B11_MSK .set B10_MSK .set B9_MSK B8_MSK B7_MSK B6_MSK B5_MSK B4_MSK B3_MSK B2_MSK B1_MSK B0_MSK .set .set .set .set .set .set .set .set .set .set 8000h 4000h 2000h 1000h 0800h 0400h 0200h 0100h 0080h 0040h 0020h 0010h 0008h 0004h 0002h 0001h ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask ;Bit Mask
WSGR DP_PF1 DP_PF2 DP_PF3 DP_EV
.set .set .set .set .set
0FFFFh 0E0h 0E1h 0E2h 0E8h ;page peripheral file (7000h/80h) ;page peripheral file (7080h/80h) ;page peripheral file (7100h/80h) register data page (7400h/80h)
Understanding Controller TMS320C24x Controller
DP_CAN
.set
0E2h 0E4h
Registers (7100h) (7200h)
DP_CAN2 .set
;Space vector constants ;-F1 VF_SLOPE INTERCEPT Vmax Vmin BCNT_MAX RMP_DLY_MAX BC_SIZE BC_BUF_STRT .set .set .set .set .set .set .set .set .set .set 0256 1024 15291 00546 032767 09830 300h ;Low Freq point profile(=15Hz) ;High Freq point profile(=60Hz) ;Volts/Hz slope 1.87 format ;Line equation intercept 0.07 ;0.99999. ;0.40000.
;100x40uS=0.004 depress valid ;100x40uS=0.004 between steps. ;Box average size ;Start buffer
Variable Declarations chip Block ;-.bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss GPR0,1 GPR1,1 GPR2,1 FREQ_SETPT,1 ;Value from FREQ_TRGT,1 XF_STATE,1 B1_CNT,1 B2_CNT,1 ;Frequency Target value ;State (i.e. Flag) button counter (Inc Freq) button counter (Dec Freq) ;Ramp rate adjusting Target freq. ;Forced delay between Re-presses. ;General purpose registers.
RMP_DLY_CNT,1 REPRESS_DLY,1 S_TABLE,1 ALPHA,1 STEP_ANGLE,1 ENTRY_NEW,1 ENTRY_OLD,1 SINVAL,1 SR_ADDR,1
;Data address store Sine table addr.
Understanding Controller TMS320C24x Controller
.bss
SECTOR_PTR,1
.bss .bss .bss .bss .bss .bss
SPEED_HI,1 SPEED_LO,1 SPEED_fb,1 SPEED_sp,1 BCAVG,1 PCNT_SETPT,1
.bss .bss .bss .bss .bss .bss .bss .bss .bss .bss .bss
dx,1 dy,1 Ta,1 Tb,1 Tc,1 vf_slope,1 FREQ_3BIT,1 LED_MASK,1 mSEC,1
Definitions ;-SBIT0 .macro DMA, MASK ;Clear Macro LACC
AND#(0FFFFh-MASK) SACL .endm
SBIT1
.macro DMA, MASK ;Set Macro LACC
#MASK SACL .endm
Understanding Controller TMS320C24x Controller
KICK_DOG
.macro LDP#00E0h SPLK SPLK LDP#0h .endm
;Watchdog reset macro
#05555h, WDKEY #0AAAAh, WDKEY
POINT_PG0
.macro LDP#00h .endm
POINT_B0
.macro LDP#04h .endm
POINT_PF1
.macro LDP#0E0h .endm
POINT_PF2
.macro LDP#0E1h .endm
POINT_EV
.macro LDP#0E8h .endm
Vector address declarations ;-.global _c_int0 .sect ".vectors"
RSVECT INT1 INT2
_c_int0 PHANTOM PWM_ISR
Reset Vector level level
Understanding Controller TMS320C24x Controller
INT3 INT4 INT5 INT6 RESERVED SW_INT8 SW_INT9 SW_INT10 SW_INT11 SW_INT12 SW_INT13 SW_INT14 SW_INT15 SW_INT16 TRAP EMU_TRAP SW_INT20 SW_INT21 SW_INT22 SW_INT23
PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM
level level level level (Analysis Int) User User User User User User User User User Trap vector maskable Emulator Trap User User User User
starts here
.text _c_int0: POINT_PG0 SETC SPLK SPLK CLRC CLRC CLRC POINT_B0 SPLK #04h, GPR0 GPR0, WSGR ;Set wait states XMIF IN#0h, #0FFh, ;Disable interrupts ;Mask Ints ;Clear Flags ;Clear Sign Extension Mode ;Reset Overflow Mode ;Configure Block Data memory.
Understanding Controller TMS320C24x Controller
POINT_PF1 SPLK #40C0h,SCSR ;CLKOUT=CPUCLK
;Comment active SPLK KICK_DOG #006Fh, WDCR ;Disable VCCP=5V
Activate drive configure pins
LDPK SPLK SPLK SPLK SPLK
#225 #0H,OCRA #00e0H,OCRB #2020h, PCDATDIR #1000h,PDDATDIR IOPC5 high IOPD4
POINT_PF1 Initialization
#DP_CAN
SPLK mask SPLK SPLK
#1001111111111110b,CANLAM0H #1111111111111111b,CANLAM0L #03f7fh,CANIMR
local acceptance 1:don't care interrupt mask
SPLK ;bit
#0000000000000000b,CANMDER |||||||||||||||| FEDCBA9876543210 disable each mailbox
SPLK
#0000000100000000b,CANMCR ||||||||||||||||
Understanding Controller TMS320C24x Controller
;bit
FEDCBA9876543210 CDR: Change data field request
#DP_CAN2
SPLK ;bit 0-15
#1111111111111111b,CANMSGID0H |||||||||||||||| FEDCBA9876543210 lower part extended identifier
SPLK ;bit 0-12 ;bit ;bit ;bit
#1111111111111011b,CANMSGID0L |||||||||||||||| FEDCBA9876543210 upper bits extended identifier Auto answer mode Acceptance mask enable Identifier extension
SPLK ;bit
#DP_CAN #0000000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 CDR: Change data field request
SPLK ;bit
#0000000000000001b,CANMDER |||||||||||||||| FEDCBA9876543210 enable mailbox
SPLK ;bit
#0011000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 Change configuration request
W_CCE
CANGSR,#0Bh
Wait Change config Enable
Understanding Controller TMS320C24x Controller
BCND
W_CCE,NTC
SPLK 8-15
#DP_CAN #0000000000000000b,CANBCR2 |||||||||||||||| FEDCBA9876543210 Baud rate prescaler Reserved
SPLK
#0000010101010111b,CANBCR1 |||||||||||||||| FEDCBA9876543210
TSEG1 TSEG2 Sample point setting times, once) Synchronization jump width Synchronization falling edge Reserved
SPLK ;bit W_NCCE
#0010000000000000b,CANMCR |||||||||||||||| FEDCBA9876543210 Change configuration request
BCND
CANGSR,#0Bh W_NCCE,TC
Wait Change configuration disable
Initialize Counter, Step parameters, pointers ;-SV_PWM: POINT_B0 SPLK SPLK #STABLE, S_TABLE ;Used only save cycle
#VF_SLOPE, vf_slope ;Used later multiply.
LACC
;Start deg.
Understanding Controller TMS320C24x Controller
SACL
ALPHA
;Clear ANGLE integrator
LACC SACL
ENTRY_NEW
;Start deg. ;Clear Sine Table Pointer
LACC SACL
SECTOR_PTR
;Start sector ;Init Sector table index pointer
LACC
#1040
;Use 41.6 period (1040 40nS) ;i.e. 24.039
SACL
;Init period
LACC SACL SACL
#0512 FREQ_SETPT FREQ_TRGT
;Use ~30Hz Frequency ;Init angular speed ;same speed Target value
AR1, #CMPR1 AR2, #CMPR2 AR3, #CMPR3
;Init Timer Comp pointers
;-;EV Config starts here. ;-EV_CONFIG: ;Configure pins function pins POINT_PF2 SPLK SPLK EV_LP SPLK POINT_B0 SPLK CALL POINT_PF2 SPLK #00000h,PBDATDIR ;Configure Port #500, mSEC mS_DELAY ;Wait approx #0C0Ch,PADATDIR ;A3,A2=O/P, A1,A0=I/P, A3,A2=1,1 #0FFFFh,OCRA #0h,OCRB
Understanding Controller TMS320C24x Controller
Mask interrupts (prevent stray PDPINTs from disabling compare outputs) POINT_EV SPLK SPLK SPLK #00000h,EVIMRA #00000h,EVIMRB #00000h,EVIMRC Registers Mask Group interrupt flags Mask Group interrupt flags Mask Group interrupt flags
Clear control registers SPLK SPLK SPLK SPLK SPLK SPLK #00000h,T1CON #00000h,T2CON #00000h,DBTCON #00000h,COMCON #00000h,CAPCON #000FFh,CAPFIFO Timer control Timer control Dead band control register Compare control Capture control Capture FIFO status bits
Clear interrupts before operation starts ;-SPLK SPLK SPLK #0FFFFh,EVIFRA #0FFFFh,EVIFRB #0FFFFh,EVIFRC Clear Group interrupt flags Clear Group interrupt flags Clear Group interrupt flags
Setup Timers Initialize counter registers SPLK SPLK #00000h,T1CNT #00000h,T2CNT Timer counter Timer counter
Initialize period registers POINT_B0 LACC POINT_EV SACL SPLK T1PR #07FFFh, T2PR Timer period Limit counter values only
Initialize compare registers
Understanding Controller TMS320C24x Controller
SPLK SPLK
#00100,T1CMPR #00250,T2CMPR
Timer comp value Timer Comp Value
Configure Timer registers ;-SPLK #0000000001101010b,GPTCON ||||!!!!||||!!!! 5432109876543210
SPLK SPLK
5432109876543210 ||||!!!!||||!!!! #1001010101000010b,T2CON #1001000001000000b,T1CON ;Cont /32, ;Asym
Configure Full Compare registers ;-POINT_EV SPLK SPLK SPLK #00100,CMPR1 #00250,CMPR2 #00400,CMPR3 Comp compare value Comp compare value Comp compare value
;Start "Ball rolling" with Timers Compare units.
POINT_EV SPLK SPLK SPLK SPLK #0000111111101000b,DBTCON #0000011001100110b,ACTR #0010001000000000b,COMCON #1010001000000000b,COMCON ||||!!!!||||!!!! 5432109876543210 Full Action Cntl Compare Cntl Compare Cntl
Enable appropriate Interrupts core ;-POINT_EV SPLK #0000001000000000b,EVIMRA Enable Underflow
Understanding Controller TMS320C24x Controller
||||!!!!||||!!!! 5432109876543210
SPLK SPLK SPLK
#0FFFFh,EVIFRA #0FFFFh,EVIFRB #0FFFFh,EVIFRC
Clear Group interrupt flags Clear Group interrupt flags Clear Group interrupt flags
POINT_PG0 SPLK #0000000000000010b,IMR ||||!!!!||||!!!! 5432109876543210 Enable core Int.
SPLK CLRC
#0FFFFh, IN
Clear pending Ints Enable global Ints
;Init Capture AR4, #CAP1FIFO AR5, #BC_BUF_STRT Point Capture FIFO Point start buffer
MAIN
MAIN
Routine Name: Description: Load Timer compare regs with previously calculated Calculate Angle (alpha) Deduce Determine current Sector Pointer Calculated Branch Sector Subroutine Routine Type:
Last Update:
PWM_ISR:
POINT_EV SPLK #0FFFFh,EVIFRA Clear Group interrupt flags
Understanding Controller TMS320C24x Controller
Calculate Speed Setpoint POINT_B0 SACL SPEED_sp FREQ_SETPT SPEED_sp FREQ_SETPT
LACC SACL
FREQ_SETPT STEP_ANGLE
Load FREQ_SETPT Update angle increment
Calculate Voltage based Volts/Freq. profile PROFILE1 LACC BCND LACC SACL FREQ_SETPT PROFILE2, #Vmin NEW_ALPHA Freq.<=F1
PROFILE2
LACC BCND
FREQ_SETPT PROFILE3,
LACC SACL SACH LACC SACL
FREQ_SETPT,4 GPR0 GPR0 vf_slope
;Convert format
vf_slope
#INTERCEPT NEW_ALPHA
;convert result format
INTERCEPT ;result <1.0
PROFILE3
LACC SACL
#Vmax
Understanding Controller TMS320C24x Controller
Calculate angle ALPHA NEW_ALPHA LACC SACL LACC SACL LACC SACH LACC TBLR ENTRY_NEW ENTRY_OLD ALPHA STEP_ANGLE ALPHA ALPHA,8 ENTRY_NEW S_TABLE ENTRY_NEW ;dy=Sin(ALPHA) ;Inc angle.
SACH
dy,1 ;shift restore format
LACC resolution SACH LACC TBLR
dy,11 #0FFh ENTRY_NEW S_TABLE
;scale integer ;Save format ;ACC=60
;dx=Sin(60-ALPHA)
SACH
dx,1 ;shift restore format
LACC resolution SACH
dx,11
;scale integer ;Save format
;Determine which Sector LACC BCND Sector ENTRY_NEW ENTRY_OLD BRNCH_SR, negative need change
Understanding Controller TMS320C24x Controller
positive continue MODIFY_SEC_PTR LACC BCND Sector (S1) LACC >Sn+1) SACL PISR1 SPLK #01h SECTOR_PTR BRNCH_SR #00, SECTOR_PTR ;Reset Sector pointer ;i.e. SECTOR_PTR SECTOR_PTR select next Sector (SnSECTOR_PTR #05h PISR1,EQ ;Check last sector (S6) yes, re-init AR1=
BRNCH_SR: LACC TBLR LACC BACC #SECTOR_TBL SECTOR_PTR SR_ADDR SR_ADDR
;-;Sector calculations a,b,c a,b,c ;-SECTOR_SR1: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dx+Ta
LACC SACL
LOAD_COMPARES
;ACC ;ACC T-Ta ;ACC T-Ta
Understanding Controller TMS320C24x Controller
;Sector calculations a,b,c b,a,c
;-SECTOR_SR2: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dy+Tb
LACC SACL
LOAD_COMPARES
;ACC ;ACC T-Tb ;ACC T-Tb
;-;Sector calculations a,b,c c,a,b ;-SECTOR_SR3: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dx+Tc
LACC SACL
LOAD_COMPARES
;ACC ;ACC T-Tc ;ACC T-Tc
;-;Sector calculations a,b,c c,b,a
Understanding Controller TMS320C24x Controller
;-SECTOR_SR4: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dx+Ta
LACC SACL
LOAD_COMPARES
;ACC ;ACC T-Tc ;ACC T-Tc
;-;Sector calculations a,b,c b,c,a ;-SECTOR_SR5: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dx+Ta
LACC SACL
LOAD_COMPARES
;ACC ;ACC T-Tb ;ACC T-Tb
;-;Sector calculations a,b,c a,c,b
Understanding Controller TMS320C24x Controller
SECTOR_SR6: LACC SACL ;Acc ;Acc T-dx ;Acc T-dx-dy ;Acc 1/2(T-dx-dy)
SACL
;Acc dx+Ta
LACC SACL
;ACC ;ACC T-Ta ;ACC T-Ta
;Transfer Compare values this period LOAD_COMPARES POINT_B0 LACC SACL LACC SACL LACC SACL *,0,AR2 *,0,AR3 *,0,AR1 ;Load Compare4 Register with ;Load Compare3 Register with ;Load Compare2 Register with
Receive Frequency target from bus.
CAN_RD W_FLAG
BCND
#DP_CAN CANIFR,7 CAN_RD_END,NTC wait mailbox interrupt flag
W_RA
BCND SPLK
CANRCR,11 CAN_RD_END,NTC #0010h,CANRCR
Wait receive acknowledge
reset CANIFR
#DP_CAN2
Understanding Controller TMS320C24x Controller
LACL POINT_B0 BCND LACL POINT_B0 SACL
CANMBX0A
Load data Accu
FREQ_TRGT CAN_RD_END,EQ #DP_CAN2 CANMBX0A Freq_trgt updated value doesn't change
FREQ_TRGT
Change Freq_trg
CAN_RD_END:
;Adjust frequency demand from debugger FREQ_DMD: POINT_B0 LACC BCND FREQ_TRGT FREQ_SETPT FD_END,
LACC SACL BCND
RMP_DLY_CNT RMP_DLY_CNT #RMP_DLY_MAX FD_END2,
CHNG_FREQ: LACC BCND FREQ_TRGT FREQ_SETPT INC_FREQ,
DEC_FREQ
LACC SACL BCND SPLK
FREQ_SETPT FREQ_SETPT FD_END, FREQ_SETPT FD_END
Understanding Controller TMS320C24x Controller
INC_FREQ
LACC SACL BCND SPLK
FREQ_SETPT FREQ_SETPT #2047 FD_END,
then Frequency
#2047, FREQ_SETPT
FD_END: SPLK RMP_DLY_CNT
CLRC
IN
;-;Sector routine jump table used with BACC inst. ;-SECTOR_TBL: .word SECTOR_SR1 .word SECTOR_SR2 .word SECTOR_SR3 .word SECTOR_SR4 .word SECTOR_SR5 .word SECTOR_SR6
Routine Name: Description: Produces multiple delays using instruction. Originator: David Figoli Delay produced based value loaded mSEC. i.e. Delay mSEC (1mS version) Routine Type:
Last Update:
Understanding Controller TMS320C24x Controller
mS_DELAY: POINT_B0 LACC SACL LACC mS_LP BCND mS_LP,GT GPR0 ;25,000 cycles 25MHz cycle cycle cycles #25000 GPR0 mSEC
cycles ;-;LED display table used indicate speed setting ;-LED_TABLE: .word 00080h .word 00040h .word 00020h .word 00010h .word 00008h .word 00004h .word 00002h .word 00001h .word 00001h
;-;No. Samples Angle Range
STABLE SINVAL .word .word .word .word .word .word .word .word .word 134; 268; 402; 536; 670; 804; 938; 1072 Index 0.00 0.00 0.01 0.01 0.02 0.02 0.02 0.03 0.03 Angle Sin(Angle)
0.23 0.47 0.70 0.94 1.17 1.41 1.64
1.88
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
1206 1340 1474 1608 1742 1876 2009 2143 2277 2411 2544 2678 2811 2945 3078 3212 3345 3479 3612 3745 3878 4011 4144 4277 4410 4543 4675 4808 4941 5073 5205 5338 5470 5602 5734 5866 5998
2.11
0.04 0.04 0.04 0.05 0.05 0.06 0.06 0.07 0.07 0.07 0.08 0.08 0.09 0.09 0.09 0.10 0.10 0.11 0.11 0.11 0.12 0.12 0.13 0.13 0.13 0.14 0.14 0.15 0.15 0.15 0.16 0.16 0.17 0.17
2.34 2.58 2.81 3.05 3.28 3.52 3.75 3.98 4.22 4.45 4.69 4.92 5.16 5.39 5.63 5.86 6.09 6.33 6.56 6.80 7.03 7.27 7.50 7.73 7.97 8.20 8.44 8.67 8.91 9.14 9.38 9.61 9.84
10.08 0.17 10.31 0.18 10.55 0.18
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
6130 6261 6393 6524 6655 6787 6918 7049 7180 7310 7441 7571 7702 7832 7962 8092 8222 8351 8481 8610 8740 8869 8998 9127 9255 9384 9512 9640 9768 9896
10.78 0.19 11.02 0.19 11.25 0.20 11.48 0.20 11.72 0.20 11.95 0.21 12.19 0.21 12.42 0.22 12.66 0.22 12.89 0.22 13.13 0.23 13.36 0.23 13.59 0.24 13.83 0.24 14.06 0.24 14.30 0.25 14.53 0.25 14.77 0.25 15.00 0.26 15.23 0.26 15.47 0.27 15.70 0.27 15.94 0.27 16.17 0.28 16.41 0.28 16.64 0.29 16.88 0.29 17.11 0.29 17.34 0.30 17.58 0.30 17.81 0.31 18.05 0.31 18.28 0.31 18.52 0.32 18.75 0.32 18.98 0.33 19.22 0.33
10024 10151 10279 10406 10533 10660 10786
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
10913 11039 11165 11291 11417 11543 11668 11793 11918 12043 12167 12292 12416 12540 12664 12787 12910 13033 13156 13279 13401 13524 13646 13767 13889 14010 14131 14252 14373 14493 14613 14733 14852 14972 15091 15210 15328
19.45 0.33 19.69 0.34 19.92 0.34 20.16 0.34 20.39 0.35 20.63 0.35 20.86 0.36 21.09 0.36 21.33 0.36 21.56 0.37 21.80 0.37 22.03 0.38 22.27 0.38 22.50 0.38 22.73 0.39 22.97 0.39 23.20 0.39 10023.44 0.40 10123.67 0.40 10223.91 0.41 10324.14 0.41 10424.38 0.41 10524.61 0.42 10624.84 0.42 10725.08 0.42 10825.31 0.43 10925.55 0.43 11025.78 0.43 11126.02 0.44 11226.25 0.44 11326.48 0.45 11426.72 0.45 11526.95 0.45 11627.19 0.46 11727.42 0.46 11827.66 0.46 11927.89 0.47
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
15447 15565 15683 15800 15917 16035 16151 16268 16384 16500 16616 16731 16846 16961 17075 17190 17304 17417 17531 17644 17757 17869 17981 18093 18205 18316 18427 18538 18648 18758 18868 18978 19087 19195 19304 19412 19520
12028.13 0.47 12128.36 0.48 12228.59 0.48 12328.83 0.48 12429.06 0.49 12529.30 0.49 12629.53 0.49 12729.77 0.50 12830.00 0.50 12930.23 0.50 13030.47 0.51 13130.70 0.51 13230.94 0.51 13331.17 0.52 13431.41 0.52 13531.64 0.52 13631.88 0.53 13732.11 0.53 13832.34 0.53 13932.58 0.54 14032.81 0.54 14133.05 0.55 14233.28 0.55 14333.52 0.55 14433.75 0.56 14533.98 0.56 14634.22 0.56 14734.45 0.57 14834.69 0.57 14934.92 0.57 15035.16 0.58 15135.39 0.58 15235.63 0.58 15335.86 0.59 15436.09 0.59 15536.33 0.59 15636.56 0.60
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
19627 19735 19841 19948 20054 20160 20265 20371 20475 20580 20684 20788 20891 20994 21097 21199 21301 21403 21504 21605 21706 21806 21906 22006 22105 22204 22302 22400 22498 22595 22692 22788 22884 22980 23075 23170 23265
15736.80 0.60 15837.03 0.60 15937.27 0.61 16037.50 0.61 16137.73 0.61 16237.97 0.62 16338.20 0.62 16438.44 0.62 16538.67 0.62 16638.91 0.63 16739.14 0.63 16839.38 0.63 16939.61 0.64 17039.84 0.64 17140.08 0.64 17240.31 0.65 17340.55 0.65 17440.78 0.65 17541.02 0.66 17641.25 0.66 17741.48 0.66 17841.72 0.67 17941.95 0.67 18042.19 0.67 18142.42 0.67 18242.66 0.68 18342.89 0.68 18443.13 0.68 18543.36 0.69 18643.59 0.69 18743.83 0.69 18844.06 0.70 18944.30 0.70 19044.53 0.70 19144.77 0.70 19245.00 0.71 19345.23 0.71
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
23359 23453 23546 23640 23732 23824 23916 24008 24099 24189 24279 24369 24459 24548 24636 24724 24812 24900 24986 25073 25159 25245 25330 25415 25499 25583 25667 25750 25833 25915 25997 26078 26159 26239 26320 26399 26478
19445.47 0.71 19545.70 0.72 19645.94 0.72 19746.17 0.72 19846.41 0.72 19946.64 0.73 20046.88 0.73 20147.11 0.73 20247.34 0.74 20347.58 0.74 20447.81 0.74 20548.05 0.74 20648.28 0.75 20748.52 0.75 20848.75 0.75 20948.98 0.75 21049.22 0.76 21149.45 0.76 21249.69 0.76 21349.92 0.77 21450.16 0.77 21550.39 0.77 21650.63 0.77 21750.86 0.78 21851.09 0.78 21951.33 0.78 22051.56 0.78 22151.80 0.79 22252.03 0.79 22352.27 0.79 22452.50 0.79 22552.73 0.80 22652.97 0.80 22753.20 0.80 22853.44 0.80 22953.67 0.81 23053.91 0.81
Understanding Controller TMS320C24x Controller
.word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word
26557 26635 26713 26791 26868 26944 27020 27096 27171 27246 27320 27394 27467 27540 27612 27684 27756 27827 27897 27967 28037 28106 28175 28243 28311
23154.14 0.81 23254.38 0.81 23354.61 0.82 23454.84 0.82 23555.08 0.82 23655.31 0.82 23755.55 0.82 23855.78 0.83 23956.02 0.83 24056.25 0.83 24156.48 0.83 24256.72 0.84 24356.95 0.84 24457.19 0.84 24557.42 0.84 24657.66 0.84 24757.89 0.85 24858.13 0.85 24958.36 0.85 25058.59 0.85 25158.83 0.86 25259.06 0.86 25359.30 0.86 25459.53 0.86 25559.77 0.86
Description: Modifies: Last Update: 16-06-95 Dummy ISR, used trap spurious interrupts. PHANTOM
PHANTOM PHANTOM
Understanding Controller TMS320C24x Controller
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Understanding Controller TMS320C24x Controller
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Understanding Controller TMS320C24x Controller

Claire Monnet Digital Signal Processor Solutions Abstract Te

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