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Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
Claire Monnet Digital Signal Processing Solutions
Abstract
Texas Instruments TMS320F241, TMS320F243, TMS320C242 devices contain many on-chip peripherals, each them capable generating multiple interrupts response various events. C2xLP core support non-maskable interrupt maskable interrupt requests. does handle directly peripheral interrupt requests. That centralized interrupt controller needed arbitrate them. TMS320F241, TMS320F243, TMS320C242 devices, this controller called Peripheral Interrupt Expansion (PIE). This document explains general organization PIE. Interrupt Service Routine (ISR) programming example also provided.
Contents
Design Problem Solution Appendix Peripheral Interrupt Request Registers Peripheral Interrupt Acknowledge Registers
Figures
Figure Figure Peripheral Interrupt Expansion Block Diagram Interrupt Request Example
Digital Signal Processing Solutions
December 1998
Design Problem
TMS320F241, TMS320F243, TMS320C242 devices contain many on-chip peripherals, each them capable generating multiple interrupts response various events. C2xLP core support non-maskable interrupt maskable interrupt requests. does handle directly peripheral interrupt requests. That centralized interrupt controller needed arbitrate them. TMS320F241, TMS320F243, TMS320C242 devices, this controller called Peripheral Interrupt Expansion (PIE). This document explains general organization PIE. Interrupt Service Routine (ISR) programming example also provided.
Solution
Peripheral Interrupt Expansion Organization
centralized interrupt controller handles peripheral interrupt requests. connected peripherals, CPU, data address buses. contains three registers.
PIRQ PIVR PIACK Peripheral Interrupt Request. Detects records interrupt request from peripherals Peripheral Interrupt Vector Register. Contains interrupt vector most recently acknowledged peripheral interrupt Peripheral Interrupt Acknowledge. Sends Interrupt Acknowledge peripherals
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
Figure Peripheral Interrupt Expansion Block Diagram
From Peripherals
PIRQ Edge Detect
PIRQ
Pulse
INT1 INT2 INT3 INT4 INT5 INT6
Look Table
PIVR
Peripherals
PIACKn Generate PIACK
IACKn Decode
Address
From
RHEA Interface PIRQ, PIACK, PIVR: interrupt registers
Interrupt Priority Level Some peripheral different priority levels interrupt requests. ADC, external interrupts, SCI, configured generate either priority request and/or high priority request controller.
Interrupt Request each peripheral, interrupt flag interrupt enable will cause PIRQ module. This interrupt Request simply reflects status peripheral. request cleared interrupt acknowledge software (that clearing interrupt flag writing flag inside peripheral). unacknowledged interrupt request same priority level previously been sent, pulse generated sent when PIRQ active.
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
Figure Interrupt Request Example
Interrupt Registers Logic
INT6 INT5 INT4 INT3 INT2 INT1
INT6 INT5 INT4 INT3 INT2 INT1
Interrupt Acknowledge
Peripheral Interrupt Extension
Interrupt Controller
PIRQ Registers
Peripheral: External Interrupt Priority
Flag Mask
XINTCR
Priority
interrupt request will corresponding flag interrupt flag register IFR. interrupt been enabled setting appropriate interrupt mask register INbit cleared, will acknowledge interrupt.
Interrupt Acknowledge After accepting interrupt, sends module interrupt acknowledge value Program Address (PAB), which corresponds interrupt priority level being responded decodes this value recognizes which interrupt request been acknowledged. sends peripherals PIACK. This signal will used peripheral clear interrupt flag.
Execute Interrupt Routine When interrupt request acknowledged, controller loads peripheral interrupt vector into Peripheral Interrupt Vector Register from table stored module. Then General Interrupt Service Routine (GISR) saves necessary context reads PIVR. executes appropriate branch Specific Interrupt Routine Service (SISR) using interrupt vector target address.
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
Interrupt Service Routine (ISR) Programming
There noticeable difference between programming X241/2/3 programming X240 device. interrupts:
PART Interrupt Branch
Branch interrupts corresponding INT1 ISR1
PART Main program Disable core interrupt before initialization: SETC INMask non-used core interrupt SPLK INT1 #0000000000000001b, Mask core interrupts except
Reset core interrupt flags SPLK #0000000000111111b,IFR
only peripheral interrupt interrupt level: Mask other peripheral interrupts Unmasked chosen interrupt Clear interrupt flags Enable unmasked core interrupts. CLRC IN
PART Interrupt Service Routine
Label correctly each interrupt Write code Enable core interrupt CLRC INReturn main program.
Example shows programming example using external interrupts (XINT1 XINT2) Timer period interrupt.
Example External Interrupt Timer Period Interrupt
.sect ".vectors"
RSVECT INT1 INT2
START EXTERN_ISR PERIOD_ISR
Reset Vector Branch EXTERN_ISR Branch PERIOD_ISR
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
INT3 INT4 PHANTOM Branch PHANTOM
.text START:
SETC
Disable interrupts Initialization
SPLK SPLK
#0E1h #0FFFFH,OCRA #003FFh,OCRB
data pointer 7080h Configure Shared Pins
;**************** External Interrupt Setting *********************
SPLK 14-3:
#0E0h
data pointer 7000h
#1000000000000001b,XINT1CR Configure External |||||||||||||||| FEDCBA9876543210 Interrupt Flag. Reserved Interrupt generated falling edge High priority Enable interrupt interrupt register
SPLK
#1000000000000001b,XINT2CR Configure External Interrupt register
Enable XINT2, high priority generated falling edge ;******************* Event Manager Setting ***********************
SPLK
#0E8h
Load Event Manager data page
#00080h, EVIMRA Mask group interrupt except Timer period interrupt
SPLK SPLK SPLK
#00000h, EVIMRB Mask group interrupt #00000h, EVIMRC Mask group interrupt #0FFFFh, EVIVRA Clear group interrupt flag
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
SPLK SPLK #0FFFFh, EVIVRB Clear group interrupt flag #0FFFFh, EVIVRC Clear group interrupt flag
SPLK SPLK SPLK
#0000h,T1CNT #1000h,T1PR #0000h,GPTCON
Initialize Timer counter Initialize Timer period Initialize Timer control
;************
Mask/Unmask enable core interrupt ************;
SPLK
#0000000000000011b, Mask interrupt except INT1 INT2
SPLK
#000ffh,IFR
Clear core interrupt flags
CLRC
IN
Enable
core interrupt
;*****************
Start Timer
**********************
SPLK
#0E8h #0001000001000000, T1CON FEDCBA9876543210
Load Event Manager data page
12-11 10-8
continuous-up count mode 000: prescaler Timer enabled Internal clock selected
Interrupt Service Routines
EXTERN_ISR
started external Interrupt
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
LACL BCND #00E0h PIVR #0001h XINT1_ISR,EQ Load peripheral vector address Subtract XINT1 offset from above ACC=0, execute XINT1 SISR
LACL BCND
PIVR #0011h XINT2_ISR,EQ
Load peripheral vector address Subtract XINT2 offset from above ACC=0, execute XINT2 SISR
CLRC
IN
;=========================== XINT1_ISR: LACL SACL #00E0h XINT1CR XINT1CR
XINT1
===========================
;Clear XINT1 flag
CLRC
IN
Enable Core Interrupt Return from
;========================= XINT2_ISR: LACL SACL #00E0h XINT2CR XINT2CR
XINT2
===========================
;Clear XINT2 flag
CLRC
IN
Enable Core Interrupt Return from
PERIOD_ISR
started timer period interrupt
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
CLRC Enable Core Interrupt Return from
PHANTOM
Phantom interrupt
Return from
Appendix Peripheral Interrupt Request Registers Peripheral Interrupt Acknowledge Registers
PIRQR0 PIACKR0:
0.15
0.14
0.13
0.12
0.11
0.10
position
Interrupt
Interrupt Level
Interrupt Description
0.10 0.11 0.12 0.13 0.14 0.15 PDPINT ADCINT XINT1 XINT2 SPIINT RXINT TXINT CANMBINT CANERINT CMP1INT CMP2INT CMP3INT TPINT1 TCINT1 TUFINT1 TOFINT1 Power Device Protection interrupt pin. Interrupt. High priority External Interrupt High priority External Interrupt High priority interrupt. High priority receiver interrupt. High priority transmitter interrupt. High priority mailbox interrupt. High priority error interrupt. High priority Compare interrupt Compare interrupt Compare interrupt Timer period interrupt Timer compare interrupt Timer underflow interrupt Timer overflow interrupt INT1 INT1 INT1 INT1 INT1 INT1 INT1 INT1 INT2 INT2 INT2 INT2 INT2 INT2 INT2
Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
PIRQR1 PIACKR1:
1.14
1.13
1.12
1.11
1.10
position 1.10 1.11 1.12 1.13 1.14
Interrupt TPINT2 TCINT2 TUFINT2 TOFINT2 CAPINT1 CAPINT2 CAPINT3 SPIINT RXINT TXINT CANMBINT CANERINT ADCINT XINT1 XINT2
Interrupt Description Timer period interrupt Timer compare interrupt Timer underflow interrupt Timer overflow interrupt Capture interrupt Capture interrupt Capture interrupt interrupt. priority receiver interrupt. priority transmitter interrupt. priority mailbox interrupt. priority error interrupt. priority Interrupt. priority External Interrupt priority External Interrupt priority
Interrupt Level INT3 INT3 INT3 INT3 INT4 INT4 INT4 INT5 INT5 INT5 INT5 INT5 INT6 INT6 INT6
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Handling Different Interrupts TMS320F241, TMS320F243, TMS320C242 DSPs
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