Iain Hunter Digital Signal Processing Solutions Abstract Tex

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Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
Iain Hunter Digital Signal Processing Solutions
Abstract
Texas Instruments (TITM) TMS320F240 digital signal processor (DSP) controller contains hardware deadband unit that automatically generates deadband (pulse width modulation) signals from full compare unit. This document describes other available signals drive second three-phase inverter with deadband.
Contents
Design Problem Solution Corresponding Code
Figures
Figure Outputs Used Drive Three-Phase Inverters.2 Figure with Deadband
Digital Signal Processing Solutions
January 1998
Design Problem
TMS320F240 controller contains hardware deadband unit that automatically generates deadband signals from full compare unit. other available signals drive second three-phase inverter with deadband?
Solution
shadow registers interrupts available event manager make possible software generate deadband with minimal overhead. deadband time delay between switching power driver/transistor phase inverter switching complementary driver This ensures that delay switching device does lead shoot-through short circuit that damage circuit when partner switched Inverter connected full compare unit (pulse-width modulation) outputs, PWM1-6. Inverter uses remaining signals. simple compare outputs, PWM7-9, connected high-side drivers individual compare outputs TxPWM connected low-side drivers, shown Figure
Figure Outputs Used Drive Three-Phase Inverters
Inverter
PWM1 PWM2 PWM3 PWM4 PWM5 PWM6
F240
PWM7 T1PWM PWM8 T2PWM PWM9 T3PWM
Inverter
Configuring F240 generate software deadband second inverter places following limitations system design:
Both inverters must have same period, three timers synchronized. possible inputs because timers generation. Therefore, speed feedback from motors must input capture units.
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
second inverter without deadband implemented using simple compare unit complementing three outputs, PWM7/8/9, give !PWM7/8/9 well. deadband included using three independent outputs (TxPWM) give complemented outputs. simple compare outputs configured active high TxPWMs configured active low. Since have control over each drivers' turn-on turn-off times, easy software delay turning driver changing compare register value. Figure illustrates principle deadband pair complemented signals (phaseA, !phaseA) inverter. period with symmetric PWM, compare value deadband Figure shows following relationships used generate software deadband.
first relationship that when driver turned expected time, given compare value, associated turn delayed deadband. illustrate this, Phase switches !Phase switches expected, given compare value. However, Phase switches rather than !Phase switches rather than second relationship that during up-count phase timer, delaying Phase switch turn corresponds increase compare value 30). Conversely, during down count, delaying !Phase switch turn corresponds reduction compare value 10).
Figure with Deadband
Timer Count
(ms) Prd. 60ms Compare 20ms Deadband 10ms
Phase (SCMPRx, Active High) Phase (TxPWM, Active Low) Deadband Deadband
software deadband implementation second inverter makes these relationships following hardware features F240:
Each signals compare register, allowing each signal independently controlled. shadow registers each compare units allow compare registers updated exactly right time with synchronization problems. They updated start both down counts (count count PRD, respectively). separate timer underflow (count timer period (count PRD) interrupts used calculate compare values loaded next loading time. underflow interrupt used calculate compare values (Phase !Phase where desired compare value deadband,
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
which will loaded count down count. Similarly, period interrupt used calculate compare values next count (Phase !Phase control both three-phase inverters, event manager F240 must configured follows:
three timers configured identically continuous up/down mode with internal clock, with timers timer period start bit. compare output pins enabled, with PWM1/3/5/7/8/9 active high PWM2/4/6/TxPWM active low. full compare unit shadow reload count only. simple compare individual timer compares both count count period. hardware deadband unit full compare unit. Since three timers identical, underflow period interrupts taken from different timers allow separate interrupt vectors. This eliminates additional interrupt latency involved with secondary vector table. underflow interrupt taken from timer INT2. period interrupt taken from timer INT3. allow PDPINT (power protection interrupt) additional, occasional, source INT2, simple test interrupt vector (EVIVRA) used interrupt service routine (ISR) rather than secondary vector table.
following code example assumes that both inverters controlled control loop called every periods. actual control function control() generates compare values inverters. Inverter compare values inv1a/b/c inverter inv2a/b/c. code consists main routine with callable assembly language functions ISRs.
Corresponding Code
#include <stdlib.h> #include "c240_C.h" This based version c240.h defining pointers F240 registers Declare variables defined assembly routines used extern int_cnt; Prototype functions defined assembly used extern void dis_watchdog(void); extern void init_ev(void); Prototype functions defined this file void main(void); void main(void) This main routine which sets variables then enters infinite loop, with system functions being entirely interrupt driven.
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
void main(void) {int i=0; F240 Peripherals dis_watchdog(); Disable watchdog init_ev(); Initialise Event Manager system variables, both assembly int_cnt=0; Initialise counter asm(" clrc INTM"); Enable Interrupts for(;;); Loop This file contains functions which used C240 Event Manager ADCs. functions called either assembly functions because they declared void function(void) parameters passed. _dis_watchdog This function disables watchdog timer Vccp=+5V* _init_ev This function initialises Event Manager .include c240.h Declare functions global allow code call them. leading underscore allows functions variables referenced same name (without underscore) However they referenced from assembly code underscore required .def _dis_watchdog .def _init_ev Define constant Period. this case have down counting, 100ns 50us Define software DEADBAND 500ns, equal cycles PWM_PERIOD .equ Period *50ns 12.8us DEADBAND .equ .def PWM_PERIOD .def DEADBAND .text Start program code void dis_watchdog(void) Function disable watchdog timer _dis_watchdog: Disable watchdog #0E0h Change Event Manager, 07400h splk #006Fh, WD_CNTL Disable Watchdog (WD) Vccp=+5V splk #05555h, WD_KEY Write then Watchdog register splk #0AAAAh, WD_KEY clear counter
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
void init_ev(void) Function initialise Event Manager invertors GPTimer Full Timer 2&3, identical Timer with Simple Compare Individual compares enabled. Enable Timer 1==0 int. INT2 Timer 2==PRD INT3 other pins _init_ev: SYSCLK with 10MHz External #CKCR1/128 splk #00000010b,CKCR0 disabled, CLKIN/2 LPM0 ACLK enabled SYSCLK 5MHz splk #10110001b,CKCR1 10MHz ACLK divide ratio splk #10000011b,CKCR0 enabled LPM0 ACLK enabled SYSCLK 10MHz CLKOUT SYSCLK splk #40C0h,SYSCR Clear reset variables lacc SYSSR #0FFh sacl SYSSR zero wait states external memory lacc #0008h sacl *,WSGR ;Set INT2and INT3 clear Flags lacc #0FFh sacl Clear core Flags lacc #06h core INT2/3. sacl Configure IO\function MUXing pins #OPCRA/128 splk #3F00h,OPCRA Ports Port B0-5 splk #00F1h,OPCRB Port function Note that XF/BIO~ require select non-IO function Clear Event Manager Event Manager regs #DP_EV
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
splk #07FFh,IFRA splk #00FFh,IFRB splk #000Fh,IFRC Enable Period PDPINT INT2 (Group splk #081h,IMRA Enable Underflow (Group splk #0004h,IMRB Disable (Group interrupts splk #0000h,IMRC Initialise CAPFIFO clearing upper word splk #0FFh,CAPFIFO Initialise Full Unit based Timer Invertor splk #55h,GPTCON Enable TxCMP, active splk #05E8h,DBTCON; 500ns deadband Full Compare Unit Prescaler Enable timers splk #666h,ACTR Bits 15-12 used, space vector compare actions PWM6/PWM5 Active Low/Active High PWM4/PWM3 Active Low/Active High PWM2/PWM1 Active Low/Active High splk #02Ah,SACTR SCMPx active high splk #32Fh,COMCON; FIRST enable operation Reload Full Compare when T1CNT=0 Disable Space Vector Reload Full Compare ACTR, T1CNT=0 Enable Full Simple Compare Outputs Simple Compare time base Timer Reload Simple Compare, when ;T1CNT=0 Reload Simple Compare Action when ;T1CNT=0 Full Compare Mode splk #832Fh,COMCON; THEN enable Compare operation Timer splk #PWM_PERIOD,T1PER period splk #0,T1CNT splk #02806h,T1CON Ignore Emulation suspend Cont Up/Down Mode prescalar TENABLE Disable Timer,enable later Internal Clock Source Reload Compare Register when T1CNT=0 Enable Timer Compare operation period
Dead Band Timer
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
Timer identically Timer splk #0h,T2CNT splk #02887h,T2CON Ignore Emulation suspend Cont Up/Down Mode prescalar ENABLE Disable Timer,enable later Internal Clock Source Reload Compare Register when ;T1CNT=0 Enable Timer Compare operation Period Timer identically Timer splk #0,T3CNT splk #0A887h,T3CON; Ignore Emulation suspend Cont Up/Down Mode prescalar ENABLE Disable Timer,enable later Internal Clock Source Reload Compare Register when T1CNT=0 Enable Timer Compare operation Period Enable/Start Timer (and thus timers well) lacc T1CON #40h enable timer sacl T1CON .end This file contains assembly Interrupt Service Routines, with context* saving required assembly ISRs called environment and/or while debugger being used. functions are: _c_int2 Group Event Manager ISR, here only Period happens PDPINT. _c_int3 Group Event Manager ISR, here only Underflow _PHANTOM trap spurious other INTs .include c240.h Declare this files functions global .def _c_int2 .def _c_int3 .def _PHANTOM Declare externally defined functions/constants global .ref PWM_PERIOD .ref DEADBAND
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
Declare callable variable count number calls .bss _int_cnt,1 .def _int_cnt .bss .bss .bss .bss .bss .bss .def .def .def .def .def .def _inv1a,1 locations write desired Invertor _inv1b,1 PWMs _inv1c,1 _inv2a,1 locations write desired Invertor _inv2b,1 PWMs _inv2c,1 _inv1a _inv1b _inv1c _inv2a _inv2b _inv2c
.text c_int2: interrupt handler Every period interrupt int_cnt incremented. Full Compare Units updated Invertor load CNT=0. TxCMP/SCMPRx units have DEADBAND applied drive Invertor load CNT=0 PDPINT occurs then caught dealt with _c_int2: Carry generic context saving called C/debugger environment *,AR1 Ensure ARP=AR1 ARB=previous Increment stack safety #1,*+ Save status registers onto stack #0,*+ popd hardware stack push onto stack AR0,*+ Save AR1,* onto stack AR0,*+ Carry specific context saves this sach save sacl save Handle Interrupt Flags INT2 flag automatically cleared hardware when taken. However specific Event Manager IFRA flag needs cleared. This done reading appropriate Peripheral Vector Address Register #DP_EV LACC IVRA load interrupt this resets IFRA flag automatically normal operation only T1PRD will occur, although need check PDPINT deal with
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
sub#020h bcnd _pdpint,EQ start actual code T1PRD Increment counter #_int_cnt LACC _int_cnt SACL _int_cnt this Interrupt update compare values Invertors take effect CNT=0. #DP_EV AR3,#_inv1a *,AR3 lacc sacl CMPR1 Update Full Compare Unit lacc sacl CMPR2 lacc sacl CMPR3 Invertor need software deadband. Minimum deadband must ensured control() less than ;(PWM_PERIOD-DEADBAND) lacc sacl T1CMP _inv2a T1CMPR #DEADBAND sacl SCMPR1 _inv2a+DEADBAND SCMPR1 lacc sacl T2CMP _inv2b T2CMPR #DEADBAND sacl SCMPR2 _inv2b+DEADBAND SCMPR2 lacc sacl T3CMP _inv2c T3CMPR #DEADBAND sacl SCMPR3 _inv2c+DEADBAND SCMPR3 Restore specific context saves *,AR1 *lacl load load sbrk Restore generic context save AR0,*- Restore pshd *lst #0,*lst #1,*clrc INT2 non-interruptible
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
c_int3: interrupt handler Every underflow interrupt int_cnt incremented. TxCMP/ SCMPRx units have DEADBAND applied drive Invertor load CNT=PRD main Controller routine called every cycles _c_int3: Carry generic context saving called C/debugger environment *,AR1 Ensure ARP=AR1 that ARB=previous Increment stack safety #1,*+ Save status registers onto stack #0,*+ popd hardware stack push onto stack AR0,*+ Save AR1,* onto stack AR0,*+ Carry specific context saves this sach save sacl save Handle Interrupt Flags INT3 flag automatically cleared hardware when taken. However specific Event Manager IFRB flag needs cleared. This done reading appropriate ;Peripheral Vector Address Register #DP_EV LACC IVRB load interrupt this resets IFRA flag automatically Since INT3 contains control routine which take several periods needs interruptible both itself ;INT3 keep track ints. clrc normal operation only T2UFINT will occur Increment counter #_int_cnt LACC _int_cnt SACL _int_cnt
this symmetric cycle (int_cnt=10) then call control() bcnd not_control,LT Reset _int_cnt call control routine splk #0,_int_cnt Here call main control routine that will update _inv1a -_inv2c essential that control routine prevents case _inv2x being less than DEADBAND greater than PWMPERIOD-
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
;DEADBAND. Call _control not_control: #DP_EV AR3,#_inv2a *,AR3 Here only update Invertor values loaded Invertor need software deadband. Minimum deadband must ensured control routine _inv2x>DEADBAND lacc sacl SCMPR1 _inv2a SCMPR1 sub#DEADBAND sacl T1CMP _inv2a-DEADBAND T1CMPR lacc sacl SCMPR2 _inv2b SCMPR2 sub#DEADBAND sacl T2CMP _inv2b-DEADBAND T2CMPR lacc sacl SCMPR3 _inv2c SCMPR3 sub#DEADBAND sacl T3CMP _inv2c-DEADBAND T3CMPR Restore specific context saves *,AR1 *lacl load load sbrk Restore generic context save AR0,*- Restore pshd *lst #0,*lst #1,*ret Dummy catch spurious interrupts _PHANTOM _PHANTOM Dummy routine catch PDPINT _pdpint _pdpint Dummy control routine compare values _control: #_inv1a splk #10,_inv1a
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
splk splk splk splk splk .end
#20,_inv1b #30,_inv1c #10,_inv2a #20,_inv2b #30,_inv2c
This file contains complete interrupt vector table C240 with possible vectors identified. Define ISRs declared elsewhere global allow this file "see" them .ref_c_int0 .ref_c_int2 .ref_c_int3 .ref_PHANTOM Define interrupt vector table separate section called ".intvecs" this makes easier linker place correct program memory between .sect ".intvecs" RSVECT _c_int0 INT1 _PHANTOM INT2 _c_int2 INT3 _c_int3 INT4 _PHANTOM INT5 _PHANTOM INT6 _PHANTOM RESERVED _PHANTOM SW_INT8 _PHANTOM SW_INT9 _PHANTOM SW_INT10 _PHANTOM SW_INT11 _PHANTOM SW_INT12 _PHANTOM SW_INT13 _PHANTOM SW_INT14 _PHANTOM SW_INT15 _PHANTOM SW_INT16 _PHANTOM TRAP _PHANTOM _PHANTOM EMU_TRAP _PHANTOM SW_INT20 _PHANTOM SW_INT21 _PHANTOM SW_INT22 _PHANTOM SW_INT23 _PHANTOM .end Reset Vector (Analysis Int) User User User User User User User User User Trap vector maskable Emulator Trap User User User User
Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
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Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller
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Driving Three-Phase Inverters with Deadband Using TMS320F240 Controller

Iain Hunter Digital Signal Processing Solutions Abstract Tex

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