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TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Shaku Anjanaiah Digital Signal Processing Solutions
This document describes multi-channel buffered serial port (McBSP) TMS320C6201 digital signal processor (DSP) interfaces Voice Band Audio Processor (VBAP). VBAP under discussion TLV320AC36, 2.048 audio processor which µ-law companding device. interface also applicable TI's TLV320AC37, A-law companding audio processor. highly programmable McBSP provides glue-less interface VBAP. VBAP processes analog signals from audio sources such microphone, converts digital data choices) which then transmitted processing. turn will transmit digital data VBAP conversion analog data. VBAP outputs this analog data device such speaker. McBSP supports both companded (8-bit) linear (16-bit) form data that VBAP supports.
Digital Signal Processing Solutions
November 1998
Contents
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface Design Problem.3 Overview VBAP Operation Hardware Interface.4 McBSP Register Configuration McBSP VBAP Initialization.7 Timing Analysis.8 Conclusion
Figures
Figure `C6201 McBSP VBAP interface block diagram.3 Figure 'C6201 VBAP Schematic Fixed Data Rate Mode.5 Figure Fixed Data Rate Mode Timing Diagram Figure Receive Control Register (RCR) Figure Transmit Control Register (XCR) Figure Sample Rate Generator Register (SRGR).7 Figure Control Register (PCR).7 Figure Serial Port Control Register (SPCR) Figure McBSP Timing Internal Clocks Frames.9
Tables
Table McBSP Register Configuration Values Table Timing Analysis McBSP VBAP
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface Design Problem
interface Voice-Band Audio Processor (VBAP) TMS320C6000 Multichannel Buffered Serial Port (McBSP)?
Overview
block diagram interface between McBSP VBAP shown Figure analog voice-band input from microphone processed Analog-to-Digital Converter (ADC) VBAP. either compresses analog signal 8-bit data format compand operation chosen VBAP) transforms analog data 13-bit linear data linear data format chosen) with three LSBs padded with zeroes volume control data. VBAP thus performs transmit encoding analog data provides digital data McBSP receiver. process digital data necessary. McBSP either transmit 8-bit companded data µ-law A-law format) 16-bit linear data receive section VBAP. Digital-to-Analog Converter (DAC) VBAP expands serial data analog form sends speaker. both cases transmit receive, McBSP programmed either transmit companded data either A-law format interfacing TLV320AC37 µ-law format interfacing TLV320AC36. µ-law A-law companding standard part CCITT G.711 recommendation.
Figure `C6201 McBSP VBAP interface block diagram
'C6000
8(compand)/ 16(linear)
TLV320AC36/7 VBAP
Compress Microphone
Receiver
8(compand)/ 16(linear)
Transmitter
Expand
Speaker
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
VBAP Operation
VBAP offers modes operation, which pin-selectable. They are:
Fixed Data Rate Mode: single master clock (CLK) used clock both receive transmit data. Data transmitted rising edge clock receive data sampled falling edge CLK. Master clock frequency 2.048 MHz. Frame sync signal inputs, active high period indicate starting frame. Frame syncs must have 8KHz sampling rate. Variable Data Rate Mode: received data sampled falling edge DCLKR transmit data output rising edge DCLKX. These clocks slower than master rate 2.048MHz.
DCLKR DCLKX have range between 64KHz 2.048MHz compand mode 128KHz 2.048Mhz 16-b linear data. master clock used clocking data, internal filters. inputs remain high entire frame remain 8KHz sampling rate. More information VBAP itself obtained from following literature:
TCM320AC3x/4x Voice-Band Audio Processors Application Report, June 1996, Literature Number SLWA001 TLV320AC36, TLV320AC37 Voice-Band Audio Processors (VBAPTM) data sheet, October 1997, Literature number SLWS006B
Hardware Interface
This application note describes Fixed Data Rate Mode VBAP interface McBSP. Accordingly, interface schematic this shown Figure Since VBAP device, voltage translation necessary interface McBSP. Also, electret type microphone speaker headset) should part. Clock Generation: 2.048 clock generator drives master clock, CLK, VBAP external clock CLKS McBSP. McBSP uses this external clock source with CLKGDV=0 generate internal transmit receive clocks shift data. CLKR CLKX McBSP should configured outputs. DCLKR should tied left unconnected (logic high) fixed data rate mode. Alternatively, timer used generate 2.048MHz shift clock using (CPU clock/4) timer clock source. 200MHz DSP, timer CLKSRC would 50MHz. timer used clock mode (50% duty cycle). derive period shift clock, timer period register value calculated follows: sclk_period Period_register) f(CLKSRC) Hence, period_register 2*20 approx.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Frame Sync Generation: McBSP generates 8KHz sampling rate frame sync signal. frame sync parameters, FPER FWID programmable McBSP. order generate period (8kHz) frame sync based 2.048 clock, frame period (not FPER) should clocks. Therefore FPER 255. FWID zero since frame sync bit-clock high beginning frame. Note that (FPER+1) (FWID+1) represent actual values. Both driven same internal frame sync generator signal (FSG).
Figure 'C6201 VBAP Schematic Fixed Data Rate Mode
'C6201 TLV320AC36/7 FSX1 FSR1 CLKX1 CLKR1 CLKS1
2.048MHz Clock Generator
3.3V
0.1uF
DOUT DCLKR DCLKX LINSEL
VMID MICBIAS MICGS MICIN MICMUTE
3.3uF Microphone 470pF
EARA
EARGS
Speaker
EARB EARMUTE
Note: (R1+R2) 100K; Refer TLV320AC36/7 datasheet
Data Format: McBSP drives data receives data to/from VBAP either 8-bit compand format 16-bit linear format. /LINSEL VBAP when pulled enables data linear format. Accordingly (R/X)COMPAND McBSP should programmed receiving noncompanded data. schematic shows /LINSEL being driven therefore controlled software. Electret Microphone Interface: electret-type microphone chosen this interface. most effective noise cancellation produces clear voice transmission (compared carbon dynamic type). passive components chosen this interface based information provided VBAP datasheet.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Speaker Interface: resistor network schematic controlling power amplifier gain. parallel combination (R1+R2) load resistance (RL) sets total loading. VBAP datasheet more details. Power Down: active /PDN VBAP driven when reduced power consumption required VBAP use. inverted provide this control. Alternatively, simple switch connected /PDN will also suffice.
McBSP Register Configuration
timing diagram applicable fixed data rate mode VBAP shown Figure master clock from 2.048 clock generator drives McBSP's CLKS VBAP's CLK. CLKS drives bit-clocks CLKR CLKX with divide-downs McBSP data transfer. Frame syncs generated rising edge CLKR/CLKX. First data (MSB) transmitted/received with bit-clock delay from FSX/FSR. Therefore (R/X)DATDLY=1.
Figure Fixed Data Rate Mode Timing Diagram
CLKS/CLK CLKR/CLKX FSX/FSR DX/DR C7/L15 C6/L14 C5/L13 C0/L8 C7/L15
Cx/Ly: CompandData LinearData
programmable registers McBSP should take values based timing diagram frame sync requirements, which were described earlier. Figure through Figure Table shows register values application.
Figure Receive Control Register (RCR)
RPHASE reserved RFRLEN2 RFRLEN1 RWDLEN1 RWDLEN2 RCOMPAND reserved RFIG RDATDLY
Figure Transmit Control Register (XCR)
XPHASE reserved XFRLEN2 XFRLEN1 XWDLEN1 XWDLEN2 XCOMPAND reserved XFIG XDATDLY
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Figure Sample Rate Generator Register (SRGR)
GSYNC CLKSP CLKSM FSGM FWID FPER
0x00 CLKGDV
Figure Control Register (PCR)
0x0000 reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Figure Serial Port Control Register (SPCR)
0x00 FRST22 GRST21 XINXSYNCERR XEMPTY4 RIN3 RSYNCERR RFULL XRDY RRDY XRST0 RRST-
RJUST CLKSTP reserved reserved reserved
Table McBSP Register Configuration Values
Register [bit-field
RCR[20:19] RCR[17:16] XCR[20:19] XCR[17:16] SRGR[28] SRGR[27:16] SRGR[15:8] SRGR[7:0] PCR[11] PCR[10] PCR[9] PCR[8] SPCR[31:0]
Bit-field Name
RCOMPAND RDATDLY XCOMPAND XDATDLY FSGM FPER FWID CLKGDV FSXM FSRM CLKXM CLKRM
Value
0xFF default
Description
Receive µ-law companding bit-clock data delay Transmit µ-law companding bit-clock data delay generated Frame period 2.048Mhz clock periods 8KHz frame sync sampling rate Generates clock period active-high pulse. 2.048 CLKS drives CLKR/X with divide-down output output CLKX output generated CLKS CLKR output generated CLKS Reset bits will driven initialization procedure
McBSP VBAP Initialization
Typically services McBSP when read/write data events occur. VBAP (except McBSP reset) assumed powered before following steps taken. Power applied clock sources connected. /PDN VBAP driven send power down state when needed.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
following steps describe setup interrupts, DMA, McBSP required order. McBSP initialization procedure using (E)DMA also discussed Application Report SPRA959, TMS320C6000 McBSP Initialization. Program Sample Rate Generator Register (SRGR), Serial Port Control Register (SPCR), Control Register (PCR), Receive Control Register (RCR) values shown above. Caution: /GRST SPCR this step. Take sample rate generator reset setting /GRST=1 SPCR. Enabling Interrupts: interrupts, have Global Interrupt Enable (GIE), Non-Maskable Interrupt Enable (NMIE) bits IER. Select channel(s) want use. Enable interrupts that correspond channel that will used service McBSP. default mapping channel-complete interrupts follows: channel channel channel channel
interrupt interrupt interrupt interrupt
initialization: Program channel required operation. Following would typical
Source address Destination address valid memory location Transfer counter number elements transferred. Receive synchronization event, R/WSYNC REVT from McBSP reads. Transmit synchronization event, R/WSYNC XEVT from McBSP writes. channel complete interrupt bit, TCINT enabled Priority bit, optional, recommended.
Instruct channel(s) run. example, START=01b channel's primary control register start without auto-initialization. will start first transfer upon receiving first read/write sync event. Wake VBAP pulling /PDN logic high state this done software). Alternatively, this also done after power (before step above) using switch. assumed here that appropriate /LINSEL value chosen desired operation. VBAP ready frame sync pulses from McBSP start transmission reception /XRST=/RRST=1 wake McBSP. /FRST=1 start frame sync generator McBSP. This causes frame sync pulses FSX/FSR pins which eventually drive VBAP.
Timing Analysis
shown Figure outputs McBSP driving VBAP. CLKR CLKX generated internally external clock source CLKS without divide-down. Figure shows timing relation transmit data frame sync, receive data frame sync with respect their respective clocks.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Figure McBSP Timing Internal Clocks Frames
CLKX(int) td(CKXH-FXV) (int) tdis(CKXH-DXZ) CLKR(int) td(CKRH-FRV) (int) th(CKRL-DR) tsu(DR-CKRL) Bit(n-1) (n-2) td(CKXH-DX) Bit(n-1)
(n-2)
timing analysis shown Table satisfies hardware interface requirements. timing numbers McBSP match with that VBAP with sufficient timing margins. timing numbers VBAP correspond TLV320AC36/37 datasheet, Literature Number SLWS006B. McBSP timings found TMS320C6201 datasheet, Literature Number SPRS051D.
Table Timing Analysis McBSP VBAP
VBAP Timing Requirements C6201 Switching Characteristics (DIN)min td(CKXH-DXV)max Data Setup Time 244.14 (DIN)min td(CKXH-DXV)min Data Hold Time 244.14 (FSR)min td(CKXH-FXV)max Setup Time 244.14 (FSR)min td(CKXH-FXV)min Hold Time 244.14 (FSX)min td(CKXH-FRV)max Setup Time 244.14 (FSX)min td(CKXH-FRV)min Hold Time 244.14 C6201 Timing Requirements VBAP Switching Characteristics tsu(DRV-CKXL)min tpd2(max) Data Setup Time 244.14 th(CKXL-DRV)min tpd2(min) Data Hold Time 244.14 NOTE: following true above calculations: represents clock high duration represents clock duration. UNIT 240.14 244.14 240.14 244.14 240.14 242.14
209.14 244.14
Since CLKGDV CLK(R/X) derived from clock will have duty cycle. Therefore where Period CLK(R/X), 488.28 2.048 CLKS clock.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Conclusion
programmability `C6x McBSP provides ease interface VBAP. Although this application note only describes fixed data rate mode VBAP, equally simple interface variable-data rate mode. Variable data rate mode allows varying data rates maximum 2.048MHz. example code appendix shows McBSP1 initialization operation.
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
Appendix Sample Source Code
vbap.c: Uses peripheral support library McBSP1 used communicate VBAP u-law companded fixed data rate mode. channel used service McBSP. CLKX, CLKR generated using CLKS clock. FSX, outputs that drive VBAP's frame syncs. #include "common.h" #define M0TO1 FALSE McBSP0 unused #define M1TO0 TRUE McBSP1 used #define CLKGDV1 #define FPER1 0xFF #define FWID1 #define CLKSM1 CLK_MODE_CLKS #define M1TO0_MSTR TRUE #define XFER_SIZE number data transferred #define XFER_TYPE DMA_XFER
void init_m0to1(void); void init_M0_srgr(void); void init_m1to0(void); void init_M1_srgr(void); void main(void) xfer_size; xfer_type; mcsp0to1_rate; mcsp1to0_rate; recv1_done FALSE; xmit1_done FALSE; mcsp1to0 M1TO0; mcsp0to1 M0TO1; xfer_size XFER_SIZE; xfer_type XFER_TYPE; SRGR values needed init_M1_srgr(); Now, initialize other control registers McBSP operation (mcsp1to0)
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
init_m1to0(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(1); Reset channels switch (xfer_type) case DMA_XFER: dma_reset(); set_interrupts();/* Initialize service McBSP (mcsp1to0) uses xmit recv*/ DMA0_SRC_ADDR MCBSP_DRR_ADDR(1); DMA0_DEST_ADDR (unsigned int) in1; REG_WRITE (DMA0_XFR_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA0_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, SEN_REVT0, RSYNC, RSYNC_SZ); DMA_START(DMA_CH0); DMA2_SRC_ADDR (unsigned int) out1; DMA2_DEST_ADDR MCBSP_DXR_ADDR(1); REG_WRITE (DMA2_XFR_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT0, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); SET_BIT (MCBSP_SPCR_ADDR(1), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); while (!xmit1_done !recv1_done); break; reg_dump(); 0x00007000;
PowerDown shut MCSP
void init_m1to0(void)
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSXP, LOAD_FIELD (MCBSP_PCR_ADDR(1), M1TO0_MSTR, CLKXM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSXM, SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(1), FSX_FSG, FSGM, setup LOAD_FIELD (MCBSP_XCR_ADDR(1), SINGLE_PHASE, XPHASE, LOAD_FIELD (MCBSP_XCR_ADDR(1), WORD_LENGTH_8, XWDLEN1, XWDLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), XFRLEN1, XFRLEN1_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), DATA_DELAY1, XDATDLY, XDATDLY_SZ); LOAD_FIELD (MCBSP_XCR_ADDR(1), COMPAND_ULAW, XCOMPAND, XCOMPAND_SZ); setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_POL_HIGH, FSRP, LOAD_FIELD (MCBSP_PCR_ADDR(1), M1TO0_MSTR, CLKRM, LOAD_FIELD (MCBSP_PCR_ADDR(1), FSYNC_MODE_INT, FSRM, setup LOAD_FIELD (MCBSP_RCR_ADDR(1), SINGLE_PHASE, RPHASE, LOAD_FIELD (MCBSP_RCR_ADDR(1), WORD_LENGTH_8, RWDLEN1, RWDLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), RFRLEN1, RFRLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), DATA_DELAY1, RDATDLY, RDATDLY_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(1), COMPAND_ULAW, RCOMPAND, RCOMPAND_SZ); SPCR LOAD_FIELD (MCBSP_SPCR_ADDR(1), RXJUST_RJZF, RJUST, RJUST_SZ);
void init_M1_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKGDV1, CLKGDV, CLKGDV_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), FWID1, FWID, FWID_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), FPER1, FPER, FPER_SZ); LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKSM1, CLKSM, LOAD_FIELD (MCBSP_SRGR_ADDR(1), CLKS_POL_RISING, CLKSP, LOAD_FIELD (MCBSP_SRGR_ADDR(1), GSYNC_OFF, GSYNC,
void init_M0_srgr(void)
void reg_dump(void) (int MCBSP_ADDR(0);
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
(int MCBSP_ADDR(1); i++) regdump0[i] m0[i]; regdump1[i] m1[i]; void set_interrupts(void) intr_init(); INTR_MAP_RESET; Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); intr_hook (c_int08, CPU_INT8);
enable NMIE, default interrupt corresponding channel INTR_ENABLE(CPU_INT_NMI);/* Enable NMIE INTR_GLOBAL_ENABLE; CSR*/ INTR_ENABLE(11); default interrupt corresponding channel INTR_ENABLE(8); return;
DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit1_done TRUE; return; interrupt void c_int08(void) recv1_done TRUE; return;
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
COMMON.H V1.00 Copyright 1997 Texas Instruments Incorporated #include <dma.h> #include <emif.h> #include <intr.h> #include <timer.h> #include <cache.h> #include <hpi.h> #include <mcbsp.h> #include <regs.h> #include <stdio.h> #include <trgcio.h> #include <stdlib.h> variables used tcase mcsp0to1; mcsp1to0; volatile xmit1_done; volatile recv0_done; volatile xmit0_done; volatile recv1_done;
#define FALSE #define TRUE
BUFFERS DEFINED data6201.asm #define BUFFER_SIZE #define COMPAND_SIZE4096 extern in0[BUFFER_SIZE]; extern in1[BUFFER_SIZE]; extern out0[BUFFER_SIZE]; extern out1[BUFFER_SIZE]; extern regdump0[10]; extern regdump1[10]; extern ulawenc[BUFFER_SIZE]; extern cregister volatile unsigned AMR; extern cregister volatile unsigned CSR; extern cregister volatile unsigned IFR; extern cregister volatile unsigned ISR; extern cregister volatile unsigned ICR; extern cregister volatile unsigned IER;
extern interrupt void c_nmi01(void); extern interrupt void c_int04(void); extern interrupt void c_int05(void); extern interrupt void c_int06(void);
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
extern interrupt void c_int07(void); extern interrupt void c_int08(void); extern interrupt void c_int09(void); extern interrupt void c_int10(void); extern interrupt void c_int11(void); extern interrupt void c_int12(void); extern interrupt void c_int13(void); extern interrupt void c_int14(void); extern interrupt void c_int15(void); #define DMA_XFER #define POLL_XFER #define INT_XFER #define GPIO #define DLB1 #define DLB2 #define SPLIT_XFER #define HW_BYTE #define DMA_SPI #define DMA_STB #define DMA_MCM_FLY #define DMA_NEW_FRAMESYNC #define AUTO_INIT #define DMA_SORT #define SPLIT_SORT #define DMA_SYNCERR #define DMA_BYTE #define DMA_HALFWORD extern void reset_mcbsp(void) slave wake before frame master that frames lost (mcsp0to1) (GET_BIT(MCBSP_PCR_ADDR(1), FSRM)) {/*(mcsp1->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); else SET_BIT (MCBSP_SPCR_ADDR(1), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); (mcsp1to0) (GET_BIT(MCBSP_PCR_ADDR(0), FSRM)){ /*(mcsp0->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); else SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST);
TMS320C6000 McBSP Voice Band Audio Processor (VBAP) Interface
SET_BIT (MCBSP_SPCR_ADDR(1), FRST); extern void set_interrupts(void); extern void reg_dump(void);
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