Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

Datasheet Thumbnail

Top Searches for this datasheet

TMS320C6000 McBSP Initialization
Shaku Anjanaiah Digital Signal Processing Solutions
TMS320C6000 Multi-channel Buffered Serial Port (McBSP) operate variety modes application requirements. proper operation, serial port must initialized specific order. This document describes initialization steps necessary when either (E)DMA used service McBSP data. Typically (E)DMA used perform read/write transfers from/to McBSP. (E)DMA transfers read/write synchronized McBSP provides these sync events. Alternatively, cases where reads from writes DXR, either polled interrupt method used.
Digital Signal Processing Solutions
November 1998
Contents
TMS320C6000 McBSP Initialization Design Problem.3 McBSP Introduction.3 Servicing McBSP Initialization Requirements
Figures
Figure McBSP Functional Block Diagram.4 Figure McBSP Initialization Flowchart
TMS320C6000 McBSP Initialization
TMS320C6000 McBSP Initialization Design Problem
initialize McBSP correct frame synchronization data exchange? What important initialization steps their order execution?
McBSP Introduction
main functional blocks McBSP shown Figure They are:
Transmitter: transmitter section responsible serial transmission data that written DXR. contents copied transmit shift register XSR. transfer starts soon transmit frame sync (FSX) detected. data transmitted shifted every transmit clock CLKX. data written using either DMA. Receiver: data received shifted into Receive Shift Register (RSR) every receive clock (CLKR). Again, actual shifting data begins after detection receive frame sync (FSR). data copied Receive Buffer Register (RBR) then Data Receive Register (DRR). read either DMA. Sample Rate Generator: name implies, this module generates control signals such transmit/receive clocks frame sync signals necessary data transfer from McBSP. Clock generation circuitry allows user choose either clock external source CLKS generate CLKR/X. Frame sync signal properties such frame period frame width also programmable. FSR/X, CLKR/X bidirectional pins, therefore inputs outputs. Events/Interrupt Generation: McBSP generates sync events indicate that data ready that ready data. They read sync event REVT, write sync event XEVT. Similarly read/write McBSP based interrupts (RINT XINT) generated McBSP.
TMS320C6000 McBSP Initialization
Figure McBSP Functional Block Diagram
'C6000 McBSP
CLKX
Transmitter
CLKR
Receiver
CPUclk CLKS
Sample Rate Gen.
Events/ Interrupts RINT
XEVT
XINT
Servicing McBSP
`C6000 service McBSP DMA. control registers have programmed CPU. But, data registers accessed either DMA. Typically, channel(s) used read/write data registers, thus relieving from servicing slow peripheral. more details servicing peripheral, please refer TMS320C6000 Applications application note. DMA: write accesses write synchronization event, XEVT, provided McBSP. Similarly read synchronized internal REVT signal from McBSP. Therefore, reads from writes McBSP every serial element transfer. Once completes required number element transfers, programmed generate channel complete interrupt required. CPU: When used service McBSP, done either interruptdriven method polled method. Polling method ties while waiting data transmitted received. (R/X)RDY bits SPCR polled receive/transmit ready condition McBSP.
TMS320C6000 McBSP Initialization
interrupt-driven case, performs other processing while interrupts from McBSP signal when needs served. default value (R/X)IN= causes McBSP interrupt (R/X)INT every element transfer interrupts enabled). XINT generated when ready accept data, RINT generated when serial element been received DRR. Other interrupt mode settings (R/X)INare meant servicing McBSP data reads/writes, diagnostic, tracking purposes.
Initialization Requirements
Generation control signals such clock, frame sync, clock source McBSP programmable. order which respective modules activated important correct operation McBSP. example, consider case when transmitter clock frame master meaning responsible generation clocks frames itself device (receiver) communicating first step ensure that slave this case receiver) awake (taken reset) ready receive frame data from transmitter. This followed taking transmitter reset, then activating frame sync generator transmitter. This ensures that receiver does lose first frame data.
McBSP Initialization Cases
This section describes step-by-step procedure McBSP initialization based data transfers. following three methods initialization procedure summarized flowchart shown Figure Transfers: following steps describe setup interrupts, DMA, McBSP required order. /GRST=/XRST=/RRST=/FRST=0. coming device reset, this required. Program Sample Rate Generator Register (SRGR), Serial Port Control Register (SPCR), Control Register (PCR), Receive Control Register (RCR) required values. Caution: bits described Step while programming these registers. Take sample rate generator reset setting /GRST=1 SPCR. Internal clock CLKG driven chosen clock source programmed clock divide-down. Note: frame syncs clocks inputs both transmit receive sections McBSP, this step required. Wait clocks (CLKR/X). simple formula arrive this number terms clock cycles clock source: P=(1/CPUclock). number clocks equal data bit-clocks (1+CLKGDV) where min. value CLKGDV=1 CLKS clock source: Ps=(1/CLKS frequency) P=(1/CPUclock).
TMS320C6000 McBSP Initialization
number clocks equal data bit-clocks (1+CLKGDV) /P), where min. value CLKGDV=0 CLKS greater than (CPUclock/2) general, following formula used depending clock source: ((1+CLKGDV) CLKSM) ((1+CLKGDV) (!CLKSM)) Enabling Interrupts: interrupts, have Global Interrupt Enable (GIE), Non-Maskable Interrupt Enable (NMIE) bits IER. Select channel want use. Enable interrupts that correspond channel that will used service McBSP. These interrupts used notify frame. default mapping channel-complete interrupts follows:
channel channel channel channel
interrupt interrupt interrupt interrupt
stop condition. Clear previous R/WSTAT bits that unwanted transfers occur. initialization: Program channel required operation. following would typical
Source address reads memory location writes. Destination address memory location reads writes. Transfer counter number elements transferred. Receive synchronization event, R/WSYNC REVT from McBSP reads. Transmit synchronization event, R/WSYNC XEVT from McBSP writes. channel complete interrupt bit, TCINT enabled Priority bit, optional, recommended.
Instruct run. example, START=01b channel's primary control register start without auto-initialization. Take section (transmitter/receiver) that frame master (frame sync input) reset setting /XRST /RRST=1. slave ready accept frame sync start data transfer. Alternatively, frame sync interrupt ((R/X)INTM=10b) used wake transmitter/receiver. Pull frame master (transmitter receiver) reset (/XRST /RRST FSGM=1 (frame sync generated sample rate generator), enable frame sync generator setting /FRST=1. first frame sync will output after CLKG clocks. FSGM=0, frames generated every copy therefore /FRST used. case, master starts data transfer. Interrupt-driven Transfers: Setting (R/X)INTM=00b SPCR allows McBSP interrupt whenever data ready when data written DXR. initialization steps similar driven transfers except that used. Therefore, replace steps through under Transfers with following: required XINT0/1 and/or RINT0/1 interrupts Interrupt Multiplexer Registers.
TMS320C6000 McBSP Initialization
Enable mapped interrupts. Once McBSP initialized (after step above), each element transfer will cause execution that writes reads from DRR. Polled Transfers: transmit receive ready, (R/X)RDY bits SPCR polled determine readiness transmitter receiver. Here, check this condition which might prevent from performing needed processing. McBSP initialization process some differences compared previous methods McBSP service. Since neither interrupt-driven transfer applicable this case, steps through required. steps therefore followed polling loop.
TMS320C6000 McBSP Initialization
Figure McBSP Initialization Flowchart
'C6x reset; McBSP Reset; /XRST=/RRST=0 /GRST=/FRST=0
Program McBSP Control registers McBSP still reset state;
CLKXM CLKRM FSXM FSRM
Frame Master? (FSX output)
Pull reset; /XRST=1 FSXM=0; /RRST=1 FSRM=0
/GRST=1; Wait data clocks
Ensure slave reset
/XRST and/or /RRST=1 /FRST FSGM=1 Data Transfer Starts
Interrupt-driven Transfer?
(Polled Transfer) interrupts CPU. Enable GIE, NMIE, required CPU_INTxx. Transfer? Clear R/WSTAT bits. channel STOP state. registers transfer. START state. Select appropriate channels initiate read and/or write transfers. transfer parameters required Parameter RAM.
EDMA Transfer?
TMS320C6000 McBSP Initialization
Appendix
following sample code dlb.c common.h illustrate sequence programming McBSP control registers initialization data formats. Some functions code also show register setup reading/writing from/to McBSP. Note that this sample code Digital Loop Back Mode where McBSPs `C6000 connected internally software (DLB=1).
Copyright 1997 Texas Instruments Incorporated 05/29/98: Shaku Anjanaiah dlb.c: McBSP0 used mode using service McBSP. CLKX generated using clock SRG. #include "common.h" #define M0TO1 TRUE McBSP0 transmits McBSP1 #define M1TO0 FALSE McBSP1 transmits McBSP0 #define CLKGDV0 #define FPER0 #define FWID0 #define CLKGDV1 #define FPER1 #define FWID1 #define XFER_SIZE #define XFER_TYPE DMA_XFER #define CLKSM0 #define CLKSM1 CLK_MODE_CPU CLK_MODE_CPU
#define M0TO1_MSTR TRUE #define M1TO0_MSTR TRUE void void void void init_m0to1(void); init_M0_srgr(void); init_m1to0(void); init_M1_srgr(void);
void main(void) xfer_size; xfer_type; mcsp0to1_rate; mcsp1to0_rate; recv0_done FALSE; xmit0_done FALSE; mcsp1to0 M1TO0; mcsp0to1 M0TO1; xfer_size XFER_SIZE;
TMS320C6000 McBSP Initialization
xfer_type XFER_TYPE; SRGR values needed init_M0_srgr(); Now, initialize other control registers McBSP operation (mcsp0to1) init_m0to1(); Enable sample rate generator; /GRST=1 MCBSP_SAMPLE_RATE_ENABLE(0);
switch (xfer_type) case DMA_XFER: dma_reset();/* Reset channels set_interrupts(); Initialize service McBSP (mcsp0to1) uses xmit recv*/ DMA0_SRC_ADDR MCBSP_DRR_ADDR(0); DMA0_DEST_ADDR (unsigned int) in0; REG_WRITE (DMA0_XFR_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA0_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ); LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA0_PRIMARY_CTRL_ADDR, SEN_REVT0, RSYNC, RSYNC_SZ); DMA_START(DMA_CH0); DMA2_SRC_ADDR (unsigned int) out0; DMA2_DEST_ADDR MCBSP_DXR_ADDR(0); REG_WRITE (DMA2_XFR_COUNTER_ADDR, xfer_size); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ESIZE32, ESIZE, ESIZE_SZ); SET_BIT (DMA2_PRIMARY_CTRL_ADDR, TCINT); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_ADDR_INC, SRC_DIR, SRC_DIR_SZ); LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, DMA_DMA_PRI, PRI, LOAD_FIELD (DMA2_PRIMARY_CTRL_ADDR, SEN_XEVT0, WSYNC, WSYNC_SZ); DMA_START(DMA_CH2); SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); while (!xmit0_done !recv0_done); break; reg_dump(); 0x00007000;
PowerDown shut MCSP
void init_m0to1(void) setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_POL_HIGH, FSXP, LOAD_FIELD (MCBSP_PCR_ADDR(0), M0TO1_MSTR, CLKXM, LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_MODE_INT, FSXM, SRGR setup LOAD_FIELD (MCBSP_SRGR_ADDR(0), FSX_FSG, FSGM, setup
TMS320C6000 McBSP Initialization
LOAD_FIELD LOAD_FIELD LOAD_FIELD LOAD_FIELD LOAD_FIELD (MCBSP_XCR_ADDR(0), (MCBSP_XCR_ADDR(0), (MCBSP_XCR_ADDR(0), (MCBSP_XCR_ADDR(0), (MCBSP_XCR_ADDR(0), SINGLE_PHASE, XPHASE, WORD_LENGTH_8, XWDLEN1, XWDLEN1_SZ); XFRLEN1, XFRLEN1_SZ); DATA_DELAY1, XDATDLY, XDATDLY_SZ); NO_COMPAND_MSB_1ST, XCOMPAND, XCOMPAND_SZ);
setup*/ LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_POL_HIGH, FSRP, LOAD_FIELD (MCBSP_PCR_ADDR(0), !M0TO1_MSTR, CLKRM, LOAD_FIELD (MCBSP_PCR_ADDR(0), FSYNC_MODE_EXT, FSRM, setup LOAD_FIELD (MCBSP_RCR_ADDR(0), SINGLE_PHASE, RPHASE, LOAD_FIELD (MCBSP_RCR_ADDR(0), WORD_LENGTH_8, RWDLEN1, RWDLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(0), RFRLEN1, RFRLEN1_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(0), DATA_DELAY1, RDATDLY, RDATDLY_SZ); LOAD_FIELD (MCBSP_RCR_ADDR(0), NO_COMPAND_MSB_1ST, RCOMPAND, RCOMPAND_SZ); SPCR LOAD_FIELD (MCBSP_SPCR_ADDR(0), RXJUST_RJZF, RJUST, RJUST_SZ); LOAD_FIELD (MCBSP_SPCR_ADDR(0), DLB_ENABLE, DLB,
void init_M0_srgr(void) LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), LOAD_FIELD (MCBSP_SRGR_ADDR(0), void init_M1_srgr(void) void reg_dump(void) (int MCBSP_ADDR(0); (int MCBSP_ADDR(1); i++) regdump0[i] m0[i]; regdump1[i] m1[i];
CLKGDV0, CLKGDV, CLKGDV_SZ); FWID0, FWID, FWID_SZ); FPER0, FPER, FPER_SZ); CLKSM0, CLKSM, CLKS_POL_RISING, CLKSP, GSYNC_OFF, GSYNC,
void set_interrupts(void) intr_init(); INTR_MAP_RESET; Hook interrupt service routine interrupt intr_hook (c_int11, CPU_INT11); intr_hook (c_int08, CPU_INT8);
TMS320C6000 McBSP Initialization
enable NMIE, default interrrupt correponding channel INTR_ENABLE(CPU_INT_NMI);/* Enable NMIE INTR_GLOBAL_ENABLE; CSR*/ INTR_ENABLE(11); default interrrupt correponding channel INTR_ENABLE(8); return;
DATA TRANSFER COMPLETION ISRS interrupt void c_int11(void) xmit0_done TRUE; return; interrupt void c_int08(void) recv0_done TRUE; return;
dlb.c
COMMON.H V1.00 Copyright 1997 Texas Instruments Incorporated #include #include #include #include #include #include #include #include #include #include #include <dma.h> <emif.h> <intr.h> <timer.h> <cache.h> <hpi.h> <mcbsp.h> <regs.h> <stdio.h> <trgcio.h> <stdlib.h>
variables used tcase mcsp0to1; mcsp1to0; volatile xmit1_done; volatile recv0_done; volatile xmit0_done; volatile recv1_done;
#define FALSE #define TRUE
TMS320C6000 McBSP Initialization
BUFFERS DEFINED data6201.asm #define BUFFER_SIZE #define COMPAND_SIZE 4096 extern extern extern extern extern extern extern extern extern extern extern extern extern in0[BUFFER_SIZE]; in1[BUFFER_SIZE]; out0[BUFFER_SIZE]; out1[BUFFER_SIZE]; regdump0[10]; regdump1[10]; ulawenc[BUFFER_SIZE]; volatile volatile volatile volatile volatile volatile unsigned unsigned unsigned unsigned unsigned unsigned AMR; CSR; IFR; ISR; ICR; IER;
cregister cregister cregister cregister cregister cregister
extern extern extern extern extern extern extern extern extern extern extern extern extern #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define
interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt
void void void void void void void void void void void void void
c_nmi01(void); c_int04(void); c_int05(void); c_int06(void); c_int07(void); c_int08(void); c_int09(void); c_int10(void); c_int11(void); c_int12(void); c_int13(void); c_int14(void); c_int15(void);
DMA_XFER POLL_XFER INT_XFER GPIO DLB1 DLB2 SPLIT_XFER HW_BYTE DMA_SPI DMA_STB DMA_MCM_FLY DMA_NEW_FRAMESYNC AUTO_INIT DMA_SORT SPLIT_SORT DMA_SYNCERR
#define DMA_BYTE #define DMA_HALFWORD extern void reset_mcbsp(void) slave wake before frame master that frames lost (mcsp0to1)
TMS320C6000 McBSP Initialization
(GET_BIT(MCBSP_PCR_ADDR(1), FSRM)) {/*(mcsp1->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); else SET_BIT (MCBSP_SPCR_ADDR(1), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); (mcsp1to0) (GET_BIT(MCBSP_PCR_ADDR(0), FSRM)){ /*(mcsp0->pcr.fsrm) SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(0), FRST); else SET_BIT (MCBSP_SPCR_ADDR(0), RRST); SET_BIT (MCBSP_SPCR_ADDR(1), XRST); SET_BIT (MCBSP_SPCR_ADDR(1), FRST); extern void set_interrupts(void); extern void reg_dump(void);
common.h
INTERNET www.ti.com Register with TI&ME build custom information pages receive product updates automatically email.
Semiconductor Home Page http://www.ti.com/sc Distributors
PRODUCT INFORMATION CENTERS
Europe, Middle East, Africa Phone Deutsch +49-(0) 8161 3311 English +44-(0) 1604 3399 Francais +33-(0) 1-30 Italiano +33-(0) 1-30 +33-(0) 1-30-70 Email epic@ti.com Japan Phone International Domestic International Domestic Email Asia Phone International Domestic Australia
TMS320 Hotline email Americas Phone Email
+81-3-3457-0972 +0120-81-0026 +81-3-3457-1259 +0120-81-0036 pic-japan@ti.com
(281) 274-2320 (281) 274-2324 (281) 274-2323 dsph@ti.com +1(972) 644-5580 +1(972) 480-7800 sc-infomaster@ti.com
+886-2-3786800 1-800-881-011
Asia (continued) Number China Number Hong Kong Number India Number Indonesia Number Korea Malaysia Number Zealand Number Philippines Number Singapore Number Taiwan Thailand Number
-800-800-1450 10811 -800-800-1450 800-96-1111 -800-800-1450 000-117 -800-800-1450 001-801-10 -800-800-1450 080-551-2804 1-800-800-011 -800-800-1450 +000-911 -800-800-1450 105-11 -800-800-1450 800-0111-111 -800-800-1450 080-006800 0019-991-1111 -800-800-1450
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain application using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. Copyright 1998, Texas Instruments Incorporated trademark Texas Instruments Incorporated. Other brands names property their respective owners.
IMPORTANT NOTICE
TMS320C6000 McBSP Initialization

Shaku Anjanaiah Digital Signal Processing Solutions TMS320C6000 M

Top Searches for this datasheet

Other recent searches