Shaku Anjanaiah Vassos Soteriou ABSTRACT TMS320C6000 (C6000) Multichan
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TMS320C6000 McBSP Interface
Shaku Anjanaiah Vassos Soteriou ABSTRACT TMS320C6000 (C6000) Multichannel Buffered Serial Port (McBSP) designed interface device that supports synchronous Serial Peripheral Interface (SPI). This document describes hardware interface between McBSP ROM. McBSP operates master user-specified clock stop (CLKSTP) mode order communicate with ROM. McBSP initialization control register programming also discussed. Digital Signal Processing Solutions
Contents Design Problem Solution Configuration McBSP Initialization Timing Analysis List Figures Figure Figure Figure Figure Figure Figure Figure Figure McBSP Master Interface Slave Device Receive Control Register (RCR Master) Transmit Control Register (XCR Master) Sample Rate Generator Register (SRGR Master) Control Register (PCR Master) Serial Port Control Register (SPCR Master) Clock Stop Mode Options C6000 Timing, CLKSTP 11b, CLKXP List Tables Table McBSP Register Values Clock Table Timing Numbers McBSP Master Table Timing Analysis Master Slave
TMS320C6000 C6000 trademarks Texas Instruments. trademarks property their respective owners.
Appendix
SPRA487B
Design Problem
interface Serial Peripheral Interface (SPI) TMS320C6000?
Solution
multichannel buffered serial port (McBSP) TMS320C6000 interfaces with glue logic. system typically 4-wire interface comprising serial data serial data out, serial clock, device select. McBSP provides this 4-wire interface CLKX, pins, respectively. McBSP supports interface synchronous, full-duplex, variable element length (element length fixed given transfer), master slave mode back-to-back transmission reception. This feature achieved using clock-stop (CLKSTP) mode McBSP. This document discusses McBSP interface Atmel serial CMOS EEPROM, which only slave. McBSP master, generates required control signals clocking slave.
Configuration
McBSP master interface, must configure CLKX pins serial port outputs only. CLKX generated either C6000 clock external clock source input CLKS pin. mode, system clock other clock source drive CLKS present. clock divide down programmed application needs.
C6000 McBSP master CLKX SPI-compliant slave MOSI MISO HOLD
Figure McBSP Master Interface Slave Device signal connectivity shown Figure connecting Atmel serial CMOS EEPROM AT25 series which maximum clock rate range from This slave device organized 1k/2k/4k/8k 8-bit data only supports modes shown Figure Mode supports simultaneous transmission reception utilizing signals that correspond transmitter. McBSP simultaneously receive data since CLKR signals driven CLKX signals (respectively) internally. good practice, CLKR should programmed inputs.
TMS320C6000 McBSP Interface
SPRA487B
McBSP Initialization
various McBSP control registers shown Figure through Figure have initialized operation. serial port initialization procedure mode follows: McBSP reset state, XRST RRST SPCR. Program McBSP configuration registers XCR, RCR, SRGR, PCR, SPCR parameters required. Write desired value into CLKSTP bit-fields SPCR. Figure shows various CLKSTP modes that supported McBSP. GRST SPCR sample rate generator reset. Wait clocks McBSP reinitialize. Either should followed. This step should performed used service McBSP. XRST RRST enable serial port. Note that value written SPCR this time should have only reset bits changed remaining bit-fields should have same value Step above. used perform data transfers, should first initialized with appropriate read/write syncs, src/dst addresses, their update modes, transfer complete interrupt, other feature suitable application. Lastly, START bit. START state waits synchronization events occur. Then, pull McBSP reset. details initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Applications (SPRA529). enhanced (EDMA) used perform data transfers, channels associated McBSP transmit receive synchronization events should first configured with appropriate priority levels, element size, src/dst addresses, address update modes, transfer complete code, transfer complete interrupt enable, source destination dimensions, other feature suitable application PaRAM parameter fields. events latched event register (ER), even events disabled. Enabling corresponding event event enable register (EER) starts data transfer setting this `1'. Then, pull McBSP reset. details EDMA initialization servicing McBSP, refer TMS320C6000 McBSP Initialization (SPRA488) TMS320C6000 Enhanced DMA: Example Applications (SPRA636).
RPHASE reserved RFRLEN1 RFRLEN2 RWDLEN1 RWDLEN2 reserved RCOMPAND RFIG RDATDLY
Figure Receive Control Register (RCR Master)
TMS320C6000 McBSP Interface
SPRA487B
XPHASE reserved xFRLEN1 xFRLEN2 xWDLEN1 XWDLEN2 reserved XCOMPAND xFIG xDATDLY
Figure Transmit Control Register (XCR Master)
GSYNC CLKSP CLKSM FSGM FPER
FWID
CLKGDV 0x5F
Figure Sample Rate Generator Register (SRGR Master)
reserved 0x0000
reserved
XIOEN
RIOEN
FSXM
FSRM
CLKXM
CLKRM
reserved
CLKS_STAT
DX_STAT
DR_STAT
FSXP
FSRP
CLKXP
CLKRP
Figure Control Register (PCR Master)
0x00 FRST GRST XSYNCERR XEMPTY XRDY XRST
XIN0
reserved
reserved
reserved
RIN0
RSYNCERR
RFULL
RRDY
RRST
RJUST
CLKSTP
Figure Serial Port Control Register (SPCR Master)
TMS320C6000 McBSP Interface
SPRA487B
Table McBSP Register Values Clock
Register SRGR Value 0x00010000 0x00010000 0x2000005F Description Single phase, 8-bit element frame, bit-clock delay Single phase, 8-bit element frame, bit-clock delay Serial clock CLKX generated internal clock (CLKSM internal clock source clock C620x/C670x, CPU/2 clock C621x/C671x CPU/4 clock C64x. Frame sync generated DXR-to-XSR transfer (FSGM Clock divide down clock generate 2.08 shift clock (CLKGDV 0x5F). CLKGCV should adjusted accordingly other internal clock source rate. active-low (FSXP output (FSXM active-low (FSRP input (FSRM CLKX output (CLKXM starts with rising edge (CLKXP CLKSTP 11b. Since CLKXP=0, this refers data transmitted rising edge received falling edge CLKX master. This parameter changed application needs.
0x00000A0C
SPCR[12:10]
example code Appendix initializes McBSP0 correct order SPI-mode communication between McBSP serial EEPROM.
CLKX (CLKSTP=10b, CLKXP=0) CLKX (CLKSTP=11b, CLKXP=0) CLKX (CLKSTP=10b, CLKXP=1) CLKX (CLKSTP=11b, CLKXP=1) D(R/X) FS(R/X)
Figure Clock Stop Mode Options
Timing Analysis
mode (0,0) corresponds McBSP mode with CLKSTP CLKXP master (McBSP) shifts data falling edge CLKX slave (SPI ROM) samples receive data rising edge CLKX. slave transmits/shifts data falling edge CLKX master samples receive data rising edge CLKX.
TMS320C6000 McBSP Interface
SPRA487B CLKX Bit(n-1) Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-2)
(n-3)
(n-4)
Figure C6000 Timing, CLKSTP 11b, CLKXP timing diagram CLKSTP=11b, CLKXP=0 shown Figure corresponding values timing requirements switching characteristics 2.1MHz operation shown Table values derived from formula/numbers available TMS320C6201 datasheet. timing different C6000 devices also differ. Please refer specific device data sheet replace values Table timing analysis particular device. Table Timing Numbers McBSP Master Switching Characteristics
th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXH td(FXL-DXV) Parameter Hold time, after CLKX high Delay time, CLKX Delay time, CLKX high valid Disable time, high impedance following last data from CLKX high Delay time, valid =243 =244 UNIT
Timing Requirements
tsu(DRV-CKXL) th(CKXL-DRV) Setup time, valid before CLKX Hold time, valid after CLKX Unit
NOTE: following true above calculations: Since CLKGDV CLKX derived from clock will have duty cycle therefore Period CLKX, (1+CLKGDV) where clock. Hence, shown Table timing numbers McBSP match with that with sufficient timing margins. Note that timings correspond V-5.5 range devices. Therefore voltage translation buffer (for example, SN54LVT16373) will have used between McBSP ROM. buffers will still meet necessary timing requirements/margins.
TMS320C6000 McBSP Interface
SPRA487B
Table Timing Analysis Master Slave Switching Characteristics
Parameter twl(min) tv(max) ;;where twh(min) tho(min) where UNIT
Timing Requirements
Parameter tsu(min) Setup time, data th(min) Hold time, data UNIT
tcss(min) Setup time,
C6201 Switching Characteristics
Parameter td(FXL-CKXL)min td(FXL-DXV)max td(CKXH-DXV)min td(FXL-CKXL)min UNIT
C6201 Timing Requirements
Parameter tsu(DRV-CKXL)min Setup time, data th(CKXL-DRV)min Hold time, data UNIT
applications where McBSP used slave, please ensure that internal clock, CLKG runs least eight times that master clock. Typically, programming CLKGDV using clock (CLKSM (when McBSP slave) should suffice since clocks very slow.
TMS320C6000 McBSP Interface
SPRA487B
Appendix
Proprietary Information 02/22/01 spi3_dma.c Tests CLKSTP mode where CLKSTP=11b CLKXP=0. McBSP0 master. other SPI-compliant device slave. This sample code transmits serial data from McBSP ROM, interrupts inform completion data transmit then transmits data from back McBSP again interrupts inform completion data receive. data received/transmitted (initiated) using either EDMA depending type device used. transfer size determined xfer_size variable, buffer size (larger equal xfer_size) determined BUFFER_SIZE variable. Default values respectively this sample code. case transfer, vecs.asm assembly code file used hookup c_int11() c_int09() ISRs corresponding interrupts. Channel hooked interrupt data receive, channel hookep interrupt data transmit, controller individual interrupts each channel. EDMA controller, however, generates single interrupt (EDMA_INT) behalf channels (C621x/C671x) channels (C64x). various control registers fields facilitate EDMA interrupt generation. CPU_INT8 responsible EDMA channels vecs.asm assembly file hooks c_int8 interrupt program based 2.0. Please refer TMS320C6000 Chip Support Library User's Guide further information. Chip definition, change this accordingly #define CHIP_6203 Include files #include <c6x.h> #include <csl.h> #include <csl_dma.h> #include <csl_edma.h> #include <csl_irq.h> #include <csl_mcbsp.h>
library DMA_SUPPORT EDMA_SUPPORT IRQ_SUPPORT MCBSP_SUPPORT
Define constants #define FALSE #define TRUE #define DMA_SPI #define XFER_SIZE #define XFER_TYPE DMA_SPI #define BUFFER_SIZE
TMS320C6000 McBSP Interface
SPRA487B
Global variables used interrupt ISRs volatile recv0_done FALSE; volatile xmit0_done FALSE; Declare objects MCBSP_Handle hMcbsp0; (DMA_SUPPORT) DMA_Handle hDma1; DMA_Handle hDma2; #endif (EDMA_SUPPORT) EDMA_Handle hEdma1; EDMA_Handle hEdma2; EDMA_Handle hEdmadummy; #endif Handles McBSP
Handles
Handles EDMA
External functions function prototypes void init_mcbsp0_master(void); void set_interrupts_dma(void); void set_interrupts_edma(void); Function prototypes
Include vector table call ISRs hookup extern void vectors(); main() void main(void) static xfer_type; static xfer_size; static static static static Uint32 Uint32 Uint32 Uint32
Declaration local variables
dmaInbuff[BUFFER_SIZE]; buffer supporting devices dmaOutbuff[BUFFER_SIZE]; edmaInbuff[BUFFER_SIZE]; buffer EDMA supporting devices edmaOutbuff[BUFFER_SIZE];
IRQ_setVecs(vectors); point vector table xfer_type XFER_TYPE; xfer_size XFER_SIZE;
TMS320C6000 McBSP Interface
SPRA487B
initialize library CSL_init(); init_mcbsp0_master(); Enable sample rate generator MCBSP_enableSrgr(hMcbsp0); switch (xfer_type) case DMA_SPI: (DMA_SUPPORT) DMA_reset(INV); #endif supporting devices reset channels GRST=1 Handle SRGR
(EDMA_SUPPORT) EDMA_clearPram(0x00000000); set_interrupts_edma(); #endif
EDMA supporting devices Clear PaRAM EDMA
channels config structures (DMA_SUPPORT) supporting devices Channel receives data hDma1 DMA_open(DMA_CHA1, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma1, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE, DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority DMA_PRICTL_WSYNC_NONE, DMA_PRICTL_RSYNC_REVT0, synchronization event REVT0=01101 DMA_PRICTL_INDEX_NA, DMA_PRICTL_CNTRLD_NA, DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_INC, Increment destination element size DMA_PRICTL_SRCDIR_NONE, DMA_PRICTL_START_STOP DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only available 6202 6203 devices DMA_SECCTL_RSPOL_NA, only available 6202 6203 devices DMA_SECCTL_FSIG_NA, only available 6202 6203 devices DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_NOTHING,
TMS320C6000 McBSP Interface
SPRA487B
DMA_SECCTL_WSYNCSTAT_CLEAR, DMA_SECCTL_RSYNCCLR_NOTHING, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, DMA_SECCTL_FRAMEIE_DISABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR DRR)), DMA_DST_RMK((Uint32)dmaInbuff), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(xfer_size) Channel transmits data hDma2 DMA_open(DMA_CHA2, DMA_OPEN_RESET); Handle channel DMA_configArgs(hDma2, DMA_PRICTL_RMK( DMA_PRICTL_DSTRLD_NONE, DMA_PRICTL_SRCRLD_NONE, DMA_PRICTL_EMOD_NOHALT, DMA_PRICTL_FS_DISABLE, DMA_PRICTL_TCINT_ENABLE, TCINT DMA_PRICTL_PRI_DMA, high priority DMA_PRICTL_WSYNC_XEVT0, synchronization event XEVT0=01100 DMA_PRICTL_RSYNC_NONE, DMA_PRICTL_INDEX_NA, DMA_PRICTL_CNTRLD_NA, DMA_PRICTL_SPLIT_DISABLE, DMA_PRICTL_ESIZE_32BIT, Element size bits DMA_PRICTL_DSTDIR_NONE, DMA_PRICTL_SRCDIR_INC, Increment source element size DMA_PRICTL_START_STOP DMA_SECCTL_RMK( DMA_SECCTL_WSPOL_NA, only available 6202 6203 devices DMA_SECCTL_RSPOL_NA, only available 6202 6203 devices DMA_SECCTL_FSIG_NA, only available 6202 6203 devices DMA_SECCTL_DMACEN_LOW, DMA_SECCTL_WSYNCCLR_NOTHING, DMA_SECCTL_WSYNCSTAT_CLEAR,
TMS320C6000 McBSP Interface
SPRA487B
DMA_SECCTL_RSYNCCLR_NOTHING, DMA_SECCTL_RSYNCSTAT_CLEAR, DMA_SECCTL_WDROPIE_DISABLE, DMA_SECCTL_WDROPCOND_CLEAR, DMA_SECCTL_RDROPIE_DISABLE, DMA_SECCTL_RDROPCOND_CLEAR, DMA_SECCTL_BLOCKIE_ENABLE, BLOCK IE=1 enables channel DMA_SECCTL_BLOCKCOND_CLEAR, DMA_SECCTL_LASTIE_DISABLE, DMA_SECCTL_LASTCOND_CLEAR, DMA_SECCTL_FRAMEIE_DISABLE, DMA_SECCTL_FRAMECOND_CLEAR, DMA_SECCTL_SXIE_DISABLE, DMA_SECCTL_SXCOND_CLEAR DXR)), DMA_XFRCNT_RMK( DMA_XFRCNT_FRMCNT_DEFAULT, DMA_XFRCNT_ELECNT_OF(xfer_size) set_interrupts_dma(); DMA_start(hDma1); DMA_start(hDma2); #endif initialize interrupts enable interupts after channels opened DMA_OPEN_RESET clears disables channel interrupt once specified clears corresponding interrupt bits IER. This applcable EDMA channel open case Start channels
supporting devices
EDMA channels config structures (EDMA_SUPPORT) EDMA supporting devices
hEdma1 EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma1, EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, Destination increment element size EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(13), TCCINT 0xD, REVT0
TMS320C6000 McBSP Interface
SPRA487B
EDMA_OPT_LINK_YES, Enable linking NULL table*/ EDMA_OPT_FS_NO DRR)), /*src DRR0 EDMA_CNT_RMK(0,xfer_size), count equal xfer_size addr edmaInbuff EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdma2 EDMA_open(EDMA_CHA_XEVT0, EDMA_OPEN_RESET); EDMA_configArgs(hEdma2, EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, High priority EDMA EDMA_OPT_ESIZE_32BIT, Element size bits EDMA_OPT_2DS_NO, EDMA_OPT_SUM_INC, Source increment element size EDMA_OPT_2DD_NO, EDMA_OPT_DUM_NONE, EDMA_OPT_TCINT_YES, Enable Transfer Complete Interrupt EDMA_OPT_TCC_OF(12), TCCINT 0xC, XEVT0 EDMA_OPT_LINK_YES, Enable linking NULL table*/ EDMA_OPT_FS_NO /*src edmaOutbuff EDMA_CNT_RMK(0,xfer_size), count equal xfer_size DXR)), addr DXR0 EDMA_IDX_RMK(0,0), EDMA_RLD_RMK(0,0) hEdmadummy EDMA_allocTable(-1); Dynamically allocates PaRAM table EDMA_configArgs(hEdmadummy, Dummy Terminating Table PaRAM 0x00000000, Terminate EDMA transfers linking 0x00000000, this NULL table 0x00000000, 0x00000000, 0x00000000, 0x00000000 EDMA_link(hEdma1, hEdmadummy); Link terminating event EDMA event EDMA_link(hEdma2, hEdmadummy); EDMA_enableChannel(hEdma1); EDMA_enableChannel(hEdma2); #endif Enable EDMA channels
EDMA supporting devices
TMS320C6000 McBSP Interface
SPRA487B
MCBSP_enableRcv(hMcbsp0); Enable McBSP channel MCBSP_enableXmt(hMcbsp0); McBSP port transmitter/receiver flag interrupt when transfer/receive done (DMA_SUPPORT) while (!xmit0_done !recv0_done); #endif flag interrupt when EDMA transfer/receive done Transfer completion interrupt flag when (EDMA_SUPPORT) while (!xmit0_done !recv0_done); #endif MCBSP_close(hMcbsp0); (DMA_SUPPORT) DMA_close(hDma1); DMA_close(hDma2); #endif close McBSP port close channels
(EDMA_SUPPPORT) EDMA_close(hEdma1); close EDMA channels EDMA_close(hEdma2); EDMA_close(hEdmadummy); #endif main init_mcbsp0_master() MCBSP Config structure Setup MCBSP_0 master void init_mcbsp0_master(void) MCBSP_Config mcbspCfg0 mode, CLKSTP CLKXP Clock starts with (EDMA_SUPPORT) rising edge with delay. MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_YES, MCBSP_SPCR_GRST_YES, MCBSP_SPCR_XINTM_XRDY, MCBSP_SPCR_XSYNCERR_NO, MCBSP_SPCR_XRST_YES, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_DELAY, CLKSTP=11b with CLKXP=0, clock starts with MCBSP_SPCR_DXENA_OFF, rising edge with delay MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_YES #endif
TMS320C6000 McBSP Interface
SPRA487B
(DMA_SUPPORT) MCBSP_SPCR_RMK( MCBSP_SPCR_FRST_YES, MCBSP_SPCR_GRST_YES, MCBSP_SPCR_XINTM_XRDY, MCBSP_SPCR_XSYNCERR_NO, MCBSP_SPCR_XRST_YES, MCBSP_SPCR_DLB_OFF, MCBSP_SPCR_RJUST_RZF, MCBSP_SPCR_CLKSTP_DELAY, MCBSP_SPCR_RINTM_RRDY, MCBSP_SPCR_RSYNCERR_NO, MCBSP_SPCR_RRST_YES #endif (EDMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_NO, MCBSP_RCR_RDATDLY_DEFAULT, MCBSP_RCR_RPHASE2_DEFAULT, MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_32BIT, MCBSP_RCR_RWDREVRS_DISABLE #endif (DMA_SUPPORT) MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, MCBSP_RCR_RFRLEN2_DEFAULT, MCBSP_RCR_RWDLEN2_DEFAULT, MCBSP_RCR_RCOMPAND_DEFAULT, MCBSP_RCR_RFIG_NO, MCBSP_RCR_RDATDLY_DEFAULT, MCBSP_RCR_RFRLEN1_DEFAULT, MCBSP_RCR_RWDLEN1_32BIT #endif (EDMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DEFAULT, MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, MCBSP_XCR_XPHASE2_DEFAULT, MCBSP_XCR_XFRLEN1_DEFAULT,
CLKSTP=11b with CLKXP=0, clock starts with rising edge with delay
receive element length phase bits
receive element length phase bits
data delay
TMS320C6000 McBSP Interface
SPRA487B
MCBSP_XCR_XWDLEN1_32BIT, transmit element phase bits MCBSP_XCR_XWDREVRS_DISABLE #endif (DMA_SUPPORT) MCBSP_XCR_RMK( MCBSP_XCR_XPHASE_DEFAULT, MCBSP_XCR_XFRLEN2_DEFAULT, MCBSP_XCR_XWDLEN2_DEFAULT, MCBSP_XCR_XCOMPAND_DEFAULT, MCBSP_XCR_XFIG_DEFAULT, MCBSP_XCR_XDATDLY_1BIT, data delay MCBSP_XCR_XFRLEN1_DEFAULT, MCBSP_XCR_XWDLEN1_32BIT transmit element phase bits #endif MCBSP_SRGR_RMK( MCBSP_SRGR_GSYNC_FREE, MCBSP_SRGR_CLKSP_RISING, MCBSP_SRGR_CLKSM_INTERNAL, SRGR clock mode from internal source MCBSP_SRGR_FSGM_DEFAULT, MCBSP_SRGR_FPER_DEFAULT, MCBSP_SRGR_FWID_DEFAULT, MCBSP_SRGR_CLKGDV_OF(0x5F) divide clock factor MCBSP_MCR_RMK( MCBSP_MCR_XPBBLK_SF1, MCBSP_MCR_XPABLK_SF0, MCBSP_MCR_XMCM_DEFAULT, MCBSP_MCR_RPBBLK_SF1, MCBSP_MCR_RPABLK_SF0, MCBSP_MCR_RMCM_DEFAULT MCBSP_RCER_RMK( MCBSP_RCER_RCEB_DEFAULT, MCBSP_RCER_RCEA_DEFAULT MCBSP_XCER_RMK( MCBSP_XCER_XCEB_DEFAULT, MCBSP_XCER_XCEA_DEFAULT MCBSP_PCR_RMK( MCBSP_PCR_XIOEN_SP, MCBSP_PCR_RIOEN_SP, MCBSP_PCR_FSXM_INTERNAL, frame sync generation MCBSP_PCR_FSRM_EXTERNAL, MCBSP_PCR_CLKXM_OUTPUT, tans. clock mode from internal SRGR MCBSP_PCR_CLKRM_INPUT, MCBSP_PCR_CLKSSTAT_0, MCBSP_PCR_DXSTAT_0, MCBSP_PCR_FSXP_ACTIVELOW, active trans. frame sync. polarity MCBSP_PCR_FSRP_ACTIVEHIGH, MCBSP_PCR_CLKXP_RISING, trans. pol. from rising edge CLKX
TMS320C6000 McBSP Interface
SPRA487B
MCBSP_PCR_CLKRP_FALLING hMcbsp0 MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); McBSP port MCBSP_config(hMcbsp0, &mcbspCfg0); set_interrupts_dma() (DMA_SUPPORT) void interrupts set_interrupts_dma(void) device supports IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_disable(IRQ_EVT_DMAINT2); IRQ_disable(IRQ_EVT_DMAINT1); INT11 INT9 IRQ_clear(IRQ_EVT_DMAINT2); IRQ_clear(IRQ_EVT_DMAINT1); IRQ_enable(IRQ_EVT_DMAINT2); IRQ_enable(IRQ_EVT_DMAINT1); return; #endif set_interrupts_edma() (EDMA_SUPPORT) void set_interrupts_edma(void) IRQ_nmiEnable(); IRQ_globalEnable(); IRQ_reset(IRQ_EVT_EDMAINT); IRQ_disable(IRQ_EVT_EDMAINT); EDMA_intDisable(12); EDMA_intDisable(13); IRQ_clear(IRQ_EVT_EDMAINT); EDMA_intClear(12); EDMA_intClear(13); IRQ_enable(IRQ_EVT_EDMAINT); EDMA_intEnable(12); EDMA_intEnable(13); return; #endif
interrupts device supports EDMA
McBSP transmit event XEVT0 McBSP receive event REVT0
TMS320C6000 McBSP Interface
SPRA487B
DATA TRANSFER COMPLETION ISRs interrupt void vecs.asm hooks this c_int11(void) xmit0_done TRUE; return; interrupt void c_int09(void) recv0_done TRUE; return; vecs.asm hooks this
interrupt void vecs.asm hooks this c_int08(void) EDMA (EDMA_SUPPORT) (EDMA_intTest(12)) xmit0_done TRUE; EDMA_intClear(12); clear CIPR future interrupts recognized else (EDMA_intTest(13)) recv0_done TRUE; EDMA_intClear(13); clear CIPR future interrupts recognized #endif return; /*-----------------------End
Copyright 2000 Texas Instruments Incorporated. Rights Reserved FILENAME. vecs.asm DATE CREATED. 02/22/2001 Global symbols defined here exported this file .global _vectors .global _vector0
TMS320C6000 McBSP Interface
SPRA487B
.global .global .global .global .global .global .global .global .global .global .global .global .global .global .global
_vector1 _vector2 _vector3 _vector4 _vector5 _vector6 _vector7 _c_int08 _c_int09 _vector10 _c_int11 _vector12 _vector13 _vector14 _vector15
Hookup c_int08 main() EDMA Hookup c_int09 main() Hookup c_int11 main()
Global symbols referenced this file defined somewhere else. Remember that your interrupt service routines need referenced here. .ref _c_int00 This mcros that instantiates entry inetrrupt service table. VEC_ENTRY .macro addr B0,*--B15 MVKL addr,B0 MVKH addr,B0 *B15++,B0 .endm
This dummy interrupt service routine used initialize IST. _vec_dummy: This actual interrupt service table (IST). properly aligned located subsection .text:vecs. This means don't explicitly specify this section your linker command file, will default link into .text section. Remember ISTP register point this table.
TMS320C6000 McBSP Interface
SPRA487B
.sect ".text:vecs" .align 1024 _vectors: _vector0: _vector1: _vector2: _vector3: _vector4: _vector5: _vector6: _vector7: _vector8: _vector9: _vector10: _vector11: _vector12: _vector13: _vector14: _vector15:
VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY VEC_ENTRY
_vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _vec_dummy _c_int08 _c_int09 _vec_dummy _c_int11 _vec_dummy _vec_dummy _vec_dummy _vec_dummy
Hookup c_int08 main() EDMA Hookup c_int09 main() Hookup c_int11 main()
/*--------------------------End
TMS320C6000 McBSP Interface
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