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Interfacing TMS320C6201 Using AMCC S5933 Controller
Brian Carlson Enterprises, Inc.
Abstract
This application report describes architecture capabilities AMCC S5933 controller interfaced Texas Instruments TMS320C6201 digital signal processor (DSP). DSP's host port interface (HPI) target external memory interface (EMIF) used support mastering. Details signals logic required implement both slave master interfaces with TMS320C6201 presented. Suggestions provided improve design achieve greater data throughput.
Contents
Introduction S5933 Controller TMS320C6201 DSP.6 Host Port Interface (HPI).7 External Memory Interface (EMIF) References.26
Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure TMS320C6201 Interface S5933 Controller S5933 Controller Block Diagram Data Paths S5933 Controller/TMS320C6201 Interface Interface S5933 Controller Register Read Control Timing.13 Register Write Control Timing EMIF Interface S5933 Controller EMIF Write S5933 Add-On Register EMIF Read From S5933 Add-on FIFO
Digital Signal Processing Solutions
March 1999
Tables
Table Table Table Table Table Table Table Table Table Table S5933 Pass-Thru Indicator Signals S5933 Pass-Thru Control Signals Control Signals Status Signals Burst End-of-Transfer Actions S5933 Add-On Registers S5933 Add-On Register Access Signals S5933 FIFO Access Signals Asynchronous EMIF Signals External Interrupt Signals
Introduction
TMS320C6201 interfaced off-the-shelf controller gain access adapter card embedded applications. AMCC S5933 controller provides flexible interface that compliant with Local Specification Revision 2.1. S5933 controller manages transactions provides general-purpose, add-on interface. interface used transfer bi-directional data between host TMS320C6201's EMIF. S5933 interfaces directly 5-V, 32-bit running MHz, supporting peak bandwidth Mbytes/s. internal registers FIFOs enable operate asynchronously. S5933 supports both master slave data transfers from TMS320C6201 memory space. master transfers enable transfer data from host's other device memory space. slave transfers enable host another device transfer data from memory space. master slave transfers application-dependent. both transfer types useful specific application. Figure illustrates TMS320C6201 interfaces with AMCC S5933 controller. S5933 directly interfaces handles transactions. serial EEPROM provides non-volatile storage configuration information that automatically downloaded into S5933 power-up. Glue logic, which implemented complex programmable logic device (CPLD), controls data transfers interrupts between S5933 DSP. 3.3-V CPLD with 5-V-tolerable inputs required interface controller 3.3-V DSP. Voltage translation buffers interface S5933 signals DSP's dedicated data bus. transceivers provide voltage translation control transmissions between S5933 data buses.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure TMS320C6201 Interface S5933 Controller
AT24C08A SERIAL EEPROM
NVRAM Interface
EMIF Data
TRANSCEIVERS
DQ[31:0]
ED[31:0]
VOLTAGE TRANSLATION
HD[15:0]
AD[31:0] C/BE[3:0]#
HCS# HDS1# HR/W# HBE[1:0]# HHWIL HCNTL[1:0] HRDY# HINT#
Add-on Interface
FRAME# IRDY# TRDY# STOP# LOCK# PTATN# PTBURST# PTNUM[1:0] PTBE[3:0]# PTWR PTADR# PTRDY# BE[3:0]# IDSEL DEVSEL# REQ# GNT# PERR# SERR# SELECT# ADR[6:2] WRFULL RDEMPTY WRFIFO# RDFIFO#
EMIF Address/Control
EA[21.16,6.2]
GLUE LOGIC (PLD)
CE1# BE[3:0] ARE# AWE# ARDY#
EXT_INT4 INTA# IRQ# EA0/EMB0 EA8/EMBCLK RST# BPCLK SYSRST# RESET# EXT_INT5 EXT_INT6
S5933 CONTROLLER
TMS320C6201
S5933 Controller
S5933 controller off-the-shelf device that provides Revision 2.1-compliant interface. S5933 supports several modes operation that allow generalpurpose, add-on interface used with different devices, such TMS320C6201 DSP. S5933 provides various ways communicate between DSP, including bi-directional FIFO interface, mailbox registers, pass-thru mode that enables DSP's accessed bus. S5933 controller three main interfaces, including bus, add-on bus, non-volatile memory interface. also three sets registers, including configuration, operation, add-on operation registers. Figure shows block diagram S5933 controller's architecture interfaces. following paragraphs summarize features interfaces S5933. Refer AMCC S5933 Controller Data Book detailed information.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure S5933 Controller Block Diagram
ddress Latch ass-T ddress
rite ass-T
ailboxes
ecoder
ntrol
uffer uffers Latches
Demux
[8/16
rite
nsfer ters
onfiguration egisters
ontrol
Interru
Interface
S5933 directly connected handle local transactions, including configuration, memory, accesses. S5933 device agent, bridge, designed endpoint within given system. This means that either source destination data transfer rather than intermediate device (bridge) data transfer.
Non-Volatile Memory Interface
system reset, S5933 downloads configuration information from external nonvolatile memory that used support PCI's plug-and-play into configuration registers. This configuration information includes vendor device IDs, revision number, class code, memory space requirements, interrupt usage. host system's operating system uses this information resource allocation card registration. S5933 supports downloading from both byte-wide serial non-volatile memories. serial memory used, then additional capabilities, such external mailbox control, available because only pins required (clock data) interface.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Add-On Interface
S5933 provides general-purpose, 32-bit add-on that allows other devices interface Data transfers from S5933 internal registers accomplished chip select decode conjunction with either read write strobe. addition control status register accesses, add-on used directly access S5933's on-chip FIFOs master transfers access pass-thru address data registers slave transfers.
Configuration Registers
S5933 contains 64-byte configuration space region that required compliance. These registers, which only accessed from host side, contain configuration information, including vendor device revision number, other information, such specific device capabilities amount memory required operation. configuration registers intended during system initialization catastrophic error handling.
FIFOs
S5933 FIFOs that each bits wide words deep transferring data both directions between add-on bus. FIFOs support mastering where S5933 directly controls transfer data instead host. Each FIFO associated address pointer transfer count registers support block transfers. read write FIFOs directly accessed using S5933's RDFIFO WRFIFO strobe pins addressed through their add-on operations register addresses. FIFO flag pins indicate when read FIFO empty write FIFO full available external logic control data transfers with FIFOs. status FIFO flags also available reading operation registers.
Mailbox Registers
S5933 contains eight 32-bit mailbox registers. Four mailboxes used transfer data from add-on bus, four mailboxes used transfer data from add-on bus. Host software detect mailbox empty/full conditions polling register being interrupted. mailboxes useful transferring data, command, status information between host DSP.
Operation Registers
S5933 32-bit operation registers, accessible only host side, that support control configuration interface, provide device status, implement add-on interface mailboxes FIFOs. host side also read/write access non-volatile memory operation registers.
Add-On Operation Registers
S5933 32-bit add-on operation registers, accessible only add-on side, that support control configuration interface, provide device status, implement add-on interface mailboxes FIFOs, present demultiplexed address data values associated with pass-thru cycles. add-on side also read/write access non-volatile memory operation registers.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Pass-Thru Operation
S5933 allows cycles executed real-time add-on interface providing simple registered access port bus. Using handshaking protocol with add-on logic, read from write add-on resources. S5933 supports four individual pass-thru regions memory space that defined configuration information stored non-volatile RAM. Each passthru region's memory width individually defined. pass-thru operation used slave transfers where host controls data transfers. pass-thru logic S5933 comprised address register data registers (read/write). Status information necessary define current pass-thru transaction provided add-on interface dedicated S5933 pins. Glue logic required drive add-on interface target device control signals accomplish data transfers. S5933 supports both single burst data transfers pass-thru operation.
TMS320C6201
TMS320C6201 interface S5933 controller EMIF. Since host processor controls data transfers, mapped slave device. Since cannot control data transfers, cannot used mastering. However, S5933 controller mapped into DSP's EMIF support DSP-controlled mastering. DSP's EMIF interfaces with S5933 supports independent data paths that under host control depending needs application. Both data paths used simultaneously time-sliced fashion granted arbiter) some applications support different types data transfers. example, bus-mastering interface EMIF used full-duplex data streams between another processor, while slave interface used another processor send control data receive status data from DSP. ability support independent data paths provides flexibility optimize data flow simplify software support some applications. TMS320C6201 DSP's allows master access complete memory space through simple three-register interface that front dedicated auxiliary channel. auxiliary channel connects DSP's memory space, providing direct access internal external memory memory-mapped peripherals. includes control, address, data registers that support single random accesses DSP's memory space well fast, contiguous block transfers. TMS320C6201 DSP's asynchronous operation EMIF compatible with S5933's add-on interface. S5933's add-on operation registers, including FIFO mailbox registers, mapped into DSP's memory space. busmaster transfers controlled using channels triggered status pins S5933's read write FIFOs direct software control using interrupts polling FIFO flags.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure summarizes various data paths available applications when S5933 controller interfaced TMS320C6201 DSP. S5933 FIFOs typically used support mastering shown also accessed using slave transfers from host. following sections provide detailed descriptions DSP's EMIF interfaces used with S5933 controller slave master transfers.
Figure Data Paths S5933 Controller/TMS320C6201 Interface
S5933 Controller
AILB AILBO FIFO FIFO
S320C6201
INTE RFAC
Host Port Interface (HPI)
TMS320C6201 DSP's interfaced S5933 controller slave transfers, enabling host software read write access memory space. Host software perform both random sequential accesses using HPI's registers, which memory-mapped into host's memory space. Before detailing slave interface implementation, important identify issues involved transferring data between S5933 HPI.
presents 16-bit data interface. S5933 presents 32-bit data interface that configured add-on width bits compatibility with HPI. 32-bit data transfers require successive 16-bit data transfers. S5933 base address regions (BARs) used support explicit register addressing random memory accesses auto-incremented data addressing sequential memory accesses.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Programmable logic required monitor S5933's pass-thru interface provide control signals required transfer data both directions between S5933 HPI. S5933 device requires 3.3-V levels, voltage translation buffers required S5933 add-on data bus.
Because 16-bit interface, 32-bit data transfers must divided into consecutive 16-bit data transfers. This operation supported configuring S5933 32-bit add-on interface associated BARs 16-bit pass-thru regions. 32-bit add-on interface selected grounding floating S5933's MODE pin. 16-bit pass-thru regions selected initializing bits respective definitions NVRAM this configuration S5933's internal 32-bit data have byte lanes steered lower data bits using BE[3:0]# byte enable inputs. This action directly supports requirement pass 32-bit data 16-bit data interface common data signals. Since S5933 device, Texas Instruments SN74CBTD3384 devices used translate 16-bit data 3.3-V DSP. slave interface uses S5933's pass-thru interface, which comprised address register, data registers, several control indicator signals. S5933 monitors data transfers that targeted BARs defined non-volatile memory. case HPI, BARs support random sequential memory space accesses, respectively. When master attempts access either BARs, S5933 asserts pass-thru indicator signals notify programmable logic that pass-thru cycle initiated. programmable logic responds this notification controlling S5933 signals coordinate data transfers. data transfer consists simultaneous register accesses both S5933 HPI. register side read with data presented data (HD[15:0]). register other side written with data. programmable logic asserts ready signal back S5933 indicate when each 32-bit data transfer completed control transfer rate with HPI. Figure shows interface S5933 controller.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure Interface S5933 Controller
S5933 S-THR
ABLE
320C6201
PASS-T
HINE
ycle Identificatio ontro
PASS-T ISTER
Transfer trol
ISTER
PASS-T ISTER
ISTER PIA)
PASS-T ISTER
3.3V
ISTER
74CB TD3384
S5933 Signals
Several S5933 signals required interface controller HPI. These signals provide information about slave data transfers allow add-on logic control transfer data both directions between S5933 HPI. S5933 pass-thru indicator signals identify start type slave data transfer. These signals used programmable logic initiate specific type data transfer with HPI. Table identifies pass-thru indicator signals.
Table S5933 Pass-Thru Indicator Signals
Signal PTATN# PTBURST# PTNUM[1:0] PTBE[3:0]# PTWR Function Indicates that pass-thru access occurring Indicates that pass-thru access burst access Indicates which four pass-thru regions being accessed Indicates which data bytes valid (write) requested (read) Indicates whether access write read
programmable logic state machine must control S5933 pass-thru signals accomplish data transfer. These pass-thru control signals allow state machine request target address data transfer, access pass-thru read write data registers, indicate S5933 when data transfer complete. Table identifies pass-thru control signals.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Table S5933 Pass-Thru Control Signals
Signal PTADR# BE[3:0]# Function When asserted, drives pass-thru address register contents onto add-on data bus. Individual byte enables used during pass-thru register read write operations. During reads, they control output drive each respective byte lane. During writes, they serve enables perform modification their respective byte lanes. Add-on interface select required read write pass-thru registers Add-on write strobe Add-on read strobe Add-on address lines select which 32-bit registers within S5933 desired given read write cycle. (Add-on pass-thru data register 1].) Indicates that current pass-thru transfer been completed add-on
SELECT# ADR[6:2]
PTRDY#
S5933's add-on data provides multiplexed address data information. When PTADR# signal asserted, DQ[3:2] signals indicate target register. DQ[15:0] signals transfer data data bits time. S5933's buffered clock (BPCLK) used programmable logic clock state machine that generates data transfer control signals. This clock behavioral characteristics clock. state machine held reset state whenever S5933's system reset (SYSRST#) output asserted low. This signal buffered form reset.
Signals
signals controlled programmable logic state machine read write registers. These control signals select register being addressed, 16-bit word being accessed, byte lanes that enabled, direction data transfer, timing transfers. Table lists control signals required slave interface. HAS# control signal required because register address multiplexed data bus. HDS2# control signal required because only single data strobe used (HDS1#). These unused control inputs should pulled
Table Control Signals
Signal HCS# HDS1# HR/W# HBE[1:0]# HHWIL HCNTL[1:0] Function Chip select must asserted enable read write transfers Data strobe that indicates when other control signals data valid. Read/write strobe that high reads writes. Indicates which bytes 16-bit word written. Ignored during reads. Halfword identification input that first 16-bit word high second 16-bit word. Access type controls that indicate which internal register being accessed. (00=HPIC, 01=HPIA, 10=HPID with HPIA inc., 11=HPID)
provides status signals that indicate when ready data transfer performed when host interrupt been asserted. Table lists status signals.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Table Status Signals
Signal HRDY# HINT# Function ready data transfer when asserted low. Interrupt signal host
dedicated 16-bit data bus. This parallel, bi-directional, three-state data placed high-impedance state when performing read access.
Programmable Logic Implementation
component slave design programmable logic state machine that monitors S5933's pass-thru interface controls signals transfer data. data transfers initiated master information about transfer provided S5933's pass-thru interface. response this information, state machine generates corresponding pass-thru register accesses required data transfer. state machine clocked buffered clock (BPCLK), runs maximum cycle time). Three control signals directly controlled state machine. HCNTL[1:0] control signals, which select target register, decoded from latched pass-thru address output when PTADR# signal asserted state machine. Since target address latched, HCNTL[1:0] signals remain fixed throughout register access. HR/W# access-type control signal opposite polarity S5933's pass-thru PTWR indicator signal. Therefore, PTWR signal routed through inverter directly generate HR/W# control signal without state machine interaction. other five control signals used (HCS#, HDS1#, HHWIL HBE[1:0]#) directly controlled state machine. following four sections describe implementations slave interface register read, register write, sequential data read sequential data write accesses.
Register Read
master read three registers perform following functions:
Determine selected halfword data transfer order Determine host interrupt status Observe ready flag Read current address (HPIA) register value Read value from memory space pointed HPIA register
When register read, simultaneous S5933 register write required complete transfer. programmable logic state machine performs requested register read strobes into pass-thru data register subsequent transfer over master. programmable logic state machine performs following steps register read. timing diagram shown Figure referenced visual description these steps.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Wait PTATN# PTNUM[1:0], indicating transfer registers' pass-thru region. Assert PTADR# output target address (HPI register indication). Assert S5933 pass-thru control signals prepare write pass-thru data register (SELECT# ADR[6:2]). Deassert PTADR# address phase. Assert pass-thru control signal begin data write phase pass-thru data register. Assert HCS# enable HPI. HHWIL indicate first halfword transfer. Assert HCNTL[1:0] control signals select access cycle. timing diagram Figure shows write HPID register since HCNTL[1:0] Assert HDS1# signal, which causes internal logic latch other control signals (HR/W#, HHWIL, HCNTL[1:0]). Assert BE[1:0]# signals enable write lower bits pass-thru data register. should HRDY# signal high indicate that internal operation progress. When data available read from data register, will assert HRDY# signal low. Wait HRDY# asserted, indicating that data available read. Since asynchronous controller, HRDY# signal should synchronized clock (BPCLK) before being sampled state machine address metastability. synchronization sampling HRDY# signal requires clock cycles. Deassert HDS1# signal first halfword transfer. HHWIL signal high indicate second halfword data transfer. Deassert pass-thru BE[1:0]# signals disable further writes lower bits pass-thru data register. Assert BE[3:2]# signals enable write upper bits pass-thru data register. lower bits value being read clocked into pass-thru data register rising BPCLK edge this step. Assert HDS1# signal latch other control signals begin second halfword read. Note that second halfword always available, HRDY# does have checked. Deassert HDS1# signal second halfword transfer. Deassert pass-thru signal pass-thru data register write cycle. Deassert BE[3:2]# signals disable further writes upper 16-bits pass-thru data register. Assert PTRDY# indicate that data transfer performed. upper bits value being read clocked into pass-thru data register rising BPCLK edge this step. SELECT# ADR[6:2] signals disable add-on interface. Deassert PTRDY# data transfer. Return step handle subsequent data transfers.
Deassert HCS# signal disable access HPI. Deassert pass-thru
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure Register Read Control Timing
Register Write
master write three registers perform following functions:
Select halfword data transfer order. Assert DSPINT interrupt clear HINT host interrupt. Request data fetch under software control. Write memory address address (HPIA) register. Write data into memory space pointed HPIA register.
When register written, simultaneous S5933 register read required access source data complete transfer. programmable logic state machine will perform read pass-thru data register strobe data into data register. When pass-thru data register read, ready signal returned S5933, controller accept more data from master bus. programmable logic state machine performs following steps register write. timing diagram shown Figure referenced visual description these steps.
Wait PTATN# PTNUM[1:0], indicating transfer registers' pass-thru region.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Assert PTADR# output target address (HPI register indication). Assert S5933 pass-thru control signals prepare write pass-thru data register (SELECT# ADR[6:2]). Deassert PTADR# address phase. Assert BE[1:0]# signals enable read from lower bits pass-thru data register. Assert pass-thru control signal begin data read phase from pass-thru data register. Assert HCS# enable HPI. HHWIL indicate first halfword transfer. HBE[1:0]# byte enables corresponding values PTBE[1:0]# first halfword transfer. Assert HCNTL[1:0] control signals select access cycle. timing diagram shows write HPID register since HCNTL[1:0] Assert HDS1# signal which causes internal logic latch other control signals (HR/W#, HHWIL, HCNTL[1:0]). Wait HRDY# asserted, indicating that ready accept another transfer. most cases, HRDY# should asserted immediately, there chance that previous write prefetch read have completed yet. Since asynchronous controller, HRDY# signal should synchronized clock (BPCLK) before being sampled state machine address metastability. This will extra clock delay before state machine respond Deassert HDS1# signal first halfword transfer. HHWIL signal high indicate second halfword data transfer. Deassert pass-thru BE[1:0]# signals disable output lower bits pass-thru data register. Assert BE[3:2]# signals enable output upper bits pass-thru data register. Assert HDS1# signal latch other control signals. Note that second halfword always immediately written, HRDY# does have checked. Deassert HDS1# signal second halfword transfer. HCNTL[1:0] control signals optionally default state When HDS1# brought back high, auxiliary controller initiates write into memory space. HRDY# signal deasserted during this operation. HRDY# signal returns default asserted state. Deassert pass-thru signal pass-thru data register read cycle. Deassert BE[3:2]# signals disable data from upper 16-bits pass-thru data register. Assert PTRDY# indicate that data transfer performed.
Deassert HCS# signal disable access HPI. When HCS# asserted,
Deassert pass-thru SELECT# ADR[6:2] signals disable add-on
interface. Deassert PTRDY# data transfer. Return step handle subsequent data transfers.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure Register Write Control Timing
BPCLK PTATN# PTNUM[1:0] PTBE[3:0]# PTWR PTADR# PTRDY# BE[3:0]# SELECT# ADR[6:2] HCS# HDS# HR/W# HBE[1:0]# HHWIL HCNTL[1:0] HRDY# STEP
Sequential Data Reads
master take advantage HPI's sequential memory access capability efficiently support block read transfers. HPI's address auto-increment feature facilitates reading from sequential memory locations with data prefetching reduce latency subsequent host read requests. this mode operation, address register (HPIA) initialized memory source address block read transfer. When HCNTL[1:0] control signals configured subsequent reads data register (HPID) increment HPIA automatically prefetch data next address anticipation next data read. This capability simplifies data transfer coordination host side because source address only written once data read sequentially thereafter without writes other registers. This allows host software implement efficient block data transfers using tight loops that result efficient data bursts. data bursts increase data throughput because they eliminate repetitive arbitration address phase overhead involved single-word transfers.
Interfacing TMS320C6201 Using AMCC S5933 Controller
separate pass-thru memory region defined S5933 controller's BARs used dedicated, sequential memory accesses. Since data transfers this dedicated memory region targeted HPID register, detailed address information provided multiplexed needed. Therefore, address phase each data transfer this region eliminated, allowing data transferred from immediately. This means that S5933's PTADR# control signal required support block reads. additional benefit using dedicated memory region sequential memory accesses that HCNTL[1:0] control signals forced select HPID with address auto-incrementing accesses. This provides very simple decoding mechanism supporting block transfers. From host software, dedicated memory region block transfers viewed linear circular buffer. point that data transfer must extend past memory region's defined memory space defined configuration NVRAM. Memory accesses beyond this memory space accepted S5933 cause system problems. Therefore, proper operation, important ensure that host memory accesses maintained memory region's address space. control timing sequential data reads same individual register reads with following exceptions:
pass-thru address phase eliminated, steps involving assertion deassertion PTADR# control signal required. HCNTL[1:0] control signals forced accesses dedicated memory region, rather than being decoded from latched pass-thru address register value. each 32-bit data transfer, PTATN# PTBURST# indicator signals should sampled determine burst data transfer with subsequent data being requested appropriate action should taken. Table summarizes four combinations these signal states corresponding actions take.
Table Burst End-of-Transfer Actions
PTATN# PTBURST# Status burst. S5933 ready next read more read left burst burst, S5933 ready next read burst Action Read HPID data from next memory address.
Read HPID last data burst from next memory address. Wait PTATN# asserted before reading HPID data from next memory address. Return idle state awaiting next pass-thru transfer indicated PTATN# being asserted.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Sequential Data Writes
master also take advantage HPI's sequential memory access capability efficiently support block write transfers. HPI's address auto-increment feature facilitates writing sequential memory locations after initializing HPIA register with block's destination address memory space. When HCNTL[1:0] control signals configured subsequent writes data register (HPID) will increment HPIA automatically. same dedicated pass-thru memory region used sequential data reads should used data writes. state machine should check PTWR indicator signal determine whether read write access being made HPID register. control timing sequential data writes same individual register writes, with same exceptions identified sequential data reads. pass-thru PTATN# PTBURST# indicator signals must similarly sampled each data word transfer determine corresponding action take, summarized Table
Slave Performance
required transfer protocol defines maximum transfer rate between host transfer 16-bit words, 30-ns state machine clock period, response time HPI's auxiliary controller. 16-bit wide asynchronous interface, overhead required interface 32-bit wide synchronous interface bus. Because state machine must synchronous 33-MHz clock, there minimum between control signal transitions. response (HRDY#) time typically varies between clocks longer depending conflicts. Assuming that 32-bit data transfer requires states plus clocks slave throughput rate about Mbytes/s achieved.
External Memory Interface (EMIF)
TMS320C6201 DSP's asynchronous EMIF interfaced S5933 controller access S5933's add-on registers, including control, status, mailbox, FIFO registers. access add-on FIFO registers enables support mastering where resource controls data transfers rather than host. Before detailing EMIF interface implementation, important identify issues involved.
Both DSP's EMIF S5933 add-on data buses bits wide. Programmable logic required decode DSP's EMIF control address signals, enable data transceivers, generate S5933 control signals add-on accesses. Programmable logic required monitor S5933 FIFO flags generate interrupts mastering data transfer control. S5933 generates interrupt indicate defined mailbox states, endof-transfers, error conditions.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Because S5933 device requires 3.3-V levels, voltage translation buffers required S5933 add-on data bus.
Because S5933 add-on EMIF data buses both bits, data transfers involve single 32-bit data transfers. S5933 mapped into DSP's memory spaces (CE0-CE3) that corresponding memory space control register 32bit asynchronous memory. Figure shows interface between EMIF S5933 controller.
Figure EMIF Interface S5933 Controller
S5933 LLER
DECODERS NTRO
ABLE
NTRO
S320C6201
ADDR CONTROL/STATUS
TRANSFER NTRO
NTRO
DECODE
NTRO
DATA
SN74LV TH162245
S5933 add-on interface presents operation registers mapped 32-bit word boundaries. these registers used pass-thru support, only actually used EMIF. add-on operation registers accessed asserting add-on chip select (SELECT#) address pins conjunction with either read (RD#) write (WR#) control strobe. Access bi-directional FIFOs also achieved using dedicated RDFIFO# WRFIFO# pins. Table lists add-on operation registers that provide communication interface between S5933.
Table S5933 Add-On Registers
Address Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Register Name AIMB1 AIMB2 AIMB3 AIMB4 AOMB1 AOMB2 AOMB3 Description Add-on Incoming Mailbox Register Add-on Incoming Mailbox Register Add-on Incoming Mailbox Register Add-on Incoming Mailbox Register Add-on Outgoing Mailbox Register Add-on Outgoing Mailbox Register Add-on Outgoing Mailbox Register Access Type Read Only Read Only Read Only Read Only Read/Write Read/Write Read/Write
Interfacing TMS320C6201 Using AMCC S5933 Controller
Address Offset 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x58 0x5C Register Name AOMB4 AFIFO MWAR APTA APTD MRAR AMBEF AINT AGCSTS MWTC MRTC Description Add-on Outgoing Mailbox Register Add-on FIFO Port Master Write Address Register Add-on Pass-Thru Address Register Add-on Pass-Thru Data Register Buss Master Read Address Register Add-on Mailbox Empty/Full Status Add-on Interrupt Control Register Add-on General Control/Status Register Master Write Transfer Count Master Read Transfer Count Access Type Read/Write Read/Write Read/Write Read Only Read/Write Read/Write Read Only Read/Write Read/Write Read/Write Read/Write
Programmable logic performs memory decoding, S5933 access arbitration, direct control S5933 add-on interface, interrupt generation. Logic determines when attempting access S5933 add-on decoding EMIF address control signals. master simultaneously access DSP's interface slave, add-on interface available EMIF. Arbitration logic must included allow master access S5933 add-on time. add-on available DSP, pending asynchronous access held asserting EMIF ARDY signal. When EMIF granted access add-on bus, data transceivers, such SN74LVTH162245, enabled connect EMIF add-on data buses provide required voltage translation. state controls S5933 chip select, address, read/write strobes achieve data transfer well DSP's ARDY signal indicate data transfer. External interrupts support interface between S5933 TMS320C6201. interrupt dedicated general controller notifications, such mailbox status, transfer status, error conditions. second interrupt notifies when data written S5933's write FIFO. third interrupt notifies when data read from S5933's read FIFO. FIFO interrupts used directly control synchronization controllers move data background.
S5933 Signals
Several S5933 signals required interface controller EMIF access S5933's add-on registers bi-directional FIFOs. S5933 add-on registers accessed asserting device's chip select, selecting register offset desired byte enables, strobing data with either write read strobe. Table lists signals required provide access S5933's add-on registers.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Table S5933 Add-On Register Access Signals
Signal SELECT# ADR[6:2] BE[3:0]# Function Add-on interface chip select Add-on address lines select which 32-bit registers within S5933 desired given read write cycle Add-on write strobe Add-on read strobe Individual byte enables used during register read/write accesses. During reads, they control output drive each respective byte lane. During writes, they serve enables perform modification their respective byte lanes.
S5933 provides dedicated signals that indicate status read write FIFOs allow direct access FIFOs without requiring chip select read/write strobes. Table lists signals related FIFOs.
Table S5933 FIFO Access Signals
Signal WRFULL RDEMPTY WRFIFO# RDFIFO# Function Write FIFO full when asserted. Read FIFO empty when asserted. Automatically writes add-on data information into FIFO Automatically drives FIFO data onto add-on data
S5933 also provides IRQ# signal that source general controller interrupt DSP. S5933's buffered clock (BPCLK) used programmable logic clock that state machine that generates data transfer control signals. state machine held reset state whenever S5933's system reset (SYSRST#) output asserted low.
EMIF Signals
S5933 accessed DSP, other asynchronous devices. memorymapped certain memory space configured 32-bit asynchronous memory accesses. (The memory space used this application report.) external address (EA) signals decode memory accesses S5933 EMIF request S5933's add-on bus. upper address bits EA[21:16] used this application report determine when S5933 being accessed lower address bits EA[6:2] used access specific add-on registers. Table lists DSP's asynchronous EMIF signals used interface S5933 controller.
Interfacing TMS320C6201 Using AMCC S5933 Controller
Table Asynchronous EMIF Signals
Signal ED[31:0] EA[21:16] EA[6:2] CE1# BE[3:0]# ARE# AWE# ARDY Function External data External address signals used decode accesses S5933 controller External address signals used access S5933 add-on registers Indicates when selected external memory space (configured 32-bit asynchronous accesses) being accessed Individual byte lane enables indicating which bytes selected both read write accesses Asynchronous read strobe Asynchronous write strobe Asynchronous ready input used assert wait states needed
Three external interrupts support interface S5933. used general notifications other synchronize transfer mastering data. Table lists external interrupts used this application report.
Table External Interrupt Signals
Signal EXT_INT4 EXT_INT5 EXT_INT6 Function controller interrupt (mailbox status, transfer done, errors) master reads synchronization master writes synchronization
Programmable Logic Implementation
following four areas programmable logic associated with EMIF interface S5933 controller:
Decode logic Add-on arbiter Data transfer control Interrupt control
Decode Logic
Decode logic monitors EMIF address signals determine when S5933 being accessed. this application report, upper address signals (EA[21:16]) used decode S5933's operation registers FIFOs. separate memory regions used, with mapped access operation register bank other mapped direct FIFO access. FIFOs accessed offset 0x20, design flexibility separate memory region also provided take advantage direct FIFO access capability support potential external FIFOs increase depth on-chip FIFOs. output decode logic flag indicating that access S5933 being made DSP. following shows example decoding logic:
Interfacing TMS320C6201 Using AMCC S5933 Controller
"Constants [EA21, EA20, EA19, EA18, EA17, EA16];
PCI_REG_ADDR PCI_FIFO_ADDR
"S5933 Decode (EMIF Request) emif_req !CE1_ PCI_REG_ADDR) PCI_FIFO_ADDR));
Add-On Arbiter
state machine required perform arbitration add-on control EMIF accesses S5933. This same state machine used handle slave transfers discussed previously. state machine expanded handle EMIF accesses S5933. Add-on arbitration inherent state machine design since state machine only services request time. EMIF requests access S5933 while transfer taking place, will held (ARDY asserted) until transfer completed. Likewise, access will begin until current EMIF access completed. state machine sets emif_ack flag when EMIF granted access add-on bus. This flag used generation ARDY signal back DSP.
ARDY emif_req emif_ack (!ARE_ !AWE_)
ARDY asserted when EMIF requests granted add-on bus, read/write strobe (ARE#/AWE#) asserted. ARDY deasserted when deasserts read/write strobe.
Data Transfer Control
There four types data transfers between EMIF S5933:
Add-on operation register write Add-on operation register read Add-on FIFO write Add-on FIFO read
type data transfer determined DSP's external address (EA), ARE#, AWE# signals. Based these values, state machine branches states that handle particular type data transfer. S5933 add-on operation register access, state machine controls S5933 signals defined Table S5933 add-on FIFO access, state machine only controls RDFIFO# signal reads WRFIFO# signal writes. RDFIFO# WRFIFO# strobes synchronized BPCLK, S5933 configured asynchronous FIFO accesses (bits offset 0x45 configuration NVRAM). Asynchronous FIFO accesses directly compatible with DSP's asynchronous EMIF.
Interfacing TMS320C6201 Using AMCC S5933 Controller
DSP's memory space control register value must select minimum CLKOUT periods read write strobes support ARDY logic. Figure shows control signal timing write S5933 add-on register. Figure shows control signal timing read from S5933 FIFO.
Figure EMIF Write S5933 Add-On Register
[21:16] [6:2] [3:0]# ARE# ARDY [6:2] [3:0]#
Interfacing TMS320C6201 Using AMCC S5933 Controller
Figure EMIF Read From S5933 Add-on FIFO
[21:16] [6:2] [3:0]# ARE# ARDY [6:2] [3:0]#
Interrupt Control
types interrupt control associated with EMIF interface S5933. first type interrupt control consists generation EXT_INT4 interrupt, which indicates general controller event, such mailbox, end-of-transfer, error condition. This interrupt routed directly EXT_INT4 pin, polarity (falling edge) opposite DSP's default polarity. consistency with other system interrupt polarities, S5933's IRQ# output inverted that EXT_INT4 asserted rising edge. Since each interrupt's polarity uniquely programmed, hardware inversion optional. second type interrupt control consists generation DSP's EXT_INT5 EXT_INT6 interrupts, which indicate when time read write S5933 FIFOs, respectively. These interrupts synchronize read write data transfers between S5933. sources these interrupts status S5933's RDEMPTY WRFULL signals, respectively. independent state machines generate EXT_INT5 (read) EXT_INT6 (write) interrupts. They both work same, only EXT_INT5 interrupt generation described. this example, register named pcimren, located programmable logic, enables interrupt generation. pcimren bit, which directly controlled software, flag used enable interrupt generation state machine. following four states required implement state machine:
Interfacing TMS320C6201 Using AMCC S5933 Controller
State MRD_IDLE: EXT_INT5 interrupt yet). When (pcimren==1) (RDEMPTY==0) goto MRD_INT, else MRD_IDLE. This state waits RDEMPTY flag because this indicates that read FIFO empty, data read from This default state reset. State MRD_INT: EXT_INT5 high interrupt DSP. Goto MRD_WAIT. This state causes external interrupt that triggers transfer that reads S5933 FIFO. State MRD_WAIT: Keep EXT_INT5 high. (pcimren (RDFIFO then goto MRD_DONE, else MRD_WAIT. This state waits state machine disabled start FIFO read access begin. State MRD_DONE: Keep EXT_INT5 high. (pcimren (RDFIFO then goto MRD_IDLE, else MRD_DONE. This state waits state machine disabled FIFO read access complete. important wait FIFO access complete FIFO flags updated before they sampled again prevent multiple interrupts.
EMIF Master Performance
data throughput optimized when burst transfers used achieve peak bandwidth Mbytes/s. Several factors influence ability maintain burst transfers, including components system. S5933 supports burst transfers achieve peaks Mbytes/s. However, limiting factor fast add-on device provide data keep pipeline full remain master achieve long bursts data. S5933 provides internal, 8-word deep FIFO that sufficient maintain long bursts, add-on device cannot provide data fast enough keep internal FIFO full. This addressed using external, high-speed dual-port SRAM FIFOs that filled add-on device before requested, resulting long bursts data peak rate. design described this application report provides simple, low-cost EMIF interface S5333 controller that provides about Mbytes/s average throughput, which comparable slave interface throughput. EMIF mastering advantage over slave transfers because transfers handled hardware without requiring host software explicitly transfer data. This means that mastering with EMIF requires less processing time host side move data, which important some applications. design described this application report uses TMS320C6x evaluation module (EVM) meet following constraints: design simple, low-cost, able support least Mbytes/s throughput. these constraints satisfied with design. (For additional information, including programming, refer TMS320C6x Evaluation Module Reference Guide Improved throughput realized using external memories increase size bursts decouple from controller's limited FIFO depth full/empty indicator flags. external memory used, burst blocks data from each interrupt assertion instead incurring additional latency overhead associated with word transferred interrupt. side, S5933 maintain longer moves data between external memory internal FIFO without interruption. possible increase data throughput average about 55-60 Mbytes/s host memory using external memories.
Interfacing TMS320C6201 Using AMCC S5933 Controller
References
[1]. TMS320C6201 Data Sheet, Texas Instruments, SPRS051, March 1998. [2]. TMS320C6201/C6701 Peripherals Reference Guide, SPRU190, March 1998. [3]. S5933 Controller Data Book, Applied Micro Circuits Corporation, 1997. [4]. TMS320C6201/6701 Host Port Interface (HPI) Performance, Zoran Nikolic, SPRA449, April 1998. [5]. TMS320C6x Evaluation Module Reference Guide, SPRU269, April 1998.
Interfacing TMS320C6201 Using AMCC S5933 Controller
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Interfacing TMS320C6201 Using AMCC S5933 Controller
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Interfacing TMS320C6201 Using AMCC S5933 Controller
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