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TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Brian Carlson Enterprises, Inc.
Abstract
This application note describes CS4231A multimedia audio codec interfaced TMS320C6201 DSP. codec's digital audio data directly interfaced DSP's McBSP efficient data transfers that don't contend DSP's EMIF. codec controlled monitored codec's parallel interface which memory-mapped directly EMIF's asynchronous interface with glue logic. EMIF access codec allows external processor also control monitor DSP's host port interface. application note also identifies other codec digital interface signals that useful some applications.
Contents
Abstract Introduction Serial Interface Timing.6 Codec Registers Registers Parallel Interface Other Interface Signals.14 References.14
Figures
Figure TMS320C6201 Interface CS4231A Multimedia Audio Codec Figure CS4231A 64-bit Enhanced Mode Serial Timing Figure Receive Control Register (RCR) Figure Transmit Control Register (XCR) Figure Sample Rate Generator Register (SRGR).10 Figure Control Register (PCR).10 Figure Serial Port Control Register (SPCR) Figure CS4231A Parallel Interface Read Timing.11 Figure CS4231A Parallel Interface Write Timing Figure EMIF Space Control Register Diagram
Digital Signal Processing Solutions
December 1998
Tables
Table Serial Port CS4231A Codec Timing Analysis.7 Table CS4231A Digital Audio Format Selection Table CS4231A Parallel Interface Parametric Timing
Introduction
TMS320C6000 interface CS4231A multimedia audio codec several ways since codec provides both parallel serial interfaces with interrupt support. most efficient interface method takes advantage CS4231A's serial audio data port which compatible with TMS320C6000's multichannel buffered serial port (McBSP). This interface method provides dedicated path serial audio data that does continuously contend bandwidth DSP's parallel, external memory interface (EMIF). codec's parallel control interface memory-mapped into DSP's EMIF control status access, which used during initialization infrequently during normal operation. separate control interface codec simplifies software driver support. codec driver does have deal with complexities additional memory requirements associated with data control/status information multiplexed single stream. added benefit, memory-mapped codec interface enables external processor control monitor codec through DSP's host port interface (HPI). This direct access codec from host processor provides flexibility that could useful some applications. This application note specifically addresses digital interfaces between codec using serial interface audio data parallel interface control status. Other parallel interface methods possible, they optimal TMS320C6201. analog interface CS4231A, other functional aspects directly related digital interface DSP, within scope this application note. CS4231A data sheet provides extensive information about device should referenced further details. Figure shows digital interfaces between TMS320C6000 CS4231A codec.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Figure TMS320C6201 Interface CS4231A Multimedia Audio Codec
CS4231A AUDIO CODEC SN74CBTD3384 BUFFER TMS320C6000
Serial Interface
SCLK
McBSP
CLKS CLKR CLKX EXT_INTx
FSYNC SDOUT SDIN A[1:0]
VOLTAGE TRANSLATION
ADDRESS
EA[3:2]
Parallel Interface
D[7:0]
DATA
EMIF
VOLTAGE TRANSLATION SN74CBTD3384 BUFFER
3.3V DATA
ED[7:0]
digital interfaces between codec consist serial interface that connects codec DSP's McBSP parallel interface that connects codec EMIF's asynchronous mode. important note that CS4231A device, signals that provides 3.3V must translated using devices such SN74CBTD3384 switches. Signals originating from need translated since their values compatible with codec. codec always generates serial data clock frame sync signals. After voltage translation, serial data clock connected three DSP's McBSP clock pins which should programmed inputs. Similarly, frame sync signal connected both FSX, which should also programmed inputs. This configuration means that both transmit receive data synchronized with phase alignment.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
codec's parallel interface consists 8-bit data bus, 2-bit address bus, chip select, read strobe, write strobe. EMIF's lower eight bits (ED[7:0]) connected codec's data using voltage translation buffer. DSP's EA[3:2] address signals mapped directly codec's A[1:0] address signals, codec register's mapped 32-bit word boundaries with only lower eight data bits being valid. EMIF asynchronous control signals directly connected codec's chip select read/write strobes since EMIF memory space control register programmed with timing characteristics that match requirements codec. optional interrupt connection shown Figure This interrupt connection independent both serial parallel interfaces required codec operation. codec supports active-high interrupt output that driven from internal 16-bit timer. This interrupt useful some applications independent watchdog timer that connected DSP's EXT_INTx inputs. this interrupt used, DSP's default rising-edge interrupt polarity should used.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Serial Interface
Timing
codec's serial port timing directly compatible with TMS320C6000 McBSP. McBSP designed directly interface with devices such CS4231A audio codec that present serial clock, frame sync data. codec generates serial data clock that operates rate times sample rate. maximum sample rate 48KHz, serial clock 3.072 MHz, which below maximum DSP. codec transitions SDOUT data rising edge SCLK samples SDIN data falling edge, which default operation McBSP. serial data streams, codec's left channel data always before right channel data, most-significant each element transmitted first which compatible with McBSP. Both left right channels' elements always bits wide with actual audio data being left justified element. example, 8-bit companded data would occupy first eight bits. Unused bits output zeros after leastsignificant bit. codec supports three types serial data formats that used with flexible McBSP. However, codec's default, 64-bit enhanced mode serial format recommended since provides most flexibility without incurring additional overhead. 64-bit enhanced mode serial format directly compatible with McBSP configured positive frame sync pulses with 1-bit data delay. this mode, each frame data bits. first bits data represent left channel second bits represent right channel. last bits optionally used monitor codec's interrupt, capture enable, playback enable over-range indicators. application does need extra status information, then number elements phase (frame) just 32-bit word. mono applications, number elements could just 16-bit word. status information needed, 32-bit mode serial format could used. this mode, clock still runs times sample rate, frame consists bits times. However, SCLK SDOUT held during last bits frame. This stopping SCLK compatible with McBSP since clock stopped after 32-bits already transferred. 32-bit mode used TMS320C62x EVM's example applications since they don't require additional status information. serial port timing requirements orders magnitude parameters maximum sample rate (3.072 SCLK), there critical timing parameters serial interface. timing analysis shown Table
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Table Serial Port CS4231A Codec Timing Analysis
CS4231A Timing Requirements (min) SDIN valid SCLK falling (min) SDIN hold after SCLK falling McBSP Timing Requirements tsu(DRV-CKRL)min Setup Time, valid before CLKR(ext) th(CKXL-DRV)min Hold Time, valid after CLKR(ext) tsu(FRH-CKRL)min Setup Time, ext. high before CLKR(ext) th(CKRL-FRH)min Hold Time, ext. high after CLKR(ext) tsu(FXH-CKXL)min Setup Time, ext. high before CLKX(ext) th(CKXL-FXH)min Hold Time, ext. high after CLKX(ext) McBSP Switching Characteristics (tSCLK/2) td(CKXH-DXV)max (tSCLK/2) td(CKXH-DXV)min CS4231A Switching Characteristics (tSCLK/2) tPD1(max) (tSCLK/2) tPD1(min) tpD1(min) available (tSCLK/2) tPD2(max) (tSCLK/2) tPD2(min) (-20) (tSCLK/2) tPD2(max) (tSCLK/2) tPD2(min) (-20) UNIT
Figure shows codec's 64-bit enhanced mode serial format.
Figure CS4231A 64-bit Enhanced Mode Serial Timing
zero
Bits Left
Bits ight
Bits
Codec Registers
CS4231A includes four direct access (R0-R3) indirect access (I0-I31) registers that used initialize, control monitor codec. There only register bits that must initialized certain manner order support digital serial interface between codec DSP. paragraphs this section highlight these specific register bits. Refer CS4231A data sheet details registers them.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
order enable CS4231A codec's serial interface, which expanded mode features, MODE2 MODE register (I12) must initialized This allows access indirect registers 16-31 that required enable configure serial interface. Alternate Feature Enable register (I16) must initialized enable serial port select serial data format. Serial Port Enable (SPE) must enable serial interface. When serial port enabled, digital audio data from ADCs sent SDOUT, audio data from SDIN sent DACs. Serial Format bits (SF1, SF0) should both select default, 64-bit enhanced serial data format. Index Address Register (R0) must before SPE, register bits changed. Playback Data Format (I8) Capture Data Format (I28) registers used select digital audio data format. these registers selects either Mono Stereo data streams. mono mode, left right channels have same data. stereo mode, alternating samples represent left right audio channels. C/L, FMT1 FMT0 bits audio data format shown Table data formats, data always sent first left justified each 16-bit element. example, 4-bit ADPCM data would occupy first four bits would followed zeros. Index Address Register (R0) must before C/L, FMT1 FMT1 register bits changed. playback capture bits (PEN/PPIO/CEN/CPIO) Interface Configuration (I9) register should enable codec's operation. Other codec registers initialized needed particular application.
Table CS4231A Digital Audio Format Selection
FMT1 FMT0 Data Format Linear, 8-bit unsigned µ-Law, 8-bit companded Linear, 16-bit, comp. A-Law, 8-bit companded RESERVED ADPCM, 4-bit RESERVED RESERVED
Registers
McBSP configuration registers need initialized support serial interface with CS4231A audio codec. There several McBSP register bits, this section only addresses ones that directly related serial interface codec. following serial interface characteristics, relative DSP, need addressed McBSP register bits initialization:
External frame syncs External serial clocks Positive frame sync polarities
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Positive serial clock polarities Single phase frames element phase 16-bits audio channel Most-significant first Left-justified with right zero fill 16-bit (Mono) 32-bit (Stereo) element length Companding match selected codec data format 1-bit data delay
Serial Port Control Register (SPCR) should initialized disable frame sync sample rate generators (/FRST,/GRST=0) since these provided codec. interrupt modes selected needed application. transmitter receiver should enabled (/RRST=/XRST=1). Control Register (PCR) should initialized enable pins support serial port operation (RIOEN=XIOEN=0). Frame syncs clocks should configured inputs since they provided codec (FSXM FSRM CLKRM CLKXM frame sync polarities should active high (FSRP=FSXP=0). transmit data should driven rising edge CLKX, receive data should sampled falling edge CLKR (CLKXP=CLKRP=0). Receive Transmit Control Registers (RCR/XCR) should initialized select data format serial interface. serial interface uses single-phase frame with data element RPHASE, XPHASE, RFRLEN1 XFRLEN1 bits should receive element length application dependent. mono applications, 16-bits only required (RWDLEN1= XWDLEN1=010b). stereo applications, 32-bits required (RWDLEN1= XWDLEN1=101b). RCOMPAND XCOMPAND bits should according selected companding mode codec. receive transmit data delay should 1-bit (RDATDLY=XDATDLY=01b). above McBSP registers their bit-field values shown Figure through Figure
Figure Receive Control Register (RCR)
RPHASE reserved RFRLEN2 RFRLEN1 RWDLEN1 RWDLEN2 RCOMPAND RFIG RDATDLY reserved
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Figure Transmit Control Register (XCR)
XPHASE reserved XFRLEN2 XFRLEN1 XWDLEN1 XWDLEN2 XCOMPAND reserved XFIG XDATDLY
Figure Sample Rate Generator Register (SRGR)
GSYNC CLKSP CLKSM FSGM FWID FPER CLKGDV
Figure Control Register (PCR)
0x0000 reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP
Figure Serial Port Control Register (SPCR)
0x00 FRST22 GRST21 XINXSYNCERR XEMPTY4 RIN3 RSYNCERR RFULL XRDY RRDY XRST0 RRST-
RJUST CLKSTP reserved reserved reserved
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Parallel Interface
codec's parallel interface directly compatible with EMIF's asynchronous mode. When EMIF's space configured asynchronous operation, high degree programmability shaping accesses provided DSP. programmable parameters include setup, strobe hold times. Setup time time between beginning memory cycle activation read (ARE) write (AWE) strobe. Strobe time time between activation deactivation read write strobe. Hold time time between deactivation read write strobe cycle. codec's parallel interface timing defined read cycle timing diagram shown Figure write cycle timing diagram shown Figure Table provides parametric timing indicated timing diagrams.
Figure CS4231A Parallel Interface Read Timing
tCSSU
tDHD1
tADSU
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Figure CS4231A Parallel Interface Write Timing
CSSU
tCSHD
tRDDV
WDSU
DHD2
D[7:0] ED[7:0] A[1:0] EA[3:2]
tADSU tADHD
Table CS4231A Parallel Interface Parametric Timing
Parameter setup falling edge hold from rising edge strobe width falling edge data valid Data hold from rising edge Data valid rising edge Data hold from rising edge Address setup falling edge Address hold from rising edge Symbol tCSSU tCSHD tSTW tRDDV tDHD1 tWDSU tDHD2 tADSU tADHD (ns) (ns)
Figure EMIF Space Control Register Diagram
0101 WRITE SETUP Reserved 10010 WRITE STROBE 10010 READ STROBE WRITE HOLD MTYPE 0101 READ SETUP reserved READ HOLD
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
start asynchronous EMIF access codec's parallel interface begins with memory space's chip enable (CE0#) being asserted. codec setup requirements prior falling edge read write data strobe. chip select must setup least address must setup least before data strobe's falling edge. Since EMIF CE0# address signals transition same CLKOUT1 edge, worst case setup time that This time period defines asynchronous setup time that should programmed CE0# memory space control register located address 0x1800008. Assuming clock MHz, with CLKOUT1 period read write setup fields this control register should codec requires minimum read write data strobe period least This means that read write strobe fields control register should During read access, codec register data available after maximum into strobe period. This means that there data setup which easily meets DSP's setup requirement. codec data hold time minimum after rising edge read strobe. Since rising edge read strobe after edge that samples data, this problem. During write access, codec requires that data setup least before rising edge write strobe. Since provides valid data beginning memory cycle writes, there approximately setup time. codec requires that write data held least after rising edge write strobe. Since holds data valid until hold period, length hold period must least codec's chip select does have held past rising edge read write data strobe. However, address signals must held least after data strobe's rising edge. worst case hold time therefore, defined write data hold time MHz, this means that read write hold fields control register should codec timing parameter that shown timing diagrams that important note that there must least between rising edge read write strobe next falling edge read write strobe. This means that codec accesses need controlled, either hardware software, application would ever attempt perform sequential register accesses codec. hardware approach simple increasing setup strobe periods EMIF memory space control register clocks respectively. this total clocks between data strobe beginning next would would meet requirement. more elaborate solution would programmable logic manage codec interface signals ensure that back-to-back accesses meet minimum time period. This solution required anyway additional asynchronous devices were required same memory space. software approach would require delay inserted between codec accesses ensure that requirement met. codec cannot allocated asynchronous EMIF memory space, such CE0#, co-exist with other asynchronous devices using programmable logic that manages codec interface signal timing provides required ready (ARDY) signal generation. This approach taken TMS320C6x since multiple devices, including daughter board interface, co-exist asynchronous interface. When multiple asynchronous devices with different timing requirements design, programmable logic required handle these timing differences through ARDY signal.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
Other Interface Signals
There other codec signals independent from serial parallel interfaces that could interfaced some applications. mentioned previously, codec's interrupt output interfaced DSP's external interrupt inputs. codec provides on-chip timer that used independent timing source watchdog timer. codec's power-down (/PDWN) input controlled disable device into low-power mode. codec provides general-purpose output signals (XCTL1/XCTL0) that controlled writes codec's Control (I10) register.
References
[1]. TMS320C6201 Data Sheet, Texas Instruments, SPRS051, March 1998. [2]. TMS320C6201/C6701 Peripherals Reference Guide, SPRU190, March 1998. [3]. CS4231A Parallel Interface, Multimedia Audio Codec Data Sheet, Crystal Semiconductor, September 1994. [4]. TMS320C6x Evaluation Module Reference Guide, SPRU269, April 1998.
TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
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TMS320C6000 McBSP Interface CS4231A Multimedia Audio Codec
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