ABSTRACT Development begin TMS320C6211 systems. compatibility bet

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ABSTRACT Development begin TMS320C6211 systems. compatibility bet

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Begin Development Today with TMS320C6211
ABSTRACT
Development begin TMS320C6211 systems. compatibility between TMS320C6000 generation devices, current `C6000 tools used develop code `C6211 other future devices. This allows systems running when silicon becomes available.
Contents
Begin Development Today with TMS320C6211 DSP. TMS320C6000 Compatibility
Similarities between 'C6211 'C6201 DSPs Differences between 'C6211 'C6201 DSPs
Best Price/Performance. Begin writing code 'C6211 today.
C6000 tools support.6 support.6 `C6000 literature available
Figures
Figure TMS320C6200 Fixed-Point Roadmap Figure TMS320C6211 Digital Signal Processor.3
Digital Signal Processing Solutions
September 1998
Begin Development Today with TMS320C6211
Texas Instruments TMS320C6000 generation high-performance digital signal processors includes TMS320C6211. `C6211 low-cost version original `C6000 device, `C6201. `C6211 device will begin sampling first quarter 1999, providing 1200 MIPS (million instructions second) 150MHz. Introduced February 1997, `C6000 generation based TI's VelociTIarchitecture, advanced very long instruction word (VLIW) architecture DSPs. Figure shows roadmap fixed-point generation `C6000 platform.
Figure TMS320C6200 Fixed-Point Roadmap
C6202 233-250+
pans
C6201 167-200
C6200B 0.18
C6201B 167-200+
Lower L1/L2 emory ystem Enhanc
C6200A 0.25
C6211 150-167
1997
1998
1999
Begin Development Today with TMS320C6211
TMS320C6000 Compatibility
`C6000 generation devices code-compatible with another, with exception that there some floating-point instructions that only valid floating-point (`C67x) members. 'C6200 fixed-point devices based same core designed achieve high performance through increased instruction-level parallelism. Surpassing throughput traditional superscalar designs, VelociTI provides eight execution units, including multipliers arithmetic logic units (ALUs). These units operate parallel perform eight instructions during single clock cycle-up 2000 MIPS MHz. VelociTI's advanced features include instruction packing, conditional branching, variablewidth instructions, pre-fetched branching, which eliminate problems that were previously associated with VLIW implementations. architecture highly deterministic, with restrictions when instructions fetched, executed, stored. This architectural flexibility breakthrough efficiency levels 'C6000 compiler. This common architecture allows designers begin development with existing `C6000 software tools those devices currently development. This also allows migration from `C6000 processor another, design requirements require. addition CPU, many on-chip peripherals common between `C6000 devices. Figure shows block diagram `C6211. Those blocks gray shared between `C6201 `C6211.
Figure TMS320C6211 Digital Signal Processor
External Memory Interface (EMIF) Multi-channel Buffered Serial Port (McBSP Multi-channel Buffered Serial Port (McBSP Host Port Interface (HPI) Power Down Logic
C6211 Digital Signal Processor
Controller
Cache Direct Mapped Kbytes
Enhanced Controller
Memory Banks Kbytes
C6200B Control Registers Instruction Dispatch In-Circuit Instruction Decode Emulation Instruction Fetch Data Path Register File Data Path Register File
Timer
Timer
Controller
Cache 2-Way Associative Kbytes
Interrupt Control
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Similarities between 'C6211 'C6201 DSPs
`C6211 highly-compatible with first `C6000 device, `C6201. following device components identical between devices:
CPU: `C6211 identical that `C6201, which means that code written `C6201 will unmodified `C6211. Multi-channel Buffered Serial Ports (McBSPs): McBSPs unchanged `C6211. Host-Port Interface (HPI): 16-bit asynchronous identical that `C6201. 32-bit Timers: timers `C6211. Interrupt Selection: There similar interrupt sources that used interrupt send event controller.
Differences between 'C6211 'C6201 DSPs
Several modifications have been made allow `C6211 available significantly lower cost than original `C6201. These include:
Slower clock rate: maximum clock frequency been decreased from 150MHz. This will still allow 1200MIPs during operation. Cache memory architecture: `C6211 cache-based device, with separate level-one program data caches. These small, fast memories always active, provide with high (~98%) rate most applications. Another internal memory block available level-two cache, memory mapped SRAM space, combination two. Enhanced Direct Memory Access (EDMA) controller: enhanced been implemented `C6211 provide more flexibility programming data transfers. External Memory Interface (EMIF): EMIF been enhanced allow device interface more memory types. `C6211 interface 16-, 32-bit SDRAM, SBSRAM, asynchronous memories.
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Best Price/Performance
cache architecture `C6211 allows this device offered cost, while keeping high performance capabilities the'C6000 generation. having efficient on-chip cache, system designers slower, less expensive external memory devices data program storage without seriously reducing processing speed device. addition, cache helps programmers achieve their performance goals faster, shortening code development accelerating time market. on-chip memory organized allow design flexibility ensure efficient memory usage. `C6211 72Kbytes on-chip memory, with 8Kbytes serving levelone (L1) cache that directly access. L1cache divided into Kbytes program (L1P) Kbytes data (L1D) cache memory. remaining 64Kbytes on-chip memory unified program data memory space. serve level-two (L2) cache, directly mapped internal memory, serve combination these functions. direct-mapped, that each instruction byte occupies unique location cache. wide data path CPU, that fetch eight instructions (one fetch packet) every cycle. two-way associative, that hold different sets information with independent address ranges. cache dual-ported memory that allows simultaneous accesses from both data ports, that load store 32-bit values single data cycle. cache uses least-recently-used (LRU) replacement scheme select between possible cache locations. memory divided into four 16-Kbyte banks, each which programmed cache space. Each bank selected cache adds associativity, allowing cache 4-way associative. which selected cache included `C6211 memory map. mapability blocks addressable locations allows critical code data locked into internal memory. enhanced direct memory access (EDMA) controller allows designers optimize data organization their systems. Capable accessing location `C6211 memory map, EDMA used transfer data background operation. EDMA controller handle multiple transfers simultaneously interleave bursts. EDMA offers independent channels, with separate space hold additional transfer configurations. Each EDMA channel synchronized event allow minimal intervention CPU. extensive tests 'C6211 determine performs with enhanced full-rate vocoder, system-level applications ADSL, routines multichannel modems, other commonly used algorithms. both data program, TI's tests indicate cache rates greater than percent. high rate, combined with flexibility memory organization, means that 'C6211 operate more than percent cycle performance more costly device with ideal memory organization where system memory chip. This high degree efficiency allows systems such client units rely inexpensive external memory program data storage, while same time performing high-speed number-crunching routines real time.
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`C6211 designed with TI's low-power high-density TSC6000 ASIC Standard Cell library cost, while still providing 150MHz performance.
Begin writing code 'C6211 today
identical CPUs `C6211 `C6201 devices allow code written `C6211 using existing `C6000 tools. `C6201 code will require modification `C6211. peripheral-specific code, with exception EDMA will also able unchanged `C6211. This high level compatibility between processors allows system development begin now. taking advantage `C6000 software tools currently available, `C6211 systems have running start when silicon becomes available. `C6000 compiler used members `C6000 device platform. Fixedpoint devices object code compatible, code written `C6201 used `C6211. Code development `C6211 begin using `C6000 fast simulator. simulator provides cycle-accurate account device performance, assuming that onchip memory used code data. simulator provides good environment learn `C6000 VLIW architecture. fast simulator used model `C6211 high cache rate lack memory bank conflicts data accesses. standard `C6000 simulator used incorporate peripheral support. `C6211 designs worked detail simulator prior purchasing actual silicon, with cycle-accurate accounts peripherals performance. peripherals `C6211, with exception EDMA identical those modeled simulator. `C6211-specific simulator also available model cache performance device. Using this simulator, possible optimize code structure data organization take advantage `C6211 cache structure. This simulator provides 100% cycle accuracy both cache misses. EDMA simulated with cycle accuracy `C6211 simulator. development start hardware, `C6201 used understand `C6000 functionality. peripherals `C6211 identical those `C6201, with exception EDMA, good tool understand incorporate peripherals into real-time system. Applications running `C6201 will 100% cycle accurate `C6211 system, difference internal memory architecture, `C6211 will provide approximately same performance `C6201 operating 150MHz. Using these development platforms, well `C6000 literature currently available will enable `C6211 systems completed soon after `C6211 silicon made available.
C6000 tools support support
`C6000 tools available `C6000 designs. `C6211 specific support will added development tools early fourth quarter 1998. `C6000 development tools available today are:
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`C6000 Simulator Software `C6000 Optimizing Compiler/Assembler TMS320C6201 Evaluation Module (EVM) XDS510 `C6000 Source Debugger Software XDS510 Emulator Hardware with JTAG Emulation Cable
`C6000 literature available
great deal literature available today `C6000 devices.
TMS320C62x/C67x Instruction Reference Guide TMS320C6201/C6701 Peripherals Reference Guide TMS320C6202/C6211 Peripherals Reference Guide Addendum TMS320C6000 Technical Brief TMS320C62x/C67x Programmer's Guide TMS320C6x Evaluation Module Reference Guide TMS320C6000 Peripheral Support Library Programmer's Reference TMS320C6x Assembly Language Tools User's Guide TMS320C6x Optimizing Compiler User's Guide TMS320C6x Source Debugger User's Guide TMS320C6x Source Debugger Sparcstations
Many application notes also exist assistance with `C6000 applications.
Bit-Reverse/Digit-Reverse: Linear-Time Small Lookup Table ImplementationC6000
Guidelines Software Development Efficiency TMS320C6000 VelociTI
Architecture
Implementation G.726 ADPCM TMS320C62XX Implementing V.32BIS VITERBI Decoding TMS320C62XX Performance Analysis Line Echo Cancellation Implementation Using
TMS320C6201
TMS320C6201 (Revision 2.X) TMS320C6201B (Revision 3.X) TMS320C6201 Power Supply TMS320C6201 System Clock Circuit Example TMS320C6201/6701 Host Port Interface (HPI) Performance TMS320C6X EMIF External SDRAM/SGRAM Interface TMS320C6X Manufacturing With Package TMS320C6X Reset Circuit TMS320C6X Thermal Design Considerations Using TMS320C6X McBSP High Speed Communication Port
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more information.
IMPORTANT NOTICE
Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain application using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. Copyright 1998, Texas Instruments Incorporated trademark Texas Instruments Incorporated.
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ABSTRACT Development begin TMS320C6211 systems. compatibility bet

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