Kyle Castille Digital Signal Processing Solutions Abstract I

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TMS320C6000 EMIF External SDRAM/SGRAM Interface
Kyle Castille Digital Signal Processing Solutions
Abstract
Interfacing external SDRAM Texas Instruments (TITM) TMS320C6000 digital signal processor (DSP) simple compared previous generations DSPs because advanced external memory interface (EMIF). EMIF glueless interface variety external memory devices. This application report describes EMIF's control registers SDRAM/SGRAM signals along with SDRAM functionality, including functions supported EMIF performance considerations when used with EMIF. General examples include several SDRAM configurations supported EMIF, including timing analysis. addition, specific examples provided using Micron SDRAM.
Contents
Interface 'C6000 EMIF with SDRAM SGRAM 'C6201/'C6202/'C6701 Compatible Memory Types 'C6211/'C6711 Compatible Memory Types.5 'C6201/'C6202/'C6701 Forced Compatibility Memory Types.6 'C6211/'C6711 Forced Compatibility Memory Types 'C6000 EMIF-to-SDRAM/SGRAM Physical Interface Overview `C6000 EMIF 'C6201/'C6202/'C6701 SDRAM Interface Summary.16 'C6211/'C6711 SDRAM Interface Summary 'C6000 EMIF Signal Descriptions 'C6000 EMIF Registers SDRAM SDRAM Commands.27 SDRAM Initialization Monitoring Page Boundaries.38 Address Shift.40 Timing Constraints Complete Example Using 'C6201B Micron's MT48LC4M16A2-10.46 Register Configuration 'C6201B MT48LC4M16A2 Complete Example Using 'C6211 Micron's MT48LC16M8A2-8 Register Configuration 'C6211 MT48LC16M8A2.49 Appendix Code Example 'C6201B Micron MT48LC4M16A2-10.52 References.53
Digital Signal Processing Solutions
June 1999
Figures
Figure 'C6000 EMIF 16-Mbit SDRAM Interface Using 16-Bit-Wide Chips.10 Figure 'C6000 EMIF 16-Mbit SDRAM Interface Using Four 8-Bit-Wide Chips Figure 'C6000 EMIF 64-Mbit SDRAM Interface Using 16-Bit-Wide Chips.12 Figure 'C6000 EMIF 64-MBit SDRAM Interface Using 32-Bit-Wide Chip Figure 'C6211/'C6711 EMIF 64-Mbit SDRAM Interface Using 16-Bit-Wide Chip-Big Endian Figure 'C6201/'C6202/'C6701 EMIF-to-8-Mbit SGRAM Figure 'C6211/'C6711 EMIF-to-8-MBit SGRAM Figure 'C6201/'C6202/'C6701 EMIF-to-16-Mbit SGRAM Figure 'C6211/'C6711 EMIF-to-16-MBit SGRAM Figure 'C6201/'C6202/'C6701 EMIF-to-32-Mbit SGRAM Figure 'C6201/'C6701 EMIF Block Diagram Figure 'C6202 EMIF Block Diagram.18 Figure 'C6211/'C6711 EMIF Block Diagram Figure 'C6211/'C6711 Byte-Lane Alignment Endianness Figure 'C6201 'C6201B/'C6701 Output Timing.21 Figure 'C6202 Output Timing Figure 'C6211/'C6711 Output Timing.21 Figure EMIF Global Control Register Diagram.22 Figure 'C6201/'C6202/'C6701 EMIF Space Control Register Diagram Figure 'C6211/'C6711 EMIF Space Control Register Diagram Figure EMIF SDRAM Control Register.24 Figure EMIF SDRAM Refresh Period.26 Figure 'C6211/'C6711 SDRAM Extension Register Figure SDRAM DCAB-Closes Banks Space.30 Figure 'C6211/'C6711 SDRAM DEAC-Closes Single Bank Specified BS.30 Figure 'C6201/'C6202/'C6701 SDRAM Read-CAS Latency Figure 'C6211/'C6711 SDRAM Read-CAS Latency Figure 'C6211/'C6711 SDRAM Read With DEAC.33 Figure 'C6201/'C6202/'C6701 SDRAM Burst Length Write Figure 'C6211/'C6711 SDRAM Burst Length Write.35 Figure Mode Register Value Figure SDRAM Mode Register Set: Command Figure SDRAM Refresh Figure Logical Address Breakdown Bank Bit, Bits, Column Bits.39 Figure Outputs From 'C6201/'C6202/'C6701 (Write Data [ED], Control, Address Signals).43 Figure Outputs From 'C6211/'C6711 (Write Data [ED], Control, Address Signals) Figure Input 'C6000 (Read Data) Figure EMIF Global Control Register Diagram 'C6201B MT48LC4M16A2 Figure EMIF Space Control Register Diagram 'C6201B MT48LC4M16A2 Figure EMIF SDRAM Control Register 'C6201B MT48LC4M16A2.47 Figure EMIF SDRAM Refresh Period 'C6201B MT48LC4M16A2.48 Figure EMIF Global Control Register Diagram 'C6211 MT48LC16M8A2 Figure EMIF Space Control Register Diagram 'C6211 MT48LC16M8A2.49 Figure EMIF SDRAM Control Register 'C6211 MT48LC16M8A2 Figure EMIF SDRAM Refresh Period 'C6211 MT48LC16M8A2
Tables
Table Table Table Table Table Table Table Table Table 'C6201/'C6202/'C6701 Compatible Memory Type Characteristics.4 'C6211/'C6711 Compatible Memory Type Characteristics Characteristics Forced Compatible Memory Types.6 4-Mbit SDRAM/8-Mbit SGRAM Memory 'C6201/'C6202/'C6701 16-Mbit SGRAM Memory 'C6201/'C6202/'C6701 32-Mbit SGRAM Memory 'C6201/'C6202/'C6701 Characteristics Forced Compatible Memory Types 'C6211/'C6711 4-Mbit SDRAM/8-Mbit SGRAM Memory 'C6211/'C6711.8 16-Mbit SGRAM Memory 'C6211/'C6711
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 32-Mbit SGRAM Memory 'C6211/'C6711 'C6000 EMIF Signal Descriptions: Shared Signals SDRAM Signals 'C6000 EMIF Memory Mapped Registers EMIF Global Control Register Field Description.23 'C6000 EMIF Space Control Register Field Description SDRAM.24 EMIF SDRAM Control Register Field Description EMIF SDRAM Refresh Period Field Description 'C6211/'C6711 EMIF SDRAM Extension Register Field Description EMIF SDRAM Commands Truth Table SDRAM Commands 'C6201/'C6202/'C6701 SDRAM Timing Parameters 'C6211/'C6711 SDRAM Timing Parameters 'C6211/'C6711 Recommended Values Parameters Implied SDRAM Configuration Value.36 'C6201/'C6202/'C6701 Byte Address Mapping SDRAM CAS.40 'C6211/'C6711 Byte Address Mapping SDRAM SDRAM Registers Timing Parameter Calculation SDRAM Control Register 'C6201B MT48LC4M16A2 Period Calculation SDRAM Refresh Period 'C6201B MT48LC4M16A2 SDRAM Registers 'C6211 MT48LC16M8A2.49 Timing Parameter Calculation SDRAM Control Register 'C6211 MT48LC16M8A2.50 Period Calculation SDRAM Refresh Period 'C6211 MT48LC16M8A2.50 SDRAM Extension Register Values 'C6211 MT48LC16M8A2
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Interface 'C6000 EMIF with SDRAM SGRAM
EMIF 'C6000 devices offer glueless interface industry standard SDRAM most commonly available configurations, including Mbit Mbit Mbit Mbit devices. Depending specific 'C6000 device, additional configurations supported.
'C6201/'C6202/'C6701 Compatible Memory Types
'C6201/'C6202/'C6701 EMIF supports glueless interface Mbit, bank Mbit, bank SDRAM, offering system designers interface high-speed highdensity memory. Table lists possible SDRAM configurations that fully supported EMIF. Table shows, SDRAM supported 'C6201/'C6202/'C6701 EMIF either eight nine column address bits maps into memory space equal smaller than Mbytes. Because 'C6201/'C6202/'C6701 EMIF 32-bit word size, four 8bit 16-bit devices must used parallel create 32-bit word.
Table 'C6201/'C6202/'C6701 Compatible Memory Type Characteristics
SDRAM Banks Width Depth Devices/ AddressSize able Space (MBytes) SDRAM Mbit 512K EMIF SDRAM EMIF SDRAM Mbit 512K EMIF SDRAM EMIF Column Address Address Bank Select Precharge
A8-A0 EA10-EA2 A7-A0 EA9-EA2 A7-A0 EA9-EA2 A7-A0 EA9-EA2
A10-A0 SDA10, EA11-EA2 A10-A0 SDA10, EA11-EA2 A11-A0 SDA10, EA13-EA2 A10-A0 SDA10, EA11-EA2
EA13 EA13 A13-A12 EA15EA14 A12-A11 EA14EA13
SDA10 SDA10 SDA10 SDA10
Table summarizes page characteristics fully supported SDRAM memory types illustrates EMIF-to-SDRAM mapping. SDRAM uses addresses A[x:0]. These pins mapped EA[x+2:2] EMIF because EMIF assumes that SDRAM memory spaces bits wide. four signals serve LSBs (least significant bits) external address. element supported SDRAM memory types that always precharge pin. support this functionality, EMIF's SDRAM interface uses named SDA10 instead EA12 support necessary SDRAM operations. During activate, SDA10 logically equivalent EA12. other SDRAM operations, SDA10 used precharge pin.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6211/'C6711 Compatible Memory Types
'C6211/'C6711 style EMIF supports glueless interface almost configuration SDRAM memory types, including those supported 'C6201/'C6202/'C6701 EMIF. This possible because larger spaces programmable SDRAM page characteristics. Table lists common configurations SDRAM that fully supported 'C6211/'C6711 EMIF.
Table 'C6211/'C6711 Compatible Memory Type Characteristics
SDRAM Banks Width Depth AddressSize Devices/ able space (MBytes) Mbit 512K 512K 128M SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF Column Address Address Bank Select Precharge
Mbit
Mbit
Mbit
A9-A0 EA11-EA2 A8-A0 EA10-EA2 A7-A0 EA9-EA2 A9-A0 EA11-EA2 A8-A0 EA10-EA2 A7-A0 EA9-EA2 A7-A0 EA9-EA2 A9-A0 EA11-EA2 A8-A0 EA10-EA2 A9-A0 EA11-EA2 A8-A0 EA10-EA2
A10-A0 EA12-EA2 A10-A0 EA12-EA2 A10-A0 EA12-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A10-A0 EA12-EA2 A11-A0 EA13-EA2 A11-A0 EA13-EA2 A12-A0 EA14-EA2 A12-A0 EA14-EA2
EA13 EA13 EA13 A13-A12 EA15-EA14 A13-A12 EA15-EA14 A13-A12 EA15-EA14 A12-A11 EA14-EA13 A13-A12 EA15-EA14 A13-A12 EA15-EA14 A14-A13 EA16-EA15 A14-A13 EA16-EA15
EA12 EA12 EA12 EA12 EA12 EA12 EA12 EA12 EA12 EA12 EA12
Table summarizes page characteristics fully supported SDRAM memory types illustrates EMIF-to-SDRAM mapping. SDRAM uses addresses A[x:0]. These pins mapped EA[x+2:2] EMIF because 'C6211/'C6711 EMIF assumes that SDRAM memory spaces bits wide. four signals serve LSBs external address. element supported SDRAM memory types that always precharge pin. Because hidden refresh supported 'C6211/'C6711 EMIF, EA12 maps directly SDRAM. 'C6211/'C6711 EMIF does SDA10 signal, does 'C6201/'C6202/'C6701 EMIF. Note that 'C6211/'C6711 EMIF also supports SDRAM memory space widths 16-bits wide.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6201/'C6202/'C6701 Forced Compatibility Memory Types
smaller amount SDRAM desired than offered with fully compatible memory types, 4-Mbit SDRAM SGRAM types useful. advantages realized using these memory types could either price board space. Table shows that SGRAM types bits wide; therefore, only device needed space, which reduces amount board space used. price advantage, 4-Mbit SDRAM used, which still requires devices space. Although SGRAM fully compatible with 'C6201/'C6701 EMIF, similarities between SGRAM SDRAM exploited force SGRAM functional with EMIF. This accomplished taking advantage identical page size between 8Mbit, 16-Mbit, 32-Mbit SGRAM 16-bit-wide SDRAM. This technique also used with 4-Mbit SDRAM. Table illustrates characteristics 4-Mbit SDRAM 8-Mbit, 16-Mbit, 32-Mbit SGRAM mappings used 'C6201/'C6202/'C6701 EMIF.
Table Characteristics Forced Compatible Memory Types
SDRAM Bank Width Depth AddressDevices/ able Size space (MBytes) 4-Mbit SDRAM 8-Mbit SGRAM 16-Mbit SGRAM 32-Mbit SGRAM SDRAM 128k EMIF SGRAM 128k EMIF SGRAM 256k EMIF SGRAM 512K EMIF Column Address Address Bank Select Precharge
A[7:0] EA[9:2] A[7:0] EA[9:2] A[7:0] EA[9:2] A[7:0] EA[9:2]
A[8:0] SDA10, EA[9:2] A[8:0] SDA10, EA[9:2] A[9:0] SDA10, EA[10:2] A[10:0] EA[11:10], SDA10, A[9:2]
EA11 EA11 EA11 EA13
SDA10 SDA10 SDA10 SDA10
Table shows, column addressing each these memory types identical column addressing used with 16-bit-wide fully compatible memory types. discussed later, only control that specifies type SDRAM control EMIF SDRAM control register that specifies either 8-bit-wide 16-bit-wide SDRAM. If-8-bit wide SDRAM specified, column address using lower order bits used, address shifted accordingly. 16-bit-wide SDRAM specified, lower order bits used column address, address shifted accordingly. Because memory types Table have 8-bit column addressing schemes, 16bit-wide interface forced work with these memory types. problem arises different precharge bank select pins used. memories Table either precharge SDRAM/SGRAM either bank select pin. force compatibility with SDRAM operations, SDA10 still must used precharge signal from EMIF. However, during addressing SDA10 logically equivalent EA12. EA10 used 4-Mbit SDRAM 8-Mbit SGRAM (which have identical page characteristics); thus there hole memory map, effectively giving image previous Kbytes. 16-Mbit 32-Mbit SGRAM, hole eliminated because every used. This summarized Table Table Table
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 4-Mbit SDRAM/8-Mbit SGRAM Memory 'C6201/'C6202/'C6701
kwords Image kwords
Bank bottom half Bank bottom half Bank half Bank half
kwords
Image
kwords
kwords Image kwords kwords Image kwords
Table 16-Mbit SGRAM Memory 'C6201/'C6202/'C6701
kwords kwords kwords kwords
Bank bottom half Bank bottom half Bank half Bank half
Table 32-Mbit SGRAM Memory 'C6201/'C6202/'C6701
kwords kwords
Bank Bank
'C6211/'C6711 Forced Compatibility Memory Types
Although SGRAM fully compatible with 'C6211/'C6711 EMIF, similarities between SGRAM SDRAM exploited force SGRAM functional with EMIF. This accomplished taking advantage identical page size between 8-Mbit, 16-Mbit, 32-Mbit SGRAM 16-bit-wide SDRAM. This technique also used with 4-Mbit SDRAM. Table illustrates characteristics 4-Mbit SDRAM 8-Mbit, 16-Mbit, 32-Mbit SGRAM mappings used 'C6211/'C6711 EMIF.
Table Characteristics Forced Compatible Memory Types 'C6211/'C6711
SDRAM Banks Width Depth AddressSize Devices/ able space Bytes) 4-Mbit SDRAM 8-Mbit SGRAM 16-Mbit SGRAM 32-Mbit SGRAM SDRAM 128K EMIF SGRAM 128K EMIF SGRAM 256K EMIF SGRAM 512K EMIF Column Address Address Bank Select Precharge
A[7:0] EA[9:2] A[7:0] EA[9:2] A[7:0] EA[9:2] A[7:0] EA[9:2]
A[8:0] EA12, EA[9:2] A[8:0] EA12, EA[9:2] A[9:0] EA12, EA[10:2] A[10:0] EA[11:10], EA12, EA[9:2]
EA13 EA13 EA13 EA13
EA12 EA12 EA12 EA12
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table shows, column addressing each these memory types identical column addressing used with 16-bit-wide fully compatible memory types. 'C6211/'C6711 interface SGRAM slightly different than 'C6201 style interface. This because 'C6211/'C6711 SDRAM controller must programmed with number column address bits, address bits, bank select bits. EA12 must always connected precharge input SDRAM. Also, care must taken ensure that bank select outputs 'C6211/'C6711 correspond bank select inputs SGRAM. bank select outputs 'C6211/'C6711 always correspond address bits EA13 above because least address bits always assumed. Because SGRAM fewer address bits (depending specific device), EA13 always tied bank select input SGRAM. This results holes memory because 4-Mbit SDRAM 16-Mbit SGRAM have fewer than address bits. 32-Mbit SGRAM interface accomplished without holes memory map, shown Table
Table 4-Mbit SDRAM/8-Mbit SGRAM Memory 'C6211/'C6711
kwords Three Images kwords kwords Three Images kwords kwords Three Images kwords kwords Three Images kwords
Bank bottom half
Bank half
Bank bottom half
Bank half
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 16-Mbit SGRAM Memory 'C6211/'C6711
kwords Image kwords kwords Image
Bank bottom half
Bank bottom half kwords Bank half
kwords Image kwords kwords Image kwords
Bank half
Table 32-Mbit SGRAM Memory 'C6211/'C6711
kwords kwords
Bank Bank
'C6000 EMIF-to-SDRAM/SGRAM Physical Interface
following figures illustrate EMIF SDRAM interface 'C6000 devices. 16Mbit SDRAM interfaces shown Figure Figure 64-Mbit interfaces shown Figure Figure Table describes connection related signals specific SDRAM operation. 16-bit interface 'C6211/'C6711 (big-endian) shown Figure Although every possible interface shown 'C6211/'C6711, examples below used reference. interfaces denser SDRAMs (such 128-Mbit 256-Mbit), only difference that additional address bits used. control data interfaces identical figures shown here.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6000 EMIF 16-Mbit SDRAM Interface Using 16-Bit-Wide Chips
/SDRAS /SDCAS /SDWE /RAS /CAS DQMU DQML A[11] A[10] A[9:0] DQ[15:0]
External Memory Interface (EMIF)
/BE[3] /BE[2] /BE[1] /BE[0]
Mbit SDRAM (1Mx16)
EA[13] SDA10/EA12** EA[11:2] ED[31:16] ED[15:0] SDCLK 'C6701/'C6701 CLKOUT2 'C6202 ECLKOUT 'C6211/'C6711 (system must provide ECLKIN) SDA10 used 'C6201/'C6202/'C6701 EA12 used 'C6211/'C6711
/RAS /CAS DQMU DQML A[11] A[10] A[9:0] DQ[15:0]
Mbit SDRAM (1Mx16)
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6000 EMIF 16-Mbit SDRAM Interface Using Four 8-Bit-Wide Chips
/RAS /CAS A[11] A[10] A[9:0] DQ[7:0] /CEn /SDRAS /SDCAS /SDWE BE[3] BE[2] BE[1] BE[0] EA[13] SDA10/EA12** EA[11:2] ED[31:24] ED[23:16] ED[15:8] ED[7:0] /RAS /CAS A[11] A[10] A[9:0] DQ[7:0] /RAS /CAS A[11] A[10] A[9:0] DQ[7:0] /RAS /CAS A[11] A[10] A[9:0] DQ[7:0]
Mbit SDRAM
External Memory Interface (EMIF)
Mbit SDRAM
SDCLK `C6201/'C6701 CLKOUT2 `C6202 ECLKOUT `C6211/'C6711 (system must provide ELCKIN) SDA10 used `C6201/'C6202/'C6701 EA12 used `C6211/'C6711
Mbit SDRAM
Mbit SDRAM
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6000 EMIF 64-Mbit SDRAM Interface Using 16-Bit-Wide Chips
/SDRAS /SDCAS /SDWE /RAS /CAS DQMU DQML A[13:11] A[10] A[9:0] DQ[15:0]
External Memory Interface (EMIF)
/BE[3] /BE[2] /BE[1] /BE[0]
Mbit SDRAM (4Mx16)
EA[15:13] SDA10/EA12** EA[11:2] ED[31:16] ED[15:0]
(system
SDCLK 'C6701/'C6701 CLKOUT2 'C6202 ECLKOUT 'C6211/'C6711 must provide ECLKIN)
/RAS /CAS DQMU DQML A[13:11] A[10] A[9:0] DQ[15:0]
Mbit SDRAM (4Mx16)
SDA10 used 'C6201/'C6202/'C6701 EA12 used 'C6211/'C6711
Figure 'C6000 EMIF 64-MBit SDRAM Interface Using 32-Bit-Wide Chip
/SDRAS /SDCAS /SDWE /RAS /CAS
64Mbit SDRAM (2Mx32)
External Memory Interface (EMIF)
/BE[3:0]
DQM[3:0] A[12:11] A[10] A[9:0] DQ[31:0]
EA[14:13] SDA10/EA12** EA[11:2] ED[31:0]
SDCLK 'C6701/'C6701 CLKOUT2 'C6202 ECLKOUT 'C6211/'C6711 (system must provide ECLKIN) SDA10 used 'C6201/'C6202/'C6701 EA12 used 'C6211/'C6711
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 EMIF 64-Mbit SDRAM Interface Using 16-Bit-Wide Chip-Big Endian
External Clock /RAS /CAS DQMU DQML A[13:0] DQ[15:0]
ECLKIN ECLKOUT /SDRAS /SDCAS /SDWE
External Memory Interface (EMIF)
/BE[3] /BE[2] /BE[1] /BE[0]
Mbit SDRAM (4Mx16)
EA[15:2] ED[31:16] ED[15:0]
Figure 'C6201/'C6202/'C6701 EMIF-to-8-Mbit SGRAM
CLKOUT2 SDCLK /SDRAS /SDCAS /SDWE /RAS /CAS
8Mbit SGRAM (256kx32)
External Memory Interface (EMIF)
/BE[3:0]
DQM[3:0] A[9] A[8] A[7:0] D[31:0]
EA[11] SDA10 EA[9:2] ED[31:0]
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 EMIF-to-8-MBit SGRAM
External Clock /RAS /CAS /BE[3:0] EA[11:10] EA13 EA12 EA[9:2] ED[31:0] DQM[3:0] A[9] A[8] A[7:0] D[31:0]
ECLKIN ECLKOUT /SDRAS /SDCAS /SDWE
8Mbit SGRAM (256kx32)
External Memory Interface (EMIF)
Figure 'C6201/'C6202/'C6701 EMIF-to-16-Mbit SGRAM
CLKOUT2 SDCLK /SDRAS /SDCAS /SDWE /RAS /CAS
16Mbit SGRAM (512kx32)
External Memory Interface (EMIF)
/BE[3:0]
DQM[3:0] A[10] A[9] A[8:0] D[31:0]
EA[11] SDA10 EA[10:2] ED[31:0]
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 EMIF-to-16-MBit SGRAM
External Clock /RAS /CAS /BE[3:0] DQM[3:0] A[10] A[9] A[8:0] D[31:0]
ECLKIN ECLKOUT /SDRAS /SDCAS /SDWE
16Mbit SGRAM (512kx32)
External Memory Interface (EMIF)
EA13 EA12 EA[10:2] ED[31:0]
Figure 'C6201/'C6202/'C6701 EMIF-to-32-Mbit SGRAM
CLK* /SDRAS /SDCAS /SDWE /RAS /CAS
32Mbit SGRAM (1Mx32)
External Memory Interface (EMIF)
/BE[3:0]
EA13 EA[11:10] SDA10/EA12** EA[9:2] ED[31:0]
DQM[3:0] A[10:9] A[7:0] D[31:0]
SDCLK 'C6701/'C6701 CLKOUT2 'C6202 ECLKOUT 'C6211/'C6711 (system must provide ECLKIN) SDA10 used 'C6201/'C6202/'C6701 EA12 used 'C6211/'C6711
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Overview `C6000 EMIF
'C6201/'C6202/'C6701 SDRAM Interface Summary
Supports 32-bit-wide SDRAM interface 16-Mbyte spaces Operates 1/2x clock speed Includes three programmable SDRAM controller values (TRC, TRCD, TRP). Other values static. Supports single open page SDRAM each space Column size programmable either 9-column address bits. Four configurations SDRAM supported. Does support SDRAM burst mode. Performs bursts issuing back-to-back commands. 'C6201/'C6701 SDCLK used SDRAM clock. Includes dedicated SDRAM control signals. combination synchronous memory types allowed. 'C6202 CLKOUT2 used SDRAM clock. SDRAM control signals MUXed with SDRAM control signals. Only type synchronous memory allowed system.
'C6211/'C6711 SDRAM Interface Summary
Supports 32-bit, 16-bit, 8-bit-wide SDRAM interfaces 256-Mbyte spaces Clock speed independent internal speed maximum MHz. Very flexible programming SDRAM timing parameters Supports four open pages SDRAM. These different spaces, single space, combination two. program SDRAM configuration (column size, size, bank size). Almost SDRAM configuration used. Supports SDRAM burst mode with 4-word burst ECLKOUT must used synchronous memory clock mirror image ECLKIN. SDRAM control signals MUXed with SBSRAM Async control signals. combination synchronous memory types allowed.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6000 EMIF Signal Descriptions
Figure Figure Figure show block diagrams 'C6201/'C6701, 'C6202, 'C6211/'C6711, respectively. Note that clocks control signals slightly different each three different style EMIFs. signals listed Table describe SDRAM interface shared interface signals.
Figure 'C6201/'C6701 EMIF Block Diagram
CLKOUT1 CLKOUT2 SDCLK Shared external interfaces Hold Interface SDRAM Interface
TMS320C6000 EMIF External SDRAM/SGRAM Interface
interface Data Access Program Access
ED[31:0]
'C6201/ 'C6701
EA[21:2] /CE[3:0] /BE[3:0]
EXTERNAL MEMORY INTERFACE (EMIF)
/SDRAS /SDCAS /SDWE SDA10
/HOLD /HOLDA
Internal peripheral interface
Figure 'C6202 EMIF Block Diagram
CLKOUT1 CLKOUT2
ED[31:0] EA[21:2]
'C6202
/CE[3:0] /BE[3:0]
SDA10
/HOLD /HOLDA
Internal peripheral interface
Figure 'C6211/'C6711 EMIF Block Diagram
CLKOUT1 CLKOUT2 ECLKIN ECLKOUT ED[31:0] EA[21:2] /CE[3:0] Shared external interfaces
'C6211/ 'C6711
Hold Interface /HOLD /HOLDA BUSREQ
Internal peripheral interface
TMS320C6000 EMIF External SDRAM/SGRAM Interface
SDRAM Interface
EXTERNAL MEMORY INTERFACE (EMIF)
/BE[3:0]
Hold Interface
SDRAM Interface
EXTERNAL MEMORY INTERFACE (EMIF)
Shared external interfaces
interface Data Access Program Access
Enhanced Data memory controller
Table 'C6000 EMIF Signal Descriptions: Shared Signals SDRAM Signals
SDRAM Signal DQ[x:0] A[13:0] 'C6201/ 'C6701 Interface ED[31:0] EA[15:2] 'C6202 Signal Interface ED[31:0] EA[15:2] 'C6211/ 'C6711 Interface ED[31:0] EA[15:2] Description
SDA10
SDA10
EA12
DQM[3:0]
/CE0, /CE2, /CE3 /BE[3:0]
/CE0, /CE2, /CE3 /BE[3:0]
/CE0,/CE1 /CE2, /CE3 /BE[3:0]
Data I/O. Byte ED[7:0], Byte ED[15:8], Byte [23:16], Byte ED[31:24]. External address output. Drives bits 15-2 byte address. EA15 maps A13, EA14 maps A12, maps excluding EA12, which treated separately. SDRAM precharge line. Address line/auto-precharge disable SDRAM memory. Serves address (logically equivalent EA12) during ACTV commands also disables auto-precharging function SDRAM during read write operations. Chip enable. must active (low) command clocked into SDRAM. Byte enables. Active-low byte strobes. Individual bytes half-words selected both read write cycles. Decoded from LSBs byte address. /BE0 controls Byte /BE1 controls Byte /BE2 controls Byte /BE3 controls Byte address strobe. Active-low /RAS SDRAM memory interface. Column address strobe. Active-low /CAS SDRAM memory interface. Write enable. Active-low SDRAM memory interface. SDRAM interface clock clock enable. Tied active high when interface EMIF always enable clocking. Define special function. Tied disable special graphic commands SGRAM. With this tied low, SGRAM behaves exactly standard SDRAM.
/RAS
/SDRAS
#SDRAS/ #SSOE #SDCAS/ #SSADS #SDWE/ #SSWE CLKOUT2 3.3V
/CAS
/SDCAS
/SDWE
SDCLK 3.3V
#AOE/ #SDRAS/ #SSOE #ARE/ #SDCAS/ #SSADS #AWE/ #SDWE/ #SSWE ECLKOUT 3.3V
'C6211/'C6711 Byte-Lane Alignment
`C6711 EMIF offers capability interface 32-bit, 16-bit, 8-bit SDRAM. Depending endianness system, different byte lane used SDRAM interface. alignment required shown Figure Note that always corresponds ED[31:24], always corresponds ED[23:16], always corresponds ED[15:8], always corresponds ED[7:0], regardless endianness.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 Byte-Lane Alignment Endianness
'C6211/'C6711
ED[31:24]
ED[23:16]
ED[15:8]
ED[7:0]
Device
Device Endian
Device Little Endian
Device Endian
Device Little Endian
'C6211/'C6711 Clocking
EMIF 'C6211/'C6711 requires external clock provided ECLKIN input. simplicity, CLKOUT2 routed into ECLKIN avoid extra hardware required create clock externally. This method restriction only allowing memory interface 1/2x clock speed 150-MHz device). external clock provided, EMIF operate MHz. 'C6211 'C6711 data sheets specify that rise/fall time externally provided clock must longer than This prove difficult with most off-the-shelf oscillators. recommended approach ICS501 multiplier chip, which produce wide range frequency outputs with standard crystals.
'C6000 Clock-to-Output Relationship
optimize synchronous memory interfaces various 'C6000 devices, output signals triggered different internal clocks 'C6000 DSP. Figure through Figure show clock relationship used various 'C6000 DSPs. Because 'C6211/'C6711 SDRAM interface timed reference externally provided clock, 'C6211 'C6711 data sheets provide tdmax tdmin tosu parameters. fact that tosu parameters factor equations allows user unconcerned about output edge being used internally 'C6000. this way, tosu parameter compared directly against tisu parameter memory given operating speed.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
tdmax tdmin parameters reference actual clock edge 'C6000 from which data driven out. tosu terms notation used 'C6000 data sheets, except those 'C6211 'C6711. tosu term shows setup time rising edge clock. term shows hold time from rising edge memory clock. refers clock period. Notice that data sheet notation directly implies clocking relationship device. example, data sheet 'C6201B SDRAM interface states that tosu 1.5P Referring diagram Figure seen that tdmax relative point from rising edge SDCLK, providing setup time 1.5P tdmax. other 'C6000 data sheets analyzed same way.
Figure 'C6201 'C6201B/'C6701 Output Timing
SDCLK tdmax tdmin tdmax 'C6201 1.5P tdmax tdmax 'C6201B/'C6701 0.5P dmin tdmin tdmin
Figure 'C6202 Output Timing
CLKOUT2 Tosu tdmax tdmax 'C6202 tdmin tdmin
Figure shows clock relationship used 'C6211/'C6711 SDRAM interface. Because this interface timed reference externally provided clock, 'C6211 'C6711 data sheets provide tdmax tdmin tosu parameters.
Figure 'C6211/'C6711 Output Timing
ECLKOUT tdmax 'C6211/'C6711 tdmin
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6000 EMIF Registers
Control EMIF memory interfaces supports maintained through memory-mapped registers within EMIF. memory-mapped registers shown Table
Table 'C6000 EMIF Memory Mapped Registers
Byte Address 0x01800000 0x01800004 0x01800008 0x0180000C 0x01800010 0x01800014 0x01800018 0x0180001C 0x01800020*
Name EMIF global control EMIF space control EMIF space control Reserved EMIF space control EMIF space control EMIF SDRAM control EMIF SDRAM refresh period EMIF SDRAM extension
Applies 'C6211/'C6711 only. Reserved other devices.
EMIF Global Control Register
EMIF global control register configures parameters common spaces (see Figure 18). Table lists only those parameters relevant with SDRAM.
Figure EMIF Global Control Register Diagram
reserved Reserved ARDY HOLD HOLDA NOHOLD SDCEN3 SSCEN3 CLK1EN CLK2EN4 SSCRT34 RBTR83 MAP3 REQ2
description parameters EMIF global control register, TMS320C6201/6701 Peripherals Reference Guide.
Field exists only 'C6211/'C6711. Fields exist 'C6211/'C6711. Fields exist 'C6202.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table EMIF Global Control Register Field Description
Field SDCEN Description SDRAM clock enable (for 'C6201, 'C6701, 'C6202) 'C6201/'C6701: SDCEN=0, SDCLK held high SDCEN=1, SDCLK enabled clock
'C6202:
SDCEN=0, CLKOUT2 held high MemType SDRAM SDCEN=0, CLKOUT2 enabled clock MemType SDRAM
Note that CLK2EN available 'C6202. CLKOUT2 disabled either SSCEN SDCEN, depending MemType used. This possible because only synchronous MemType allowed system.
Space Control Registers
Figure Figure show four space control registers, which correspond four spaces supported EMIF. MTYPE field identifies memory type corresponding space. MTYPE selects SDRAM SBSRAM, remaining fields register apply. asynchronous type selected (ROM asynchronous), remaining fields specify shaping address control signals access that space. only field interest SDRAM MTYPE field. Modification space control register should done until that space inactive.
Figure 'C6201/'C6202/'C6701 EMIF Space Control Register Diagram
WRITE SETUP +1111 Reserved WRITE STROBE +111111 READ STROBE +111111 WRITE HOLD MTYPE +010 READ SETUP +1111 Reserved READ HOLD
Figure 'C6211/'C6711 EMIF Space Control Register Diagram
WRITE SETUP +1111 WRITE STROBE +111111 READ STROBE +111111 WRITE HOLD READ SETUP +1111 MTYPE Write Hold READ HOLD +010 +011
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 'C6000 EMIF Space Control Register Field Description SDRAM
Field Mtype Description Memory Type devices: MTYPE 0011b: 32-bit-wide SDRAM 'C6211/'C6711 only: MTYPE 1000b: 8-bit-wide SDRAM MTYPE 1001b: 16-bit-wide SDRAM
SDRAM Control Register
SDRAM control register controls SDRAM parameters spaces that specify SDRAM memory type MTYPE field associated space control register (see Figure 21). Because SDRAM control register controls SDRAM spaces, each space must contain SDRAM with same timing page characteristics. timing fields EMIF SDRAM control register terms EMIF clock period. 'C6201, 'C6202, 'C6701, tcyc twice period because SDCLK CLKOUT2 1/2x frequency. 'C6211 'C6711, tcyc equals ECLKOUT period.
Figure EMIF SDRAM Control Register
SDBSZ
INIT
TRCD
SDRSZ Reserved
SDCSZ RFEN SDWID
+0100
+1000
Reserved
+1111 Refers 'C6211/'C6711 only Refers 'C6201/'C6202/'C6701 only
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table EMIF SDRAM Control Register Field Description
Field TRCD INIT Description Specifies value SDRAM EMIF clock cycles. (tRC tcyc) Specifies value SDRAM EMIF clock cycles. (tRP tcyc) Specifies tRCD value SDRAM EMIF clock cycles. TRCD (tRCD tcyc) Forces initialization SDRAM present. INIT effect. INIT initialize SDRAM each space configured SDRAM. Refresh enable. RFEN SDRAM refresh disabled. RFEN SDRAM refresh enabled. SDRAM width select. SDWID=0, page size words (9-column address pins) SDWID=1, page size words (8-column address pins) SDRAM column size. SDCSZ 9-column address pins SDCSZ 8-column address pins SDCSZ 10-column address pins SDCSZ reserved SDRAM size SDRSZ address pins SDRSZ address pins SDRSZ address pins SDRSZ reserved SDRAM bank size SDBSZ banks bank select pin) SDBSZ four banks bank select pins)
RFEN
SDWID
SDCSZ
SDRSZ
SDBSZ
SDWID applies 'C6201/'C6202/'C6701 only. SDCSZ, SDRSZ, SDBSZ apply 'C6211/'C6711 only.
SDRAM Timing Register
SDRAM timing register controls refresh PERIOD SDRAM terms EMIF clock cycles, tcyc. tcyc twice clock period 'C6201/'C6202/'C6701. tcyc equal ECLKOUT period 'C6211/'C6711. When counter reaches zero, automatically reloaded with PERIOD continues decrementing. 'C6211/'C6711 control number refreshes performed when refresh counter expires XRFR field. four refreshes performed when refresh counter expires. This field useful because 'C6211/'C6711 does differentiate between trickle urgent refreshes. When refresh counter expires, 'C6211/'C6711 EMIF interrupts accesses soon possible execute required number refreshes.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure EMIF SDRAM Refresh Period
Reserved
COUNTER
+0000 0100 0000 +0101 1101 1100
PERIOD
+0000 0100 0000 +0101 1101 1100
XRFR
R,+0 Applies 'C6201/'C6202/'C6701 only Applies 'C6211/'C6711 only
Table EMIF SDRAM Refresh Period Field Description
Field PERIOD COUNTER XRFR
Description Refresh period CLKOUT2 cycles Refresh period ECLKOUT cycles Current value refresh counter. Extra refreshes: controls number refreshes performed SDRAM when refresh counter expires
Applies 'C6201/'C6202/'C6701 only Applies 'C6211/'C6711 only
'C6211/'C6711 SDRAM Extension register
SDRAM extension register 'C6211/'C6711 allows programming many SDRAM timing parameters. This programmability allows 'C6211/'C6711 interface wide variety SDRAMs. Also, timing register allows interface tweaked characteristics specific SDRAM rather than default parameters that generally apply worst-case parameters broad range SDRAMs. SDRAM extension register applies SDRAM memory spaces system, SDRAMs with identical timing characteristics must used. Alternatively, register programmed according worst-case timings SDRAMs system that system works correctly.
Figure 'C6211/'C6711 SDRAM Extension Register
Reserved
WR2RD RW,+0
RW,+0
RW,+1
WR2DEAC RW,+11
WR2WR R2WDQM
R2WDQM RW,+1
RD2WR RW,+111
RD2RD RW,+0
THZP TW,+11
RW,+11
TRRD RW,+1
TRAS RW,+111
RW,+1
RD2DEAC RW,+11
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 'C6211/'C6711 EMIF SDRAM Extension Register Field Description
Field Description Specified latency SDRAM ECLKOUT cycles latency ECLKOUT cycles latency ECLKOUT cycles Specifies tRAS value SDRAM ECLKOUT cycles TRAS tRAS Specifies tRRD value SDRAM ECLKOUT cycles TRRD then tRRD ECLKOUT cycles TRRD then tRRD ECLKOUT cycles Specifies value SDRAM ECLKOUT cycles Specifies tHZP value SDRAM ECLKOUT cycles THZP tHZP Specifies number cycles between READ READ command (same space) SDRAM ECLKOUT cycles RD2RD READ READ ECLKOUT Cycle RD2RD READ READ ECLKOUT Cycle Specifies number cycles between READ DEAC/DCAB SDRAM ECLKOUT cycles RD2DEAC cycles READ DEAC/DCAB) Specifies number cycles between READ WRITE command SDRAM ECLKOUT cycles RD2WR cycles READ WRITE) Specifies number cycles that signals must high preceding WRITE interrupting READ R2WDQM cycles high) Specifies minimum number cycles between WRITE WRITE command SDRAM ECLKOUT cycles WR2WR cycles WRITE WRITE) Specifies minimum number cycles between WRITE DEAC/DCAB command SDRAM ECLKOUT cycles WR2DEAC cycles WRITE DEAC/DCAB) Specifies minimum number cycles between WRITE READ command SDRAM ECLKOUT cycles WR2RD cycles WRITE READ)
TRAS TRRD
THZP RD2RD
RD2DEAC
RD2WR
R2WDQM
WR2WR
WR2DEAC
WR2RD
SDRAM
SDRAM Commands
EMIF supports SDRAM commands described Table These commands detailed following sections.
Table EMIF SDRAM Commands
Command ACTV READ REFR DCAB DEAC
Function Activate selected bank select row. Input starting column address begin read operation. Input starting column address begin write operation. Mode register set. Configure SDRAM mode register. Auto refresh cycle with internal address Deactivate (also known precharge) banks. Deactivate single bank. Selected bank-select address outputs.
DEAC supported 'C6211/'C6711 only.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table Truth Table SDRAM Commands
Command ACTV READ REFR DCAB DEAC
/RAS
/CAS (/SDCAS)
(/SDWE)
A13-A11; A9-A0 (EA15-13; EA11-EA2) Bank select/row address Column address Column address Mode Bank select/X
(SDA10/EA12) address
(/CE)
(/SDRAS)
SDA10 used 'C6201/'C6202/'C6701. EA12 used 'C6211/'C6711. DEAC supported 'C6211 only.
Timing Requirements
Several SDRAM timing parameters decouple EMIF from SDRAM speed limitations. 'C6201B/'C6202/'C6701, three these parameters programmable EMIF SDRAM control register; remaining assumed static values, shown Table three programmable values assure that EMIF control SDRAM obeys these minimum timing requirements. Consult manufacturer's data sheet particular SDRAM.
Table 'C6201/'C6202/'C6701 SDRAM Timing Parameters
Parameter tRCD tRAS tnEP
Note:
Description REFR command ACTV, MRS, subsequent REFR command ACTV command READ command DCAB command ACTV, MRS, REFR command ACTV command DCAB command Overlap between read data DCAB command
Value EMIF Clock Cycles TRCD
Cycles shown following timing diagrams have TRCD (tRCD CLKOUT2 cycles).
`C6211/'C6711 additional programmable timing parameters programmable SDRAM control register SDRAM extension register. These parameters superset parameters `C6201/'C6202/'C6701. Consult manufacturer's data sheet particular SDRAM.
designator parentheses EMIF signal; preceding designator SDRAM signal connected
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 'C6211/'C6711 SDRAM Timing Parameters
Parameter tRCD tRAS tRRD tHZP Description REFR command ACTV, MRS, subsequent REFR command ACTV command READ command DCAB/DEAC command ACTV, MRS, REFR command Latency SDRAM ACTV command DEAC/DCAB command ACTV bank ACTV bank (same space) Write recovery, time from last data 'C6000 (write data) DEAC/DCAB command High from precharge, time from DEAC/DCAB SDRAM outputs (read data) high Value EMIF Clock Cycles TRCD TRAS TRRD THZP
'C6211/'C6711 also allows user program other functional parameters SDRAM controller. These parameters explicitly spelled timing parameters data sheet, user must ensure that parameters programmed valid value. most common SDRAMs, following values used. user must ensure that these values appropriate specific SDRAM.
Table 'C6211/'C6711 Recommended Values Parameters
Parameter Description Value EMIF Suggested clock cycles value CL=2 RD2RD RD2RD Suggested value CL=3 RD2RD
READ READ READ DEAC READ WRITE
READ command READ command. Used interrupt READ burst random READ addresses Used conjunction with tHZP. Specifies minimum amount time between READ command DEAC/DCAB command READ WRITE command. value programmed this parameter depends READ WRITE should latency plus cycles EMIF clock cycles) provide turnaround cycle before WRITE command. Specifies number cycles that outputs should high before write allowed interrupt read. This related READ WRITE parameter. Number cycles between WRITE interrupting WRITE. Used random WRITEs. Number cycles between WRITE command DEAC/DCAB command Number cycles between WRITE command READ command
RD2DEAC
RD2DEAC
RD2DEAC
RD2WR
RD2WR
RD2WR
high before write interrupting read WRITE WRITE WRITE DEAC WRITE READ
R2WDQM
R2WDQM
R2WDQM
WR2WR
WR2WR
WR2WR
WR2DEAC WR2DEAC WR2DEAC WR2RD WR2RD WR2RD
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Deactivation (DCAB DEAC)
DCAB command issued close active page memory. SDRAM deactivation (DCAB) performed after hardware reset when INIT=1 EMIF SDRAM control register. This cycle required SDRAMs prior REFR MRS. 'C6201/'C6202/'C6701, DCAB also issued when page boundary crossed. During DCAB command, SDA10 (for 'C6201/'C6202/'C6211) EA12 ('C6211/'C6711) driven high ensure that SDRAM banks deactivated. 'C6211 does issue DCAB page crossing within bank, uses DEAC command (shown Figure 25). This because 'C6211 ability have more than page open space simultaneously. DEAC command allows 'C6211 close only desired page.
Figure SDRAM DCAB-Closes Banks Space
DCAB Clock /CEx /BE[3:0] EA[15:2] ED[31:0] SDA10/EA12 /SDRAS /SDCAS /SDWE
Figure 'C6211/'C6711 SDRAM DEAC-Closes Single Bank Specified
DEAC ECLKOUT /CEx /BE[3:0] EA[15:13] EA12 EA[11:2] ED[31:0] /SDRAS /SDCAS /SDWE Bank Select
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Activate (ACTV)
Activate (ACTV) command issued before read write SDRAM. ACTV command opens page memory, allowing future accesses (reads writes) with minimum latency. shown Figure Figure when ACTV command issued EMIF, delay tRCD incurred before read write command issued this example, tRCD EMIF clock cycles.) Reads writes currently active bank SDRAM achieve much higher throughput than reads writes random areas because every time page accessed, ACTV command must issued.
SDRAM Read (READ)
SDRAM read, selected bank activated with address during ACTV command. this example, three read commands performed three successive column addresses same page.
'C6201/'C6202/'C6701 Read
'C6201/'C6202/'C6701 EMIF uses latency burst length three-cycle read latency causes data appear three cycles after corresponding column address, shown Figure Refresh cycle access different page memory required, DCAB cycle performed following last column access deactivate bank. idle cycle inserted between final read command DCAB command meet SDRAM timing requirements. transfer data completes during past DCAB command (controlled tnEP). access pending, DCAB command performed until page information becomes invalid.
Figure 'C6201/'C6202/'C6701 SDRAM Read-CAS Latency
tRCD cycles ACTV Clock /CEx /BE[3:0] EA[15:2] ED[31:0] SDA10/EA12 /SDRAS /SDCAS /SDWE Address Bank Activate/Row Latency cycles C6000 Latches data Read Read Read
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6211/'C6711 Read
'C6211/'C6711 EMIF programmed latency either three cycles. burst length fixed four words both reads writes. general, using faster latency results slightly slower timings SDRAM device. This require running EMIF slower clock frequency. Depending requirements system, this acceptable. example shown Figure three-word read uses latency three cycles. three-cycle read latency causes data appear three cycles after corresponding column address. This example assumes that accesses pending SDRAM. this case, allowed driven SDRAM, 'C6000 ignores this data because only three words required this example. access pending, DEAC command performed until page information becomes invalid.
Figure 'C6211/'C6711 SDRAM Read-CAS Latency
tRCD cycles ACTV Clock /CEx /BE[3:0] EA[15:2] ED[31:0] EA12 /SDRAS /SDCAS /SDWE Address Bank Activate/Row Addre Latency cycles C6000 Latches data Read ignor
Bank/Column
refresh cycle pending, DCAB cycle will performed deactivate bank. access different page memory same bank SDRAM required (that page miss), DEAC command will issued following last column access, followed ACTV open correct page. DEAC/DCAB command timing controlled THZP RD2DEAC. These parameters ideally programmed that transfer data completes during after DCAB/DEAC command. example Figure shows same example shown Figure with access pending different page same bank. With THZP (tHZP cycles) DEAC command issued same time latched, causing outputs SDRAM stop driving data before This good because only three words were needed. Because next access same bank SDRAM, ACTV command issued soon possible controlled parameter, which three cycles this example.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 SDRAM Read With DEAC
tHZP cycles cycles DEAC C6000 Latches data
tRCD cycles
Latency cycles
ACTV Clock /CEx /BE[3:0] EA[15:2] ED[31:0] EA12 /SDRAS /SDCAS /SDWE Address Bank Activate/Row Addre
Read
Bank/Column
Bank Bank Activate
SDRAM Write (WRT)
SDRAM write, selected bank activated with address during ACTV command. this example, three write commands performed three successive column addresses same page.
'C6201/'C6202/'C6701 SDRAM Writes
SDRAM writes have burst length bank activated with address during ACTV command. There latency writes data output same cycle column address. Byte half-word writes enabled appropriate inputs. Following final write command, idle cycle inserted meet SDRAM timing requirements. required, bank then deactivated with DCAB command memory interface begin page access. access pending, access pending same page, DCAB command performed until page information becomes invalid.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6201/'C6202/'C6701 SDRAM Burst Length Write
tRCD cycles ACTV Clock /CEx /BE[3:0] /EA[15:2] /ED[31:0] SDA10 /SDRAS /SDCAS /SDWE Address Bank Activate/Row Address WRITE WRITE WRITE
'C6211/'C6711 SDRAM Writes
'C6211/'C6711, SDRAM writes have burst length bank activated with address during ACTV command. There latency writes data output same cycle column address. Byte half-word writes enabled appropriate inputs. less than four-word burst required, write data masked /BEx outputs (tied inputs SDRAM). Following final write command, idle cycles inserted according TWR, WR2DEAC, and/or WR2RD parameters meet SDRAM timing requirements. refresh pending, banks then deactivated with DCAB command. page miss occurred, DEAC command issued followed ACTV correct page. DEAC/DCAB command performed until page information becomes invalid.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure 'C6211/'C6711 SDRAM Burst Length Write
tRCD cycles ACTV ECLKOUT /CEx /BE[3:0] /EA[15:2] /ED[31:0] EA12 /SDRAS /SDCAS /SDWE Address Bank Activate/Row Address Bank/Column WRITE blocked
Mode Register (MRS)
mode register located external SDRAM memory that dictates operating characteristics. When initializing SDRAM, EMIF must this register value described here before normal read write accesses occur. EMIF automatically performs DCAB command followed eight refreshes, followed command whenever INIT field EMIF SDRAM control register set. INIT device reset user write. with DCAB REFR commands, commands sent spaces configured SDRAM. Following cycle, INIT cleared prevent multiple cycles. 'C6201/'C6202/'C6701 EMIF always uses mode register value 0x0030 during command. 'C6211/'C6711 uses value either 0x0032 0x0022, depending latency interface. Figure shows mapping between mode register bits, EMIF pins, mode register value. Table shows SDRAM configuration selected this mode register value.
Figure Mode Register Value
Mode Register EMIF Pins EA15 EA14 EA13 SDA10 EA11 EA10 Field Reserved Write Reserved Burst Length '6201/'C6202/ `C6701 'C6211/'C6711 w/CL=3 'C6211/'C6711 w/CL=2 Read Latency Burst Length
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table Implied SDRAM Configuration Value
Field Write burst length Read latency Serial/interleave burst type Burst length 'C6201/'C6202/' 'C6211/'C6711 C6701 Selection Selection (CL=3) Serial Serial 'C6211/'C6711 Selection (CL=2) Serial
Figure SDRAM Mode Register Set: Command
Clock /CEx /BE[3:0] EA[15:2] ED[31:0] SDA10/EA12 /SDRAS /SDCAS /SDWE value
Refresh
RFEN SDRAM control register shown Figure selects SDRAM refresh mode EMIF. value RFEN field disables EMIF refreshes; user must ensure that refreshes implemented external device. value RFEN field enables EMIF perform refreshes SDRAM described this section. refresh command (REFR) sent spaces configured SDRAM MTYPE field corresponding space control register. REFR automatically preceded DCAB command. This ensures that spaces selected with SDRAM deactivated before refresh occurs. Page information always invalid before after REFR command; thus refresh cycle always forces page miss next access.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure SDRAM Refresh
REFR Clock /CEx /BE[3:0] EA[15:2] ED[31:0] SDA10/EA12 /SDRAS /SDCAS /SDWE
'C6201/'C6202/'C6701 Refresh Operation
Following DCAB command, EMIF begins performing trickle refreshes rate defined PERIOD value EMIF SDRAM control register, provided other SDRAM access pending. SDRAM interface monitors number refresh requests posted performs them. Within EMIF SDRAM control block, 2-bit counter monitors backlog refresh requests. counter increments once each refresh request decrements once each refresh cycle performed. counter saturates values reset, counter automatically ensure that several refreshes occur before accesses begin. value indicates urgent refresh condition, causing page information register invalidated forcing controller close current SDRAM page. Thus, EMIF SDRAM controller performs three REFR commands, decrementing counter following DCAB command before proceeding with remainder current access. SDRAM present multiple spaces, DCAB-refresh sequence occurs spaces containing SDRAM. During idle times SDRAM interface(s), request pending from EMIF, SDRAM interface performs REFR commands long counter value nonzero. This feature reduces likelihood having perform urgent refreshes during actual SDRAM accesses later. Note that SDRAM present multiple spaces, this refresh occurs only interfaces idle with invalid page information.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6211/'C6711 Refresh Operation
'C6211/'C6711 EMIF does concept urgent versus trickle refresh. refresh requests considered high priority. refresh request pending, transfers progress allowed complete, required number refreshes issued (controlled XRFR field). XRFR field allows four requests issued succession each time refresh counter expires. This gives system designer allowing requests happen less often while still meeting requirements SDRAM.
SDRAM Initialization
EMIF performs necessary functions initialize SDRAM spaces configured SDRAM. SDRAM initialization requested write INIT EMIF SDRAM control register (see Figure 21). This should done SDRAM access occurring. actual sequence events initialization follows:
DCAB command spaces configured SDRAM Eight REFR commands command spaces configured SDRAM
Monitoring Page Boundaries
Because SDRAM paged memory type, EMIF SDRAM controller monitors active SDRAM that boundaries crossed during course access. accomplish this monitoring, EMIF stores address open page performs compares against that address subsequent accesses SDRAM bank.
'C6201/'C6202/'C6701 Page Boundaries
'C6201/'C6701/'C6202 allows single page open each space. number address bits compared function page size programmed SDWID field EMIF SDRAM control register. SDWID SDRAM control register, EMIF expects spaces configured SDRAM have page sizes words. Thus, logical byte address bits compared 25:11. SDWID EMIF expects spaces with SDRAM have SDRAMs that have page sizes 256. Thus, logical byte address bits compared 25:10.
Note that upper address bit, both 8-bit- 16-bit-wide SDRAM used indicate logical address range accessible EMIF, that CE3, which address 0x03FFFFFF. Thus, logical address lines (0:25) needed.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
page boundary crossed during course access,, EMIF performs DCAB command starts access. Note that simply ending current access condition that forces active SDRAM closed. EMIF speculatively leaves active open until becomes necessary close This feature decreases deactivate-reactivate overhead allows interface fully capitalize address locality memory accesses.
'C6211/'C6711 Page Boundaries
'C6211/'C6711 allows four pages open simultaneously. Open pages distributed across spaces located same space. example, pages open four pages open CE0. maximum number open pages single space limited number banks SDRAM, which programmed into SDBSZ field. Only page open bank time. combination SDCSZ, SDRSZ, SDBSZ control which logical address bits compared determine page open. example, typical 2-bank 512K 16-bit SDRAM settings banks, eleven address bits, eight column address bits. 32-bit-wide SDRAM access uses logical address bits A[9:2] (two-bit offset word addressing) specify column being accessed (that address within page). Bits A[20:10] specify offset (that page within bank) A[21] specifies bank. Logical address bits A[31:28] determine space used. page boundary crossed during access same bank space, 'C6711/'C6711 performs DEAC command starts access. access different bank performed, 'C6211/'C6711 EMIF does always close first page. Each bank SDRAM space simultaneously have open page pages closed with random replacement strategy. page miss occurs access bank that currently page open, that bank must closed open correct page. However, access occurs bank that does have page open, four page registers use, four pages randomly closed with DEAC command, page opened. example, assume that SDRAM that banks (such 2-bank 512K 16-bit device) CE0. Therefore, CE0, Bank0 CE0, Bank1 simultaneously have open pages. Assume Bank0 open page Bank1 does not. access Bank0 results page miss, that page must closed before correct page Bank0 opened. access Bank1 must first open correct page. four page registers internal 'C6000 (assume that other spaces have open pages), single page closed random correct page CE0, Bank1 opened. four page registers use, CE0, Bank1, Pagex opened immediately.
Figure Logical Address Breakdown Bank Bit, Bits, Column Bits
(Page within bank) space Bank Address (Address within Page) Column Address byte
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Address Shift
Because same EMIF pins address column address, EMIF interface appropriately shifts address column address selection. Table shows translation between bits logical byte address they appear pins column addresses. SDRAMs address inputs control well address. With this consideration, following items clarify figure:
address line that corresponds SDRAM's bank-select latched internally SDRAM controller. This ensures that bank select remains correct during READ commands. Thus, EMIF maintains these values shown both column addresses. EMIF forces precharge disable (SDA10 `C6201/'C6202/'C6701, EA12 'C6211/'C6711) unless /RAS active low, high during DCAB commands page accesses. This prevents auto precharge from occurring following READ command.
Table 'C6201/'C6202/'C6701 Byte Address Mapping SDRAM CAS7
SDRAM SDWID DRAM Width Command SDRAM Pins EMIF Pins Address Address Legend: internally latched during ACTV command. Reserved future use. Undefined.
EA21- EA17
values indicate byte address present corresponding during cycle.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table 'C6211/'C6711 Byte Address Mapping SDRAM CAS8
Column DRAM Size Command SDRAM Pins EMIF Pins Address Address Address Legend: internally latched during ACTV command. Reserved future use. Undefined.
EA21- EA17
Timing Constraints
This section discusses timing constraints used determine SDRAM operate with 'C6000 given clock frequency. following constraint calculations, time margin calculated representing margin system after taking into account worst-case numbers from memory 'C6000 data sheets. After calculating time tmargin, system-level issue determine proper amount margin been met. required timing margin extremely system dependent, depending primarily trace length loading, other factors come into play. Therefore, this parameter should determined particular system question. general, timing margin required same different parameters read/write cycles. output signals, required timing margin minimal because output clock output control/data signals both propagate from 'C6000 SDRAM. Therefore, timing margin must account possible skew between signals (clock versus control/data) caused loading effects differences route length. example, signals board manufactured with 0.5-ounce copper traces exhibit propagation delay time ~0.17 inch. skew between clock output signals inches, required board margin ~0.5 both output setup hold. This does consider settling time effects other loading issues that should considered when determining amount margin required.
values indicate byte address present corresponding during cycle.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
timing margin required reads more complicated. issue with reads that memory outputting data relative clock that undergone propagation delay when traveling from 'C6000 SDRAM. memory outputs data time tacc from this delayed clock. output data from memory undergoes delay itself before arriving 'C6000 DSP. Therefore, timing margin read setup must account these propagation delays. read hold time improved because this margin required considered negligible. Using same board characteristics previously used, this implies that both clock data paths approximately inches long, round-trip propagation delay clock SDRAM data back 'C6000 approximately inches ps/inch). Therefore, margin required reads this example least input setup time input hold time. This does consider settling time effects other loading issues that should considered when determining amount margin required. These numbers guidelines. actual margin required system might different. following discussion, used denote memory specifications. additional designators used denote 'C6000 timing specifications.
'C6000 Outputs (ED, SDCAS, SDRAS, SDWE)
'C6201/'C6701/'C6202 Output Comparison
simplicity, 'C6201, 'C6701, 'C6202 data sheets specify outputs setup time (tosu) next rising edge hold time (toh) from previous rising edge. Thus, comparison between 'C6000 specifications memory specifications extremely straightforward. This also allows user unconcerned with which clock edge triggers output data. following equations derived from Figure calculate timing margin between 'C6000 desired SDRAM.
Setup time: output setup time (tosu) from inactive active must provide ample setup time (tisu(m)) input. Therefore, margin available tmargin tosu tisu(m) Hold time: output hold time from active inactive must greater than hold time required input (tih(m)). margin then: tmargin tih(m)
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Figure Outputs From 'C6201/'C6202/'C6701 (Write Data [ED], Control, Address Signals)
Tcyc EMIF Clock tosu tisu(m) 'C6000 Output
SBSRAM Latches Signal Tcyc
tih(m)
'C6211/'C6711 Output Comparison
'C6211 'C6711 data sheets specify outputs minimum delay maximum delay from rising edge ECLKOUT. When comparing these parameters against specification particular SDRAM, maximum delay (tdmax) used verify that input setup time (tis(m)) memory met. minimum delay (tdmin) used verify that input hold time (tih(m)) memory met. following equations derived from Figure calculate timing margin between 'C6211/'C6711 desired SDRAM.
Setup time: maximum (tdmax) from clock output signal valid must provide ample setup time (tisu(m)) input. Therefore, margin available tmargin tcyc (tdmax tisu(m)) Hold time: minimum dela (tdmin) from clock output signal invalid must greater than hold time required input ih(m)). margin then: tmargin tih(m)
Figure Outputs From 'C6211/'C6711 (Write Data [ED], Control, Address Signals)
Tcyc EMIF Clock
SBSRAM Latches Data Tcyc
tdmax 'C6000 Outputs
tih(m) tisu(m) tdmin
TMS320C6000 EMIF External SDRAM/SGRAM Interface
'C6000 Inputs (Output Data From SDRAM, Read
Figure shows output data from SDRAM occurs during read cycle. situation similar outputs from 'C6000 except that SDRAM must provide ample setup input hold 'C6000. constraints expressed follows:
Setup times: access time acc(m)) SDRAM must provide large enough input setup time (tsu) input 'C6000. tmargin tcyc (tacc(m) tsu) Hold times: output hold (toh(m)) data output from SDRAM, must provide hold time greater than hold time required input (tih) 'C6000. tmargin toh(m)
Figure Input 'C6000 (Read Data)
Tcyc EMIF Clock tacc(m) Read Data
'C6x Latches Data Tcyc
toh(m)
Timing Comparisons Three SDRAMs
This section summarizes comparisons listed above three different SDRAMs with three different 'C6000 devices. Although every 'C6000 device shown following examples, approach same current 'C6000 devices. following examples, notice that more margin achieved with faster memory. example, 100-MHz interface desired, 125-MHz SDRAM will provide more margin than 100-MHz SDRAM. Although 'C6000 DSPs designed operate with SDRAMs rated speeds, sometimes extra margin worth extra cost faster memories. Several vendors have SDRAM devices available faster. newest data sheets should compared 'C6000 data sheet verify operation with desired margins.
'C6201B Micron's MT48LC4M16A2-10
MT48LC4M16A2 device 64-Mbit 16-bit device, which results addressable space Mbytes with devices parallel. This example uses 'C6201B-200 running maximum clock speed this example, EMIF clock, SDCLK, operates 1/2x speed, resulting Tcyc
TMS320C6000 EMIF External SDRAM/SGRAM Interface
timing parameters MT48LC4M16A2-10 'C6201B-200 summarized follows:
'C6201B-200 Outputs Inputs Tosu 1.5P 0.5P Tisu MT48LC4M16A2-10 Inputs Outputs Tisu Tacc
Tosu Tisu
Tmargin
Tcyc Tacc tisu
'C6202 Micron's MT48LC1M16A1-8
MT48LC1M16A1-8 16-Mbit 16-bit device. 'C6202 interface, these devices used parallel, resulting addressable space MBytes. This example uses 'C6202-250 running maximum clock speed ns). Because 'C6202 EMIF uses CLKOUT2 (which 1/2x speed) synchronous memory interfaces, Tcyc timing parameters MT48LC1M16A1-8 'C6202-250 summarized follows:
'C6202-250 Outputs Tosu Tisu MT48LC1M16A1-8 Inputs Tisu Tacc Tmargin Tosu Tisu
Inputs
Outputs
Tcyc Tacc tisu
'C6711 Micron's MT48LC16M8A2-8
MT48LC16M8A2-8 128-Mbit 8-bit device, which results addressable space MBytes. This example uses 'C6711-150 running maximum clock speed 6.67 ns). Because speed independent EMIF clock speed, externally provided clock synchronous memory interface, resulting Tcyc timing parameters MT48LC16M8A2-8 'C6711-150 summarized follows:
'C6711-150 Outputs Inputs Tdmax Tdmin Tisu MT48LC16M8A2-8 Inputs Outputs Tisu Tacc Tmargin Tcyc Tdmax Tisu Tdmin
Tcyc Tacc tisu
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Complete Example Using 'C6201B Micron's MT48LC4M16A2-10
This section walks through register configuration interfacing 'C6201B with Micron's MT48LC4M16A2-10, which 512K 16-bit 4-bank SDRAM capable operating MHz. additional timing margin needed, this device available provides additional timing margin. Because memory bits wide, devices parallel complete 32-bit word, giving total addressable space MBytes. block diagram interface schematic identical that shown Figure Assumptions:
CLKOUT1 frequency 100-MHz SDRAM clock frequency. (SDCLK CLKOUT2 CLKOUT1 frequency) Tcyc SDRAM located (logical address 0x02000000) Driven SDCLK SSCLK CLKOUT1 used other memory system CLKOUT2 system
Register Configuration 'C6201B MT48LC4M16A2
Table SDRAM Registers
Register Name EMIF global control EMIF space control EMIF SDRAM control EMIF SDRAM timing Fields Required SDCEN, CLK2EN, SSCEN, CLK1EN MTYPE TRC, TRP, TRCD, INIT, RFEN, SDWID PERIOD
EMIF Global Control Registers 'C6201B MT48LC4M16A2
Because MT48LC4M16A2-10 SDRAM driven SDCLK, must then following:
Figure EMIF Global Control Register Diagram 'C6201B MT48LC4M16A2
Reserved Reserved /ARDY /HOLD /HOLDA NOHOLD SDCEN SSCEN CLK1EN CLK2EN SSCRT RBTR8
Note: SDCEN indicates that SDCLK enabled clock because assume driving SDRAM interface. SSCEN indicates that SSCLK enabled because assume system. CLK1EN indicates that SSCLK enabled because assume system. CLK2EN indicates that CLKOUT2 disabled because assume system.
Thus, valid setting EMIF global control register 0x00003371.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
additional information remainder fields, TMS320C6000 Peripherals Reference Guide.
EMIF Space Control Register 'C6201B MT48LC4M16A2
Figure EMIF Space Control Register Diagram 'C6201B MT48LC4M16A2
WRITE SETUP 1111 READ STROBE 111111 WRITE STROBE 111111 MTYPE WRITE HOLD READ SETUP 1111 Reserved READ HOLD
MTYPE indicates that 32-bit-wide SDRAM located address space. rest fields irrelevant because they refer asynchronous memory SDRAM configured this space. valid setting EMIF space control 0xFFFFFF33.
EMIF SDRAM Control Register 'C6201B MT48LC4M16A2
SDRAM control register, values must actually calculated based clock frequency used (100 this example, tCYC 10ns) parameters SDRAM used. Table summarizes values.
Table Timing Parameter Calculation SDRAM Control Register 'C6201B MT48LC4M16A2
Field Name TRCD Formula Value from Micron Data Sheet tRC=90 (min) (min) tRCD (min) Value Calculated Field TRCD Value Recommended
(tRC tCYC) (tRP tCYC) TRCD (tRCD tCYC)
Figure EMIF SDRAM Control Register 'C6201B MT48LC4M16A2
Reserved
SDWID
RFEN
INIT
TRCD
0010
0010
00000
1000
Reserved
000000000000
Note: SDWID indicates that wide SDRAM used. RFEN indicates that SDRAM refresh enabled. INIT forces initialization SDRAM. TRCD 0010b from previous calculation. 0010b from previous calculation. 1000b from previous calculation
Based above calculations, value 0x07228000 should written EMIF SDRAM control register.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
EMIF SDRAM Refresh Period 'C6201B MT48LC4M16A2
Table Period Calculation SDRAM Refresh Period 'C6201B MT48LC4M16A2
Field Name PERIOD Formula PERIOD tRefresh/tCYC Value from TMS626812B Data Sheet tRefresh 4096 Value Calculated Field Period 0x61A cycles
Figure EMIF SDRAM Refresh Period 'C6201B MT48LC4M16A2
Reserved
COUNTER
0000 0000 0000 +0000 0100 0000
PERIOD
0110 0001 1010 (0x61A) +0000 0100 0000
00000000 Note: Period 0x61A from previous calculation.
Based this result, value 0x61A should written EMIF SDRAM refresh period register.
Complete Example Using 'C6211 Micron's MT48LC16M8A2-8
This section walks through register configuration interfacing 'C6211 with Micron's MT48LC16M8A2-8, which 8-bit 4-bank SDRAM capable operating MHz. Because memory bits wide, four devices parallel complete 32-bit word, total addressable space MBytes. block diagram interface schematic identical that shown Figure except that ECLKOUT used memory clock, EA12 used instead SDA10. This 125-MHz SDRAM featured because offers additional timing margin compared typical 100-MHz SDRAMs used system that requires extra margin. Assumptions:
100-MHz SDRAM clock frequency. (ECLKIN ECLKOUT MHz). Tcyc SDRAM located (logical address 0xB0000000) CLKOUT1 CLKOUT2 system
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Register Configuration 'C6211 MT48LC16M8A2
Table SDRAM Registers 'C6211 MT48LC16M8A2
Register Name EMIF global control EMIF space control EMIF SDRAM control EMIF SDRAM timing EMIF SDRAM extension Fields Required CLK1EN, CLK2EN MTYPE TRC, TRP, TRCD, INIT, RFEN, SDCSZ, SDRSZ, SDBSZ PERIOD
EMIF Global Control Registers 'C6211 MT48LC16M8A2
Because none programmable clocks system, must following:
Figure EMIF Global Control Register Diagram 'C6211 MT48LC16M8A2
Reserved Reserved Reserved /ARDY /HOLD /HOLDA NOHOLD Reserved CLK1EN CLK2EN
Note: CLK1EN indicates that SSCLK enabled because assume system. CLK2EN indicates that CLKOUT2 disabled because assume system.
Thus, valid setting EMIF global control register 0x00003300. additional information remainder fields, TMS320C6000 Peripherals Reference Guide.
EMIF Space Control Register 'C6211 MT48LC16M8A2
Figure EMIF Space Control Register Diagram 'C6211 MT48LC16M8A2
WRITE SETUP 1111 READ STROBE 111111 WRITE STROBE 111111 WRITE HOLD READ SETUP 1111 Reserved READ HOLD
MTYPE 0011
Note: MTYPE 0011 indicates that 32-bit-wide SDRAM located address space. rest fields irrelevant because they refer asynchronous memory SDRAM configured this space.
valid setting EMIF space control 0xFFFFFF33.
EMIF SDRAM Control Register 'C6211 MT48LC16M8A2
SDRAM control register, values must actually calculated based clock frequency used (100 this example, tCYC 10ns) parameters SDRAM used. Table summarizes values.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Table Timing Parameter Calculation SDRAM Control Register 'C6211 MT48LC16M8A2
Field Name TRCD Formula Value From Value Calculated KM416S4030 Data Field Sheet tRC=70 (min) (min) tRCD (min) TRCD Value Recommended
(tRC tCYC) (tRP tCYC) TRCD (tRCD tCYC)
Figure EMIF SDRAM Control Register 'C6211 MT48LC16M8A2
SDBSZ
RFEN
INIT
TRCD
0001
0001
SDRSZ
SDCSZ
0110
Reserved
000000000000
Note: SDCSZ=10b indicates that column address bits used. SDCSZ=10b indicates that column address bits used. SDBSZ=1 indicates that bank address bits used banks). RFEN indicates that SDRAM refresh enabled. INIT forces initialization SDRAM. TRCD 0001b from previous calculation. 0001b from previous calculation. 0110b from previous calculation.
Based above calculations, value 0x5B116000 should written EMIF SDRAM control register.
EMIF SDRAM Refresh Period 'C6211 MT48LC16M8A2
Table Period Calculation SDRAM Refresh Period 'C6211 MT48LC16M8A2
Field Name PERIOD Formula PERIOD tRefresh/tCYC Value From Micron Data Sheet tRefresh 4096 Value Calculated Field Period 0x61A cycles
Figure EMIF SDRAM Refresh Period 'C6211 MT48LC16M8A2
Reserved
00000000
COUNTER
000000000000
PERIOD
11000011010 (0x61A)
Note: Period 0x61A from previous calculation.
Based this result, value 0x61A should written EMIF SDRAM refresh period register.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
EMIF SDRAM Extension Register 'C6211 MT48LC16M8A2
SDRAM extension register, values must calculated based clock frequency used (100 this example, tCYC 10ns) parameters SDRAM used. Table summarizes values.
Table SDRAM Extension Register Values 'C6211 MT48LC16M8A2
Field Name TRAS TRRD THZP Formula Value From SDRAM Data Sheet cycles tRAS tRRD tHZP cycles Value Calculated Field TRAS TRRD THZP Value Recommended TRAS TRRD THZP RD2RD RD2DEAC RD2WR R2WDQM WR2WR WR2DEAC WR2RD
(tCL) TRAS (tRAS tCYC) TRRD (tRRD tCYC) (tWR tCYC) THZP (tHZP)
RD2RD RD2DEAC RD2WR R2WDQM Recommended value from Table WR2WR WR2DEAC WR2RD
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Appendix Code Example 'C6201B Micron MT48LC4M16A2-10
following code segment sets EMIF described above using TMS320C6000 Peripheral Runtime Support Control Library.
#include <emif.h> /*OTHER USER CODE*/ default values unsigned g_ctrl unsigned ce0_ctrl unsigned ce1_ctrl unsigned ce2_ctrl unsigned ce3_ctrl unsigned sdram_ctrl unsigned sdram_ref
EMIF registers GET_REG(EMIF_GCTRL); GET_REG(EMIF_CE0_CTRL); GET_REG(EMIF_CE1_CTRL); GET_REG(EMIF_CE2_CTRL); GET_REG(EMIF_CE3_CTRL); GET_REG(EMIF_SDRAM_CTRL); GET_REG(EMIF_SDRAM_REF);
Global Control Disable CLKOUT2 Enable SDCLK, CLKOUT1, SSCLK RESET_BIT(&g_ctrl, CLK2EN); SET_BIT(&g_ctrl, CLK1EN); SET_BIT(&g_ctrl, SSCEN); SET_BIT(&g_ctrl, SDCEN); Configure SDRAM LOAD_FIELD(&ce2_ctrl MTYPE_32SDRAM, MTYPE MTYPE_SZ Configure SDRAM Control Register LOAD_FIELD(&sdram_ctrl, LOAD_FIELD(&sdram_ctrl, LOAD_FIELD(&sdram_ctrl, TRCD SET_BIT(&sdram_ctrl, SDWID); SET_BIT(&sdram_ctrl, INIT); SET_BIT(&sdram_ctrl, RFEN); Refresh Period LOAD_FIELD(&sdram_ref, 0x61A
TRC_SZ TRP_SZ TRCD_SZ
PERIOD, PERIOD_SZ
Store EMIF Control Registers emif_init(g_ctrl, ce0_ctrl, ce1_ctrl, ce2_ctrl, ce3_ctrl, sdram_ctrl, sdram_ref); /*OTHER USER CODE*/
TMS320C6000 EMIF External SDRAM/SGRAM Interface
References
TMS320C6201/6201B Fixed-Point Digital Signal Processors Data Sheet, Literature Number SPRS051, April 1999, Texas Instruments. TMS320C6202 Fixed-Point Digital Signal Processor Data Sheet, Literature Number SPRS072, January 1999, Texas Instruments. TMS320C6211 Fixed-Point Digital Signal Processor Data Sheet, Literature Number SPRS073, March 1999, Texas Instruments. TMS320C6701 Floating-Point Digital Signal Processor Data Sheet, Literature Number SPRS067, March 1999, Texas Instruments. TMS320C6711 Floating-Point Digital Signal Processor Data Sheet, Literature Number SPRS088, March 1999, Texas Instruments. TMS320C6000 Peripherals Reference Guide, Literature number SPRU190, March 1999, Texas Instruments. TMS320C6000 Peripheral Support Library Programmers Reference, Literature number SPRU273, June 1998, Texas Instruments.
MT48LC4M16A2 Data Sheet, Micron Technology, Inc. MT48LC1M16A1 Data Sheet, Micron Technology, Inc. MT48LC16M8A2 Data Sheet, Micron Technology, Inc.
TMS320C6000 EMIF External SDRAM/SGRAM Interface
Contact Numbers
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TMS320C6000 EMIF External SDRAM/SGRAM Interface
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TMS320C6000 EMIF External SDRAM/SGRAM Interface

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