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Implementing Spectrum Analyzer Using 128-Point TMS320F240 Dave Fi


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Implementing Spectrum Analyzer Using 128-Point TMS320F240
Dave Figoli Digital Signal Processing Applications
Abstract
Evaluation module (EVM) application produces spectrum analyzer using digital-to-analog converter (DAC) Texas Instruments TMS320F240 EVM. spectrum analyzer produced using 128-point fast Fourier transform (FFT) with values collected from analog-to-digital converter (ADC). output produced using DAC, results viewed using oscilloscope trigger. results normalized that maximum value obtained equivalent This application implemented using C2xx assembly code. specific topic discussed implementation.
Contents
Overview Modules Used Input Output Background Methodology Implementation.3
Digital Signal Processing Solutions
June 1999
Overview
This application produces spectrum analyzer using TMS320F240 EVM. spectrum analyzer produced using 128-point with values collected from ADC. output produced using DAC, results viewed using oscilloscope trigger. results normalized that maximum value obtained equivalent This application implemented using C2xx assembly code.
Modules Used
Input
Event manager General-purpose timer
ADCIN0
Output
DAC0
Background Methodology
initial setup program similar finite-impulse-response (FIR) filter application. phase-locked loop (PLL) module, digital ports, event manager must configured prior capturing input waveform. event manager provides sampling time base general-purpose timer this application. Without known sampling frequency, peaks appearing result cannot associated with particular frequency. example, knew that sampling frequency 128-point FFT, first spike would then 1kHz/64, etc. module application (PWM0.ASM). (For more information application application report, Creation Pulse Width Modulated Signal With Fixed Duty Cycle, SPRA410.) frequency which CPUCLK runs important timer period register event manager module control sampling frequency ADC. this application, CPUCLK (that CLKIN MHz, divide enabled, multiplication ratio application output control register must configured that port sharing with configured input channel. (For more information application application report, Generating Signal Modulated Analog Input, SPRA413.)
Implementing Spectrum Analyzer Using 128-Point TMS320F240
application (FIR0.ASM). (For more information application application report, Detecting Frequency Band Using Bandpass Filter, SPRA414.) event manager controls sampling frequency. Because event manager starts ADC, single conversion.
Implementation
implemented using polling routine. interrupts masked setup event manager. However, because interrupt flags still when interrupt supposed occur, flags still used polling routine. polling routine determines when period register timer matches counter. When values match, timer interrupt flag set. using polling routine watch flag, routine that gathers data executed each time flag set. routine that gathers values from ADCFIFO register:
Fetches value Stores converted value location memory using bit-reversed addressing capabilities C2xx core Changes counter that tracks many points have been gathered Performs either following: Restarts more points must gathered), clears flag register, returns polling routine, Implements with stored points
counter keeps track many values converts. polling routine waits until flag register event manager before value ADCFIFO register read. Because cannot performed until samples obtained, auxiliary registers before first sample obtained. indirect addressing C2xx manipulates auxiliary registers values loaded. Once values loaded, performed. results output EVM; however, results from small hard visualize. result, magnitudes normalized that maximum magnitude maximum voltage produce. normalize values magnitudes, maximum magnitude must known. simple pass through memory locations containing magnitudes locates maximum value. Once maximum value obtained, remaining values "divided" maximum value. normalize values maximum value, routine that subtracts maximum value from magnitude then shifts remainder that maximum value subtracted again provides result repeating routine times.
Implementing Spectrum Analyzer Using 128-Point TMS320F240
example, simple fractions 2/3. value 2000h and, value 5555h. result result
shift left shift left shift left shift left
shift left shift left shift left shift left
Result 2000h (Q15 0.25)
Result 5555h (Q15 0.666656)
resulting values then multiplied maximum value output, which FFFh. result that every magnitude scaled proportion maximum value. output viewed through oscilloscope. While being output through channel DAC, held high. After results have been output, brought low. result, trigger scope view results FFT. Once program executed, runs until program halted. Thus, frequency input into modified, results viewed through oscilloscope.
Implementing Spectrum Analyzer Using 128-Point TMS320F240
File Name: FFT0.ASM Project: C240 Test Platform Originator: Allister Chang (Texas Instruments) Description:The program perfoms point FFT. data samples gathered from C240. performed magnitudes output test board. results then viewed using oscilloscope. trigger results oscilloscope Last Update:10 June Descriptions: C/F240 on-chip 10bit connected internal data bus[15:5]. Previous version assumed connected data bus. result data collected with were interpreted number gave incorrect result. Status: Works .include f240regs.h Debug directives ;-.def GPR0 ;General purpose registers. .def GPR1 .def GPR2 .def GPR3 specific constants .set ;FFT length TWID_TBL .set 08100h ;Start Twiddle table B0_SADR .set 08000h start address (changed locate data 0x8000 B0_EADR .set 080FFh address B1_SADR .set 08100h start address B1_EADR .set 081FFh address B2_SADR .set 0060h start address B2_EADR .set 007Fh address COS45K .set 05A82h ;Constant COS(45) Mapped Registers ;-DAC0 .set 0000h ;Input Data Register DAC0 DAC1 .set 0001h ;Input Data Register DAC1 DAC2 .set 0002h ;Input Data Register DAC2 DAC3 .set 0003h ;Input Data Register DAC3 DACUPDATE .set 0004h ;DAC Update Register Variable Declarations chip Block (DP=0) ;-.bss GPR0,1 ;General purpose registers. .bss GPR1,1 .bss GPR2,1 .bss GPR3,1
Implementing Spectrum Analyzer Using 128-Point TMS320F240
.bss COS45,1 ;Value COS(45) .bss DAC0VAL,1 .bss DAC1VAL,1 .bss DAC2VAL,1 .bss DAC3VAL,1 ;DAC0 ;DAC1 ;DAC2 ;DAC3 Channel Channel Channel Channel Value Value Value Value
.bss COUNTER,1 ;COUNTER obtaining values .bss RPT_NUM,1 .bss uSEC,1 MACRO 'ZEROI' number words/number cycles: ARP=2 INPUT OUTPUT QR,QI,QR+1,. PR,PI,PR+1,. CALCULATE Re[P+Q] Re[P-Q] QR'=(PR-QR)/2 PR'=(PR+QR)/2 PI'=(PI+QI)/2 PI'=(PI-QI)/2 version 1.00 from Manfred Christ update: July ZEROI .macro LACC *,15,AR1 (1/2)(QR) *,15 (1/2)(PR+QR) SACH *+,0,AR2 (1/2)(PR+QR) *,16 (1/2)(PR+QR)-(QR) SACH (1/2)(PR-QR) LACC SACH SACH .endm MACRO 'PBY2I' number words/number cycles: ARP=2 entry macro QR,QI,QR+1,. PR,PI,PR+1,. PR'=(PR+QI)/2 PI'=(PI-QR)/2 QR'=(PR-QI)/2 QI'=(PI+QR)/2 version 1.00 from Manfred Christ update: July PBY2I .macro LACC *+,15,AR5 SACH *,1,AR2 TMP=QR LACC SACH *,15,AR1 *,15 *+,0,AR2 *-,16 QI/2 (PR+QI)/2 (PR+QI)/2 (PR-QI)/2 *,15,AR1 *,15 *+,0,AR2 *,16 (1/2)(QI) (1/2)(PI+QI) (1/2)(PI+QI) (1/2)(PI+QI)-(QI) (1/2)(PI-QI) PR+1 PR+1 PR+1 QR+1
Implementing Spectrum Analyzer Using 128-Point TMS320F240
SACH LACC SACH SACH .endm MACRO 'PBY4I' number words/number cycles: T=SIN(45)=COS(45)=W45 PR'= (W*QI W*QR) AR1) QR'= (W*QI W*QR) AR2) PI'= (W*QI W*QR) AR1+1) QI'= (W*QI W*QR) AR1+2) version 1.00 from Manfred Christ update: July PBY4I .macro TREG= PREG *+,AR5 PREG= W*QR/2 W*QR/2 *,AR1 W*QR/2 W*QR/2 W*QR/2 LACC *,15,AR2 PR/2 W*QR/2 W*QR/2 MPYS (PR-W*QR)/2 W*QR/2 W*QI/2 SPAC (PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 SACH *+,0,AR1 (PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 *,16 (-PR-W*QI-W*QR)/2 W*QR/2 W*QI/2 (PR+W*QI+W*QR)/2 W*QR/2 W*QI/2 SACH (PR+W*QI+W*QR)/2 W*QR/2 W*QI/2 LACC SPAC SACH SACH .endm MACRO 'P3BY4I' number words/number cycles: version 1.00 from: Manfred Christ update: July ENTRANCE MACRO: ARP=AR2 AR1->PR,PI AR2->QR,QI TREG=W=COS(45)=SIN(45) PR'= (W*QI W*QR) AR1) QR'= (W*QI W*QR) AR2) PI'= (W*QI W*QR) AR1+1) QI'= (W*QI W*QR) AR1+2) EXIT MACRO: ARP=AR2 AR1->PR+1,PI+1 AR2->QR+1,QI+1 *,15,AR5 *,16,AR2 *+,0,AR1 *,16 *+,0,AR2 ACCU= ACCU= (PI)/2 W*QR/2 W*QI/2 (PI-W*QI)/2 W*QR/2 (PI-W*QI+W*QR)/2 (PI-W*QI+W*QR)/2 (-PI-W*QI+W*QR)/2 (PI+W*QI-W*QR)/2 (PI+W*QI-W*QR)/2 *+,0,AR1 *,15,AR5 *,15,AR1 *+,0,AR5 *,16,AR2 (PR-QI)/2 (PI)/2 (PI-QR)/2 (PI-QR)/2 (PI+QR)/2 (PI+QR)/2 PR+1 PR+1 PR+1 QI+1
Implementing Spectrum Analyzer Using 128-Point TMS320F240
P3BY4I .macro LACC MPYA SPAC SACH SACH LACC APAC SACH SACH .endm TREG= *+,AR5 PREG= *,AR1 *,15,AR2 *+,0,AR1 *,16 *,15,AR5 *,16,AR2 *:m:+,0,AR1 *,16 *:m:+,0,AR:p: ACCU= ACCU= -W*QR/2 W*QR/2 W*QR/2 PR/2 W*QR/2 (PR+W*QR)/2 W*QR/2 (PR-W*QI+W*QR)/2 W*QR/2 (PR-W*QI+W*QR)/2 W*QR/2 (-PR-W*QI+W*QR)/2 W*QR/2 (PR+W*QI-W*QR)/2 W*QR/2 (PR+W*QI-W*QR)/2 W*QR/2 PREG -W*QR/2 W*QR/2 W*QR/2 W*QI/2 W*QI/2 W*QI/2 W*QI/2 W*QI/2 W*QI/2
(PI)/2 W*QR/2 W*QI/2 (PI+W*QI)/2 W*QR/2 (PI+W*QI+W*QR)/2 (PI+W*QI+W*QR)/2 (-PI+W*QI+W*QR)/2 (PI-W*QI-W*QR)/2 (PI-W*QI-W*QR)/2
MACRO: 'BFLY' general butterfly radix 320C2xx/5x version 1.00 from Manfred Christ update: July MACRO 'BFLY' REQUIRES WORDS INSTRUCTIONS Definition: (input) (output) Definition: (input) QR+1 (output) Definition: (input) PR+1 (output) Definition: Cxxx (input) Cxxx+1 (output) WR=cosine Definition: Sxxx (input) Sxxx+1 (output) WI=sine Definition: temporary variable (unchanged) uses index register (PR+(QR*WR+QI*WI))/2 WR=COS(W) WI=SIN(W) (PI+(QI*WR-QR*WI))/2 (PR-(QR*WR+QI*WI))/2 (PI-(QI*WR-QR*WI))/2 Note: determines Twiddle Pointers (AR3 AR4) step increments BFLY .macro (contents register after exec.) TREG *+,AR3 ;TREG:= *,AR2 ;PREG:= QR*WR/2 *-,AR4 ;ACC QR*WR/2 *,AR3 ;PREG:= QI*WI/2 MPYA *0+,AR2 ;ACC (QR*WR+QI*WI)/2 ;PREG:= QI*WR *,AR5;TREG SACH *,1,AR1 ;TEMP:= (QR*WR+QI*WI) *,15 ;ACC SACH *+,0,AR5 *,16,AR2 SACH *+,0,AR1 (PR+(QR*WR+QI*WI))/2 (PR+(QR*WR+QI*WI))/2 ;ACC (PR-(QR*WR+QI*WI))/2 (PR-(QR*WR+QI*WI))/2
Implementing Spectrum Analyzer Using 128-Point TMS320F240
*,15,AR4 ;ACC /PREG=QI*WR MPYS *0+,AR2 ;PREG:= QR*WI/2 ;ACC (PI-QI*WR)/2 APAC ;ACC (PI-(QI*WR-QR*WI))/2 SACH *+,0,AR1 (PI-(QI*WR-QR*WI))/2 QR+1 ;ACC :=(-PI+(QI*WR-QR*WI))/2 QR+1 *,16 ;ACC (PI+(QI*WR-QR*WI))/2 QR+1 SACH *+,0,AR:p: (PI+(QI*WR-QR*WI))/2 PR+1 QR+1 .endm MACRO 'COMBO' [(R1+R2)+(R3+R4)]/4 INPUT OUTPUT [(R1-R2)+(I3-I4)]/4 [(R1+R2)-(R3+R4)]/4 [(R1-R2)-(I3-I4)]/4 R1,I1 R5,I5 [(I1+I2)+(I3+I4)]/4 R2,I2 R6,I6 [(I1-I2)-(R3-R4)]/4 R3,I3 R7,I7 [(I1+I2)-(I3+I4)]/4 R4,I4 R8,I8 [(I1-I2)+(R3-R4)]/4 COMBO .macro -LACC *,14,AR4 (R3)/4 *,14,AR5 (R3+R4)/4 SACH *+,1,AR4 (R3-R4)/2 SACH SACH SACH SACH SACH LACC SACH SACH SACH LACC SACH SACH .endm *+,15,AR5 *,1,AR2 *,14,AR1 *,14 *+,0,AR5 *,16,AR3 *+,0,AR5 *,15,AR2 *,15,AR3 *,14,AR4 *,14,AR2 *+,0,AR4 *-,15,AR3 *,15,AR4 *+,0,AR1 *,14,AR2 *,14,AR5 *,1,AR2 *,15,AR3 *,14,AR4 *,14,AR1 *0+,0,AR3 *,15,AR4 *,15,AR3 *0+,0,AR5 (R3+R4)/4 (R3+R4)/2 (R2+R3+R4)/4 (R1+R2+R3+R4)/4 (R1+R2+R3+R4)/4 (R1+R2-(R3+R4))/4 (R1+R2-(R3+R4))/4 (R1+R2)/4 (R1-R2)/4 ((R1-R2)+(I3))/4 ((R1-R2)+(I3-I4))/4 ((R1-R2)+(I3-I4))/4 ((R1-R2)+ I3+I4 ((R1-R2)-(I3-I4))/4 ((R1-R2)-(I3-I4))/4 (I1)/4 (I1-I2)/4 (I1-I2)/2 ((I1+I2))/4 ((I1+I2)+(I3))/4 ((I1+I2)+(I3+I4))/4 ((I1+I2)+(I3+I4))/4 ((I1+I2)-(I3+I4))/4 ((I1+I2)-(I3+I4))/4 ((I1+I2)-(I3+I4))/4
*-,15 *,15,AR2 *0+,0,AR5 *,16,AR4 *0+,0,AR7;
(I1-I2)/4 ((I1-I2)-(R3-R4))/4 ((I1-I2)-(R3-R4))/4 ((I1-I2)+(R3-R4))/4 ((I1-I2)+(R3-R4))/4
Implementing Spectrum Analyzer Using 128-Point TMS320F240
Vector address declarations ;-.sect ".vectors" Vectors programmed EPROM RSVECT INT1 INT2 INT3 INT4 INT5 INT6 RESERVED SW_INT8 SW_INT9 SW_INT10 SW_INT11 SW_INT12 SW_INT13 SW_INT14 SW_INT15 SW_INT16 TRAP NMINT EMU_TRAP SW_INT20 SW_INT21 SW_INT22 SW_INT23 START PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM PHANTOM Reset Vector (Analysis Int) User User User User User User User User User Trap vector maskable Emulator Trap User User User User
starts here .text START: SETC IN;Disable Interrupts SPLK #0000h,IMR ;Mask core interrupts LACC ;Read Interrupt flags SACL ;Clear interrupt flags shift from PREG->ALU ROVM ;dis overflow SSXM ;allow sign extension CLRC ;Config Block Data mem. LACC #COS45K SACL COS45 ;Init location with constant.
Module ;-LDP #00E0h 224; Address 7000h 707Fh
;The following line necessary previous program different ;setting than settings which application uses. disabling PLL, ;CKCR1 register modified that settings when re-enabled. 5432109876543210 SPLK #0000000001000001b,CKCR0 ;CLKMD=PLL Disable,SYSCLK=CPUCLK/2
Implementing Spectrum Analyzer Using 128-Point TMS320F240
5432109876543210 SPLK #0000000010111011b,CKCR1 ;CLKIN(OSC)=10MHz,CPUCLK=20MHz
;CKCR1 Clock Control Register Bits (1011)CKINF(3)-CKINF(0) Crystal Clock-In Frequency Frequency 10MHz PLLDIV(2) divide Divide input Bits (011) PLLFB(2)-PLLFB(0) multiplication ratio Multiplication Ratio
5432109876543210 SPLK #0000000011000001b,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2
;CKCR0 Clock Control Register Bits (11) CLKMD(1),CLKMD(0) Operational mode Clock Module Enabled; CLKIN exiting power mode Bits (00) PLLOCK(1),PLLOCK(0) Status. READ ONLY Bits (00) PLLPM(1),PLLPM(0) Power Mode LPM0 ACLKENA 1MHz ACLK Enable ACLK Disabled PLLPS System Clock Prescale Value f(sysclk)=f(cpuclk)/2 5432109876543210 SPLK #0100000011000000b,SYSCR ;CLKOUT=CPUCLK
;SYSCR System Control Register 15-14 (01) RESET1,RESET0 Software Reset Bits Action Bits 13-8 (000000) Reserved 7-6(11) CLKSRC1,CLKSRC0 CLKOUT-Pin Source Select CPUCLK: clock output mode 5-0(000000) Reserved
SPLK #006Fh, WDCR ;Disable VCCP=5V (JP5 pos. 2-3) KICK_DOG ;Reset Watchdog Event Manager Module Reset This section resets Event Manager Module Registers.* This necessary silicon revsion 1.1; however, silicon revisions later, this necessary #232 ;DP=232 Data Page SPLK #0000h,GPTCON ;Clear General SPLK #0000h,T1CON ;Clear Timer SPLK #0000h,T2CON ;Clear Timer SPLK #0000h,T3CON ;Clear Timer Event Manager Purpose Timer Control Control Control Control
SPLK #0000h,COMCON ;Clear Compare Control SPLK #0000h,ACTR ;Clear Full Compare Action Control Register SPLK #0000h,SACTR ;Clear Simple Compare Action Control Register SPLK #0000h,DBTCON ;Clear Dead-Band Timer Control Register SPLK #0FFFFh,EVIFRA;Clear Interrupt Flag Register SPLK #0FFFFh,EVIFRB;Clear Interrupt Flag Register
Implementing Spectrum Analyzer Using 128-Point TMS320F240
SPLK #0FFFFh,EVIFRC;Clear Interrupt Flag Register SPLK #0000h,CAPCON ;Clear Capture Control SPLK #0000h,EVIMRA ;Clear Event Manager Mask Register SPLK #0000h,EVIMRB ;Clear Event Manager Mask Register SPLK #0000h,EVIMRC ;Clear Event Manager Mask Register RESET section silicon revision Event Manager Module ;-T1COMPARE .set T1PERIOD .set ;Sets period 128kHz frequency ;T1COMPARE .set ;T1PERIOD .set ;T1COMPARE .set ;T1PERIOD .set 1000
;Sets period 64kHz frequency
;Sets period 20kHz frequency
#232 ;DP=232, Data Page Event Manager Addresses SPLK #T1COMPARE,T1CMPR ;T1CMPR duty cycle 2109876543210 SPLK #0000001010101b,GPTCON
;GPTCON Timer Control Register T3STAT Timer Status. READ ONLY T2STAT Timer Status. READ ONLY T1STAT Timer Status. READ ONLY Bits 12-11 (00) T3TOADC start event Timer event starts Bits 10-9 (00) T2TOADC start event Timer event starts Bits (00) T1TOADC start event Timer event starts TCOMPOE Compare output enable Enable three timer compare outputs Bits (01) T3PIN Polarity Timer compare output Active Bits (01) T2PIN Polarity Timer compare output Active Bits (01) T1PIN Polarity Timer compare output Active SPLK #T1PERIOD,T1PR ;T1PR SPLK #0000h,T1CNT ;Clear SPLK #0000h,T2CNT ;Clear SPLK #0000h,T3CNT ;Clear T1PERIOD Timer Timer Timer value Sampling Freq. Counter Counter Counter
5432109876543210 SPLK #0001000001000010b,T1CON
;T1CON Timer Control Register Bits 15-14 (00) FREE,SOFT Emulation Control Bits Stop immediately emulation suspend Bits 13-11 (010) TMODE2-TMODE0 Count Mode Selection Continuous-Up Count Mode Bits 10-8 (000) TPS2-TPS0 Input Clock Prescaler
Implementing Spectrum Analyzer Using 128-Point TMS320F240
Divide Reserved TENABLE Timer Enable Disable timer operations Bits (00) TCLKS1,TCLKS0 Clock Source Select Internal Clock Source Bits (00) TCLD1,TCLD0 Timer Compare Register Reload Condition When counter TECMPR Timer compare enable Enable timer compare operation Reserved 5432109876543210 SPLK #0000000000000000b,T2CON Timer Used
;T2CON Timer Control Register Bits 15-14 (00) FREE,SOFT Emulation Control Bits Stop immediately emulation suspend Bits 13-11 (000) TMODE2-TMODE0 Count Mode Selection Stop/Hold Bits 10-8 (000) TPS2-TPS0 Input Clock Prescaler Divide TSWT1 Timer timer enable TENABLE TENABLE Timer Enable Disable timer operations Bits (00) TCLKS1,TCLKS0 Clock Source Select Internal Clock Source Bits (00) TCLD1,TCLD0 Timer Compare Register Reload Condition When counter TECMPR Timer compare enable Disable timer compare operation SELT1PR Period Register select period register 5432109876543210 SPLK #0000000000000000b,T3CON Timer Used
;T3CON Timer Control Register Bits 15-14 (00) FREE,SOFT Emulation Control Bits Stop immediately emulation suspend Bits 13-11 (000) TMODE2-TMODE0 Count Mode Selection Stop/Hold Bits 10-8 (000) TPS2-TPS0 Input Clock Prescaler Divide TSWT1 Timer timer enable TENABLE TENABLE Timer Enable Disable timer operations Bits (00) TCLKS1,TCLKS0 Clock Source Select Internal Clock Source Bits (00) TCLD1,TCLD0 Timer Compare Register Reload Condition When counter TECMPR Timer compare enable Disable timer compare operation SELT1PR Period Register select period register
Digital Port ;-LDP #225 225; Addresses 7800h 707Fh 5432109876543210
Implementing Spectrum Analyzer Using 128-Point TMS320F240
SPLK #0011100000001111b,OCRA ;OCRA Output Control Register CRA.15 IOPB7 CRA.14 IOPB6 CRA.13 T3PWM/T3CMP CRA.12 T2PWM/T2CMP CRA.11 T1PWM/T1CMP CRA.10 IOPB2 CRA.9 IOPB1 CRA.8 IOPB0 Bits (0000)Reserved CRA.3 ADCIN8 CRA.2 ADCIN9 CRA.1 ADCIN1 CRA.0 ADCIN0 76543210 SPLK #11110000b,OCRB Output Control Register CRB.7 CAP4 CRB.6 CAP3 CRB.5 CAP2/QEP2 CRB.4 CAP1/QEP1 CRB.3 CRB.2 CRB.1 CRB.0 IOPC0
;OCRB
Module ;-LDP #224 Data Page Registers 5432109876543210 SPLK #1000100100000000b,ADCTRL1
;ADCTRL1 Control Register Suspend-SOFT Complete Conversion before halting emulator Suspend-FREE Operations determined Suspend-SOFT ADCIMSTART start converting immediately Immediate Start Conversion ADC1EN Enable/Disable ADC2 Disable ADC2 ADC2EN Enable/Disable ADC1 Enable ADC1 ADCCONRUN Continuous Conversion Mode Disable Continuous Conversion ADCINTEN Enable Interrupt action when ADCINTFLAG ADCINTFLAG Interrupt Flag Clear Interrupt Flab ADCEOC Conversion READ ONLY Bits (000) ADC2CHSEL ADC2 Channel Select Channel Bits (000) ADC1CHSEL ADC1 Channel Select Channel ADCSOC Start conversion Action
Implementing Spectrum Analyzer Using 128-Point TMS320F240
5432109876543210 SPLK #0000000000000101b,ADCTRL2
;ADCTRL2 Control Register Bits 15-11 (00000)Reserved ADCEVSOC Event Manager mask Mask ADCEVSOC ADCEXTSOC External mask Mask ADCEXTSOC Reserved Bits (00) ADCFIFO1 Data Register FIFO1 Status READ ONLY Reserved Bits (00) ADCFIFO2 Data Register FIFO2 Status READ ONLY Bits (101) ADCPSCALE Input Clock Prescaler Prescale Value SYSCLK Period 0.1usec 0.1usec usec 6usec
;The module requires that wait states generated proper operation. #0000h ;Set Data Page Pointer 0000h, Block SPLK #4h,GPR0 ;Set Wait State Generator GPR0,WSGR ;Program Space, ;Date Space, ;I/O Space, Xfer Twiddles Block Twiddles REPEAT AR0, ;set Twiddles Xfer AR1, #B1_SADR ;AR1 points dest addr LACC #PS_TWID_STRT ;ACC points addr TWD_XFR ;select TBLR ;Mov Prog word Data ;inc BANZ TWD_XFR ;continue Xfer until AR0=0 Fetch Data sample points from port FTCH_DATA AR0, #128 ;AR0 128; Samples Reversed Addressing AR1, #B0_SADR ;AR1 Start Address Data Buffer AR2, #ADCFIFO1 ;AR2 Value Converted from AR3, #(B1_SADR+128) ;AR3 B1_SADR AR7, #127 ;AR7 ;ARP #224 ;Set ADCTRL1 SBIT1 ADCTRL1,B0_MSK ;Starts converting #232 ;Set T1CON SBIT1 T1CON,B6_MSK ;Starts Timer Correction made following data collection section CLRC Disable sign extension mode while reading data from FTCH_LPBIT EVIFRA,BIT7 ;Polling routine wait BCND FTCH_LP,NTC ;T1PINT Flag
Implementing Spectrum Analyzer Using 128-Point TMS320F240
#224 SBIT1 ADCTRL1,B0_MSK ;Restart LACC *,15,AR3 ;ACC ADCFIFO1; SACH *+,0,AR1 ;Value location pointed Value pointed AR2; SACH *BR0+,0,AR7 ;Store sample into data buffer using ;bit reversed addressing; #232 LACC EVIFRA ;ACC Event Manager Interrupt Flag Register SACL EVIFRA ;Clear flag register BANZ FTCH_LP,*-,AR2 ;Wait next flag T1PINT, ;samples have been collected, perform FFT. ;ARP SBIT0 T1CON,B6_MSK ;Stop timer SPLK #0000h,T1CNT ;Clear timer counter SETC Enable sign extension mode
Stages using Radix COMBO Macro AR0, ;Increment Data pointers AR1, #(B0_SADR) AR2, #(B0_SADR+2) AR3, #(B0_SADR+4) AR4, #(B0_SADR+6) AR5, #B2_SADR ;Gen purp AR7, #(N/4-1) ;Loop times STAGE1_2_LP: COMBO BANZ STAGE1_2_LP,*-,AR3 Stage using ZEROI, PBY4I, PBY2I, P3BY4I Macros STAGE3: ;ARP->AR2 AR0, AR1, #(B0_SADR) ;->P AR2, #(B0_SADR+8) ;->Q AR5, #B2_SADR ;Gen purp AR7, #(N/8-1) ;Loop counter times) COS45 STAGE3_LP: ZEROI PBY4I PBY2I P3BY4I ;->AR7 end, modify. BANZ STAGE3_LP,*-,AR2 Stage using ZEROI, PBY4I, PBY2I, P3BY4I, BFLY Macros STAGE4: ;ARP->AR2 AR0, ;Used Twiddle pointers AR1, #(B0_SADR) ;->P AR2, #(B0_SADR+16) ;->Q AR5, #B2_SADR ;Gen purp AR7, #(N/16-1) ;Loop counter times)
Implementing Spectrum Analyzer Using 128-Point TMS320F240
STAGE4_LP: ZEROI AR3, #(TWID_TBL+8+N/4) AR4, #(TWID_TBL+8) STG4_B1 BFLY COS45 PBY4I STG4_B2 BFLY PBY2I STG4_B3 BFLY COS45 P3BY4I STG4_B4 BFLY ADRK ADRK BANZ STAGE4_LP,*-,AR2 Stage using BUTTFLYI Macro STAGE5: ;->AR2 AR0, ;Used Twiddle pointers AR1, #(B0_SADR) ;->P (0->15) AR2, #(B0_SADR+32) ;->Q (16->31) AR5, #B2_SADR ;Gen purp ;-STG5_BLK1 AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/8-1) ;Loop counter times) STAGE51_LP: BFLY BANZ STAGE51_LP,*-,AR2 ;-STG5_BLK2: AR1, #(B0_SADR+64) ;->P (32->47) AR2, #(B0_SADR+96) ;->Q (48->63) AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/8-1) ;Loop counter times) STAGE52_LP: BFLY BANZ STAGE52_LP,*-,AR2 ;-STG5_BLK3: AR1, #(B0_SADR+128) ;->P (64->79) AR2, #(B0_SADR+160) ;->Q (80->95) AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/8-1) ;Loop counter times)
;->AR2
Implementing Spectrum Analyzer Using 128-Point TMS320F240
STAGE53_LP: BFLY BANZ STAGE53_LP,*-,AR2 ;-STG5_BLK4: AR1, #(B0_SADR+192) ;->P (96->111) AR2, #(B0_SADR+224) ;->Q (112->127) AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/8-1) ;Loop counter times) STAGE54_LP: BFLY BANZ STAGE54_LP,*-,AR2
Stage Using BFLY Macro STAGE6: ;->AR2 AR0, ;used Twiddle pointers AR1, #(B0_SADR) ;->P (0->31) AR2, #(B0_SADR+64) ;->Q (32->63) AR5, #B2_SADR ;Gen purp ;-STG6_BLK1 AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/4-1) ;Loop counter times) STAGE61_LP: BFLY BANZ STAGE61_LP,*-,AR2 ;-STG6_BLK2: AR1, #(B0_SADR+128) ;->P (64->95) AR2, #(B0_SADR+192) ;->Q (96->127) AR3, #(TWID_TBL+N/4) ;COS(angle) AR4, #(TWID_TBL) ;COS(angle+pi/4) AR7, #(N/4-1) ;Loop counter times) STAGE62_LP: BFLY BANZ STAGE62_LP,*-,AR2
Stage Using BFLY Macro STAGE7: ;->AR2 AR0, ;Used Twiddle pointers AR1, #(B0_SADR) ;->P (0->63) AR2, #(B0_SADR+128) ;->Q (64->128) AR5, #B2_SADR ;Gen purp AR3, #(TWID_TBL+N/4) AR4, #(TWID_TBL) AR7, #(N/2-1) ;Loop counter times) STG_7_LP BFLY
Implementing Spectrum Analyzer Using 128-Point TMS320F240
BANZ STG_7_LP,*-,AR2
Convert Real/Img into Magnitude sqr(Xr[n]) sqr(Xi[n]) AR1, #B0_SADR AR2, #B1_SADR LARK AR3, #127 ;loop times AR4, #(B1_SADR+128) MAG_LP MPYK SQRA ;Xr[n]**2 SQRA *+,AR2 ;Xi[n]**2 APAC SACH *+,0,AR4 SACH *+,0,AR3 ;XOUT(I) X(I)**2 Y(I)**2 BANZ MAG_LP,*-,AR1 Normalize Values .bss MAX,1 .bss QUOTIENT,1 .text AR1,#(B1_SADR+128) AR2,#127 SPLK #0,MAX ;Initialize variable SPLK #0,QUOTIENT ;Initizlize variable QUOTIENT ;The following section finds maximum value among magnitudes *,AR1 ;ARP FIND_MAX LACC *+,0,AR2 ;ACC Value pointed AR1; AR1+1 ;Subtract BCND RESUME,LEQ result less than zero, then ;the value larger than MAX, else SACL ;Store value RESUME BANZ FIND_MAX,*-,AR1 through magnitudes find ;maximum value, then normalize values ;The following section makes everything ratio according maximum value AR1,#(B0_SADR+256) ;AR1 B1_SADR AR2,#127 ;AR2 128-1; Number Magnitudes Normalize AR3,#(B1_SADR+128) ;AR3 B1_SADR AR4,#MAX ;AR4 Address value AR5,#QUOTIENT ;AR5 Address quotient AR6,#15 ;AR6 Number times subtract
*,AR5 ;ARP DIVIDING LACC ;ACC QUOTIENT SACL *,1,AR3 ;QUOTIENT QUOTIENT shift doesn't matter ;because QUOTIENT LACC *,0,AR4 ;ACC Value pointed ;Subtract BCND ADD_ONE,GEQ still positive, then increment
Implementing Spectrum Analyzer Using 128-Point TMS320F240
;the ones place quotient, shift ;the remainder ACC, else ;shift remainder
;Check following section reduce unnecessary instructions *,AR3 SACL *,1,AR6 ;Store remainder location ;pointed BANZ DIVIDING,*-,AR5 ;AR6 Repeat dividing NEXT_VALUE ;After repeating times, fetch another ;value ADD_ONEMAR *,AR3 ;ARP SACL *,1,AR5 ;Store Remainder shifted back ;into buffer LACC ;ACC Quotient ;Increment quotient SACL *,0,AR6 ;Store value quotient; BANZ DIVIDING,*-,AR5 ;AR6 Repeat dividing NEXT_VALUE NEXT_VALUE AR6,#15 ;Reset *,AR3 ;ARP SACL *+,0,AR5 ;Store quotient into buffer SPLK #0,*,AR2 ;Clear variable QUOTIENT BANZ DIVIDING,*-,AR5 ;Repeat dividing routine values ;The following section corrects value obtained when maximum value ;divided itself. Changes 8000h value 7FFFh AR1,#(B1_SADR+128) AR2,#127 *,AR1 ;ARP CHANGING LACC ;ACC Value pointed #8000h ;Subtract 8000h BCND CONTINUE,NEQ equal 8000h, then LACC #0FFFFh ;ACC FFFFh, else CONTINUE #8000h SACL *+,0,AR2 ;Check next value BANZ CHANGING,*-,AR1 through entire buffer
;The following section multiplies numbers maximum value (FFFh) AR1,#(B1_SADR+128) AR2,#127 *,AR1 ;ARP NORMALIZE ;TREG Value pointed #0FFFh ;Multiply FFFh ;ACC PREG SACH *+,1,AR2 ;Store high word, elimnate extra sign BANZ NORMALIZE,*-,AR1 ;Normalize magnitudes Output values AR1, #B1_SADR ;AR1 Beginning Un-normalized magnitudes AR2, ;AR2 Display first magnitudes
Implementing Spectrum Analyzer Using 128-Point TMS320F240
*,AR1 ;ARP
SPLK #2,uSEC ;Variable uSEC
;The following section outputs un-normalized values ;OUTPUTSETC ;Set high LACC *+,AR2 ;ACC value pointed SACL DAC0VAL ;DAC0VAL DAC0VAL,DAC0 ;Write value channel DAC0VAL,DACUPDATE ;Output value CALL DELAY ;Wait *,AR2 ;ARP BANZ OUTPUT,*-,AR1 ;Output remaining values CLRC ;Clear once values have been output AR1, #(B1_SADR+128) ;AR1 Beginning normalized magnitudes AR2, ;AR2 Display first magnitudes *,AR1 ;ARP ;The following section outputs normalized values OUTPUT2SETC ;Set high LACC *+,AR2 ;ACC value pointed SACL DAC0VAL ;DAC0VAL DAC0VAL,DAC0 ;Write value channel DAC0VAL,DACUPDATE ;Output value CALL DELAY ;Wait *,AR2 ;ARP BANZ OUTPUT2,*-,AR1 ;Output remaining values
SPLK #0,DAC0VAL ;DAC0VAL DAC0VAL,DAC0 ;Clear channel DAC0VAL,DACUPDATE ;Output CLRC REPEAT DEND DEND Routine Name: DELAY Description:Produces multiple 1.6uS delays using instruction. Delay produced based value loaded uSEC (i.e. Delay uSEC 1.6mS). Indirect addressing used count number times delay loop repeated. Calling Convention: Variables Entry Exit 0x0000 uSEC value un-touched DELAY: ;DP->0000h-007Fh LACC SACL RPT_NUM ;RPT_NUM ;Clear back wait next samples
Implementing Spectrum Analyzer Using 128-Point TMS320F240
AR7,uSEC *,AR7 ;Set generate ;(AR0*0.1)mSEC delay loop
DELAY_LOOP: ;DP->0000h-007Fh RPT_NUM cycles 1.6uS cycle BANZ DELAY_LOOP ;Repeat DELAY_LOOP ;Return from DELAY PHANTOM Description:Dummy ISR, used trap spurious interrupts. Modifies: Last Update:16-06-95 PHANTOM PHANTOM TWIDDLES N=128 entries) PS_TWID_STRT: .word 00000h 0.000 .word 00648h 2.812 .word 00c8ch 5.625 .word 012c8h 8.438 .word 018f9h 11.250 .word 01f1ah 14.062 .word 02528h 16.875 .word 02b1fh 19.688 .word 030fch 22.500 .word 036bah 25.312 .word 03c57h 28.125 .word 041ceh 30.938 .word 0471dh 33.750 .word 04c40h 36.562 .word 05134h 39.375 .word 055f6h 42.188 .word 05a82h 45.000 .word 05ed7h 47.812 .word 062f2h 50.625 .word 066d0h 53.438 .word 06a6eh 56.250 .word 06dcah 59.062 .word 070e3h 61.875 .word 073b6h 64.688 .word 07642h 67.500 .word 07885h 70.312 .word 07a7dh 73.125 .word 07c2ah 75.938 .word 07d8ah 78.750 .word 07e9dh 81.562 .word 07f62h 84.375 .word 07fd9h 87.188 .word 07fffh 90.000 .word 07fd9h 92.812 .word 07f62h 95.625 .word 07e9dh 98.438 .word 07d8ah 101.250 .word 07c2ah 104.062 .word 07a7dh 106.875 .word 07885h 109.688 .word 07642h 112.500
Implementing Spectrum Analyzer Using 128-Point TMS320F240
.word 073b6h .word 070e3h .word 06dcah .word 06a6eh .word 066d0h .word 062f2h .word 05ed7h .word 05a82h .word 055f6h .word 05134h .word 04c40h .word 0471dh .word 041ceh .word 03c57h .word 036bah .word 030fch .word 02b1fh .word 02528h .word 01f1ah .word 018f9h .word 012c8h .word 00c8ch .word 00648h .word 00000h .word 0f9b8h .word 0f374h .word 0ed38h .word 0e707h .word 0e0e6h .word 0dad8h .word 0d4e1h .word 0cf04h .word 0c946h .word 0c3a9h .word 0be32h .word 0b8e3h .word 0b3c0h .word 0aecch .word 0aa0ah .word 0a57eh .word 0a129h .word 09d0eh .word 09930h .word 09592h .word 09236h .word 08f1dh .word 08c4ah .word 089beh .word 0877bh .word 08583h .word 083d6h .word 08276h .word 08163h .word 0809eh PS_TWID_END: .word 08027h 115.312 118.125 120.938 123.750 126.562 129.375 132.188 135.000 137.812 140.625 143.438 146.250 149.062 151.875 154.688 157.500 160.312 163.125 165.938 168.750 171.562 174.375 177.188 180.000 182.812 185.625 188.438 191.250 194.062 196.875 199.688 202.500 205.312 208.125 210.938 213.750 216.562 219.375 222.188 225.000 227.812 230.625 233.438 236.250 239.062 241.875 244.688 247.500 250.312 253.125 255.938 258.750 261.562 264.375
267.188
Implementing Spectrum Analyzer Using 128-Point TMS320F240
Contact Numbers
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Implementing Spectrum Analyzer Using 128-Point TMS320F240
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Implementing Spectrum Analyzer Using 128-Point TMS320F240

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