XC2C384 CoolRunner-II CPLD DS095 (v2.5) October 2004 Prelimi
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XC2C384 CoolRunner-II CPLD
DS095 (v2.5) October 2004
Preliminary Product Specification
Features
Optimized 1.8V systems fast pin-to-pin delays quiescent current Industry's best 0.18 micron CMOS CPLD Optimized architecture effective logic synthesis Multi-voltage operation 1.5V 3.3V Available multiple package options 144-pin TQFP with user 208-pin PQFP with user 256-ball (1.0mm) with user 324-ball (1.0mm) with user Pb-free available packages Advanced system features Fastest system programming 1.8V using IEEE 1532 (JTAG) interface IEEE1149.1 JTAG Boundary Scan Test Optional Schmitt-trigger input (per pin) Unsurpassed power management DataGATE enable (DGE) signal control Four seperate output banks RealDigital 100% CMOS product term generation Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide 2,4,6,8,10,12,14,16) CoolCLOCK Global signal options with macrocell control Multiple global clocks with phase selection macrocell Multiple global output enables Global set/reset Advanced design security architecture Superior pinout retention 100% product term routability across function block Open-drain output option Wired-OR drive Optional bus-hold, 3-state weak pullup selected pins Optional configurable grounds unused I/Os Mixed voltages compatible with 1.5V, 1.8V, 2.5V, 3.3V logic levels SSTL2-1, SSTL3-1, HSTL-1 compatibility pluggable
Description
CoolRunner-II 384-macrocell device designed both high performance power applications. This lends power savings high-end communication equipment high speed battery operated devices. power stand-by dynamic operation, overall system reliability improved This device consists twenty four Function Blocks inter-connected power Advanced Interconnect Matrix (AIM). feeds true complement inputs each Function Block. Function Blocks consist P-term macrocells which contain numerous configuration bits that allow combinational registered modes operation. Additionally, these registers globally reset preset configured flip-flop latch. There also multiple clock signals, both global local product term types, configured macrocell basis. Output configurations include slew rate limit, hold, pull-up, open drain programmable grounds. Schmitt-trigger input available input basis. addition storing macrocell output states, macrocell registers configured direct input registers store signals directly from input pins. Clocking available global Function Block basis. Three global clocks available Function Blocks synchronous clock source. Macrocell registers individually configured power zero state. global set/reset control line also available asynchronously reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchonous set/reset output enable signals formed using product terms per-macrocell per-Function Block basis. DualEDGE flip-flop feature also available macrocell basis. This feature allows high performance synchronous operation based lower frequency clocking help reduce total power consumption device. Circuitry also been included divide externally supplied global clock (GCK2) eight different selections. This yields divide even clock frequencies. clock divide (division DualEDGE flip-flop gives resultant CoolCLOCK feature. DataGATE method selectively disable inputs CPLD that interest during certain points time.
Refer CoolRunnerTM-II family data sheet architecture description.
2003 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD mapping signal DataGATE function, lower power achieved reduction signal switching. Another feature that eases voltage translation output banking. Four output banks available CoolRunner-II macrocell device that permits easy interfacing 3.3V, 2.5V, 1.8V, 1.5V devices. CoolRunner-II macrocell CPLD compatible with various standards (see Table This device also 1.5V compatible with Schmitt-trigger inputs.
standard voltages. LVTTL standard general purpose EIA/JEDEC standard 3.3V applications that LVTTL input buffer Push-Pull output buffer. LVCMOS standard used 3.3V, 2.5V, 1.8V applications. Both HSTL SSTL standards make VREF JEDEC compliance. CoolRunner-II CPLDs also 1.5V compatible with Schmitt-trigger inputs. Table Standards XC2C384 Output VCCIO Input VCCIO Board Input Termination VREF Voltage 0.75 1.25 0.75 1.25
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs fabricated 0.18 micron process technology which derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital design technique that makes CMOS technology both fabrication design methodology. RealDigital design technology employs cascade CMOS gates implement products instead traditional sense amplifier methodology. this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance power operation.
Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V HSTL-1 SSTL2-1 SSTL3-1
information assigning Vref pins, XAPP399.
Supported Standards
CoolRunner-II macrocell features LVCMOS, LVTTL, SSTL HSTL implementations. Table
(mA)
DS095_01_053103
Frequency (MHz)
Figure Frequency Table Frequency (LVCMOS 1.8V 25°C)(1) Frequency (MHz) Typical (mA) Typical (mA) 0.03 17.5 35.03 52.53 70.03 87.53 105.03 122.35 140.03
Notes: 16-bit up/down, resettable binary counter (one counter function block).
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCCIO VJTAG
Description Supply voltage relative ground Supply voltage output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative ground Voltage applied 3-state output Storage Temperature (ambient) Junction Temperature
Value -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 +150
Units
VAUX
VTS(1) TSTG(3)
Notes: Maximum undershoot below must limited either 0.5V whichever easiest achieve. During transitions, device pins undershoot -2.0v overshoot +4.5V, provided this over undershoot lasts less than with forcing current being limited Valid over commercial temperature range. soldering guidelines thermal considerations, Device Packaging information Xilinx website. free packages, XAPP427.
Recommended Operating Conditions
Symbol VCCIO Parameter Supply voltage internal logic input buffers Commercial +70°C Industrial -40°C +85°C Units
Supply voltage output drivers 3.3V operation Supply voltage output drivers 2.5V operation Supply voltage output drivers 1.8V operation Supply voltage output drivers 1.5V operation
VAUX
Supply voltage JTAG programming
Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICCSB CJTAG CCLK IIL(2) IIH(2) Parameter Standby current (-6) Standby current (-7, -10) Standby current (industrial) Dynamic current (-6) Dynamic current (-7, -10) JTAG input capacitance Global clock input capacitance capacitance Input leakage current High-Z leakage Test Conditions 1.9V, VCCIO 3.6V 1.9V, VCCIO 3.6V 1.9V, VCCIO 3.6V VCCIO 3.9V VCCIO 3.9V Typical Max. Units
Notes: 16-bit up/down, resettable binary counter (one counter function block). Quality Reliability section CoolRunner-II family data sheet.
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
LVCMOS LVTTL 3.3V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO -0.1 VCCIO VCCIO VCCIO Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. Units
LVCMOS 2.5V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 2.3V -0.1 VCCIO 2.3V VCCIO 2.3V VCCIO 2.3V Test Conditions Min. -0.3 VCCIO 0.4V VCCIO 0.2V Max. Units
LVCMOS 1.8V Voltage Specifications
Symbol VCCIO Parameter Input source voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 1.7V -0.1 VCCIO 1.7V VCCIO 1.7V VCCIO 1.7V Test Conditions Min. 0.65 VCCIO -0.3 VCCIO 0.45 VCCIO Max. 0.35 VCCIO 0.45 Units
1.5V Voltage Specifications(1)
Symbol VCCIO VTVOH High level output voltage level output voltage VCCIO 1.4V -0.1 VCCIO 1.4V VCCIO 1.4V VCCIO 1.4V
Notes: Hysteresis used 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. VCCIO VCCIO VCCIO 0.45 VCCIO
Max. VCCIO VCCIO
Units
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Schmitt Trigger Input Voltage Specifications
Symbol VCCIO VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. VCCIO VCCIO Max. VCCIO VCCIO Units
SSTL2-1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 2.3V VCCIO 2.3V Test Conditions Min. 1.15 VREF 0.04 VREF 0.18 -0.3 VCCIO 0.62 1.25 1.25 Max. 1.35 VREF 0.04 VREF 0.18 0.54 Units
Notes: VREF should track variations VCCIO, also peak peak noise VREF exceed VREF. transmitting device must track VREF receiving devices.
SSTL3-1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO VCCIO Test Conditions Min. VREF 0.05 VREF -0.3 VCCIO Max. VREF 0.05 VCCIO VREF Units
Notes: VREF should track variations VCCIO, also peak peak noise VREF exceed VREF. transmitting device must track VREF receiving devices.
HSTL1 Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) Parameter Input source voltage Input reference voltage Termination voltage High level input voltage level input voltage High level output voltage level output voltage VCCIO 1.7V VCCIO 1.7V Test Conditions Min. 0.68 VREF -0.3 VCCIO 0.75 VCCIO Max. 0.90 VREF Units
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Electrical Characteristics Over Recommended Operating Conditions
-6(5) Symbol TPD1 TPD2 TSUD TSU1 TSU2 FTOGGLE
Min. Max. Min. 10.0 10.0
Max. 10.0 10.2 12.5 11.6 11.5
Parameter Propagation delay single p-term Propagation delay array Direct input register set-up time Setup time fast (single p-term) Setup time array) Direct input register hold time Hold time array p-term) Clock output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time array) Direct input register p-term clock hold time P-term clock hold P-term clock output Global output enable/disable P-term output enable/disable Macrocell driven output enable/disable P-term set/reset output valid Global set/reset output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High P-term pulse width High Asynchronous preset/reset pulse width (High Low) Set-up before DataGATE latch assertion Hold DataGATE latch assertion DataGATE recovery data DataGATE pulse width CDRST setup time before falling edge GCLK2
Min.
Max.
Unit
FSYSTEM1(2) FSYSTEM2(2) FEXT1 FEXT2
TPSUD TPSU1 TPSU2 TPHD TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TSUEC THEC TPCW TAPRPW TDGSU TDGH TDGR TDGW TCDRSU
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
-6(5) Symbol TCDRH TCONFIG Configuration time Parameter CDRST hold time before falling edge GCLK2 Min. Max. Min.
Max. Min.
Max.
Unit
Notes: FTOGGLE maximum frequency flip-flop reliably toggle (see CoolRunner-II family data sheet). FSYSTEM1 (1/TCYCLE) internal operating frequency device with 16-bit resettable binary counter through p-term macrocell while FSYSTEM2 through array (one counter function block) FEXT1(1/TSU1+TCO) maximum external frequency using p-term while FEXT2 through array Typical configuration current during TCONFIG speed grade Advanced Specification.
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Internal Timing Parameters
-6(1) Symbol Buffer Delays Input buffer delay TDIN TGCK TGSR TGTS TOUT Parameter(1) Min. Max. Min. Max. Min. Max. Units
Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay
Output buffer enable/disable delay P-term Delays Control term delay TLOGI1 Single P-term delay adder TLOGI2 Multiple P-term delay adder Macrocell Delay TPDI Input output valid TSUI TECSU TECHO TCOI TAOI Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock output valid Set/reset output valid
TCDBL Clock doubler delay Feedback Delays Feedback delay TOEM Macrocell global delay Standard Time Adder Delays 1.5V TIN15 Standard input adder THYS15 TOUT15 Hysteresis input adder Output adder
TSLEW15 Output slew rate adder Standard Time Adder Delays 1.8V CMOS THYS18 Hysteresis input adder TOUT18 Output adder TSLEW Output slew rate adder Standard Time Adder Delays 2.5V CMOS TIN25 Standard input adder THYS25 TOUT25 TSLEW25 Hysteresis input adder Output adder Output slew rate adder
Notes: speed grade Advanced Specification.
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Internal Timing Parameters (Continued)
-6(1) Symbol TIN33 THYS33 TOUT33 Parameter(1) Standard input adder Hysteresis input adder Output adder Min.
Max. Min.
Max. -0.5 -0.50 Min.
Max. 0.00
Units
Standard Time Adder Delays 3.3V CMOS/TTL
TSLEW33 Output slew rate adder Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder TIN, TDIN, TGCK, TGSR, TGTS Output adder TOUT SSTL3-1 Input adder TIN, TDIN, TGCK, TGSR, TGTS Output adder TOUT HSTL-1 Input adder TIN, TDIN, TGCK, TGSR, TGTS Output adder TOUT
Notes: input signal rise/fall.
Switching Characteristics
VCCIO 1.8V, 25oC
Switching Test Conditions
Device Under Test
Test Point
TPD2 (ns)
Output Type
LVTTL33 LVCMOS33 LVCMOS25
112.5
112.5
LVCMOS18 LVCMOS15
Number Outputs Switching
DS095_02_053103
Figure Derating Curve
Notes: includes test fixtures probe capacitance. nsec maximum rise/fall times inputs.
DS092_03_092302
Figure Load Circuit
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Typical Output Curves
3.3V
(Output Current
1.8V
2.5V
1.5V
(Output Volts)
XC384_IV_050703
Figure Typical Curves XC2C384
Descriptions
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
1(GSR)
2(GTS2) 2(GTS3) 2(GTS0) 2(GTS1)
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
7(CDRST) 7(GCK1) 7(GCK0) 8(GCK2) 8(DGE)
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
AA10 AB10 AB11 AA11
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
AA22 AB22 AA21 AB21 AA20 AA19 AA18 AB18
AA17 AB17 AA16 AB16 AA15 AB15
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
Descriptions (Continued)
Function Block Macrocell TQ144 PQ208 FT256 FG324 Bank
AA14 AB14 AA13 AB13 AA12 AB12
Notes: global output enable, global reset/set, global clock, CDRST clock divide reset, DataGATE enable.
XC2C384 JTAG, Power/Ground, Connect Pins Total User
Type VAUX (JTAG supply voltage) Power internal (VCC) Power Bank (VCCIO1) Power Bank (VCCIO2) Power Bank (VCCIO3) Power Bank (VCCIO4) TQ144 109, PQ208 105, 133, 157, 172, FT256 K13, D12, J11, K11, L10, F10, FG324 AB19 AB20 AA3, N20, A20, P10, J10, J11, M14, N14, P12, J12, J13, K14,
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
XC2C384 JTAG, Power/Ground, Connect Pins Total User (Continued)
Type Ground TQ144 108, 123, PQ208 104, 129, 130, 141, 156, 177, 190, FT256 F11, G10, H10, J10, K10, L11, FG324 D18, E19, J14, K10, K11, K12, K13, L10, L11, L12, L13, M10, M11, M12, M13, N10, N11, N12, N13, P14, V19, A11,A12,A14,A15,A16,A17,B 12,B13,C11,D1,D11,D13,F3,H 20,J4,K4,L4,M4,N4,P19,P22, R19,R20,W3,W9,W13,W16,W 17,Y3,AB1
connects
Total user (includes dual function pins)
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Ordering Information
Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 1.0mm 1.0mm 0.5mm 0.5mm (C/Watt) (C/Watt) 34.1 34.1 34.1 36.1 36.1 36.1 33.5 33.5 33.5 39.3 39.3 39.3 34.1 34.1 34.1 36.1 36.1 36.1 33.5 33.5 33.5 39.3 39.3 39.3 34.1 36.1 33.5 39.3 34.1 36.1 Package Body Dimensions 20mm 20mm 20mm 20mm 20mm 20mm 28mm 28mm 28mm 28mm 28mm 28mm 17mm 17mm 17mm 17mm 17mm 17mm 23mm 23mm 23mm 23mm 23mm 23mm 20mm 20mm 20mm 20mm 20mm 20mm 28mm 28mm 28mm 28mm 28mm 28mm 17mm 17mm 17mm 17mm 17mm 17mm 23mm 23mm 23mm 23mm 23mm 23mm 20mm 20mm 28mm 28mm 17mm 17mm 23mm 23mm 20mm 20mm 28mm 28mm Comm. Ind. (I)(1)
Part Number XC2C384-6TQ144C(2) XC2C384-7TQ144C XC2C384-10TQ144C XC2C384-6PQ208C(2) XC2C384-7PQ208C XC2C384-10PQ208C XC2C384-6FT256C(2) XC2C384-7FT256C XC2C384-10FT256C XC2C384-6FG324C(2) XC2C384-7FG324C XC2C384-10FG324C XC2C384-6TQG144C(2) XC2C384-7TQG144C XC2C384-10TQG144C XC2C384-6PQG208C(2) XC2C384-7PQG208C XC2C384-10PQG208C XC2C384-6FTG256C(2) XC2C384-7FTG256C XC2C384-10FTG256C XC2C384-6FGG324C(2) XC2C384-7FGG324C XC2C384-10FGG324C XC2C384-10TQ144I XC2C384-10PQ208I XC2C384-10FT256I XC2C384-10FG324I XC2C384-10TQG144I XC2C384-10PQG208I
Package Type Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin Fine Pitch Thin Fine Pitch Thin Fine Pitch Fine Pitch Fine Pitch Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch Thin BGA; Pb-free Fine Pitch BGA; Pb-free Fine Pitch BGA; Pb-free Fine Pitch BGA; Pb-free Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin Fine Pitch Plastic Quad Flat Pack; Pb-free Plastic Quad Flat Pack; Pb-free
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
Part Number XC2C384-10FTG256I XC2C384-10FGG324I
Pin/Ball Spacing 1.0mm 1.0mm
(C/Watt) (C/Watt) 33.5 39.3
Package Type Fine Pitch Thin BGA; Pb-free Fine Pitch BGA; Pb-free
Package Body Dimensions 17mm 17mm 23mm 23mm
Comm. Ind. (I)(1)
Notes: Commercial +70°C); Industrial -40°C +85°C). Inquire with your local sales representative availability this part.
Standard Example: XC2C128 Device Speed Grade Package Type Number Pins Temperature Range
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number Pins Temperature Range
Device Part Marking
Device Type Package Speed Operating Range
XC2Cxxx TQ144
This line related device part number
Part marking non-chip scale package
Figure Sample Package with Part Marking
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX
VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO4 VCCIO4
TQ144 View
VCCIO3 VCCIO1
Figure TQ144 Thin Quad Flat Pack
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VCCIO1
I/O(2) I/O(5)
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
I/O(1) I/O(1) I/O(1) I/O(1) VAUX VCCIO2 VCCIO1 I/O(2) I/O(2) I/O(4)
I/O(3) VCCIO2 VCCIO4 VCCIO4 VCCIO4
PQ208 View
DS095 (v2.5) October 2004 Preliminary Product Specification
I/O(2) I/O(5) VCCIO1 VCCIO1 VCCIO3
VCCIO4 VCCIO3 VCCIO3
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure PQ208 Plastic Quad Flat Package
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XC2C384 CoolRunner-II CPLD
I/O(2) I/O(4) I/O(5)
I/O(3)
I/O(1)
I/O(1)
I/O(1)
I/O(1)
VCCIO4
VCCIO4 VCCIO2
VCCIO2
VAUX
VCCIO2
VCCIO4
VCCIO2
VCCIO3
VCCIO1
VCCIO3
VCCIO1
VCCIO3 VCCIO3 VCCIO1 VCCIO1
I/O(2)
I/O(2)
FT256 Bottom View
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure FT256 Fine Pitch Thin
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DS095 (v2.5) October 2004 Preliminary Product Specification
XC2C384 CoolRunner-II CPLD
I/O(3) I/O(4)
I/O(1) I/O(1)
I/O(1)
I/O(1)
VAUX
VCCIO4 VCCIO4 VCCIO2 VCCIO2
VCCIO4
VCCIO2
VCCIO4
VCCIO2
VCCIO3
VCCIO1
VCCIO3
VCCIO1
VCCIO3 VCCIO3 VCCIO1 VCCIO1
I/O(2)
I/O(2)
I/O(5)
I/O(2)
FG324 Bottom View
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset DataGATE Enable
Figure FG324 Fine Pitch
Additional Information
CoolRunner-II Datasheets Application Notes Device Packages
DS095 (v2.5) October 2004 Preliminary Product Specification
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XC2C384 CoolRunner-II CPLD
Revision History
following table shows revision history this document. Date 5/31/02 9/23/02 4/16/03 5/30/03 11/7/03 1/26/04 5/7/04 8/03/04 10/01/04 Version Initial Xilinx release. Updated FT256 TQ144 pinouts. Updated FG324 package, updated Connect pins. Added characterization data. Corrected typo page 324-ball package ball pitch 1.0mm. Added links Application notes Datasheets. Corrected error package dimensions XC2C384-10TQ144I. Pb-free documentation Asynchronous Preset/Reset Pulse Width specification Electrical Characteristics. Revision
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DS095 (v2.5) October 2004 Preliminary Product Specification
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