System Solution DS088 (v1.2) June 2002 Advance Product Speci
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System Solution
DS088 (v1.2) June 2002
Advance Product Specification
Summary
System-level, high-capacity, pre-configured solution VirtexSeries FPGAs, Virtex-II Series Platform FPGAs, SpartanFPGAs Industry standard Flash memory combined with Xilinx controller technology Effortless density migration from Megabits (Mb) I/O: 1.8V, 2.5V, 3.3V Configuration rates second (Mb/s) Flexible configuration solution Slave-SelectMAP Slave-Serial Concurrent Slave-Serial eight separate chains) Patented compression technology compression) JTAG interface allows: Access standard Flash memory Boundary scan testing Native interface Flash memory accessible for: In-system parallel programming Processor access unused Flash memory locations Supports eight separate design sets (selectable mode pins JTAG) enabling systems reconfigure FPGAs different functions Compatibility with IEEE Standard 1532 User-friendly software format program bitstreams into standard Flash patented Flash programming engine Internet Reconfigurable Logic (IRL) upgradable system
Description
System ACESoft Controller (SC) solution addresses need space-efficient, pre-engineered, high-density configuration solution multiple FPGA systems. System technology ground-breaking in-system programmable configuration solution that provides substantial savings development effort cost over traditional PROM embedded solutions high capacity FPGA systems. System solution identical, terms features functionality, System solution. power-up, System (XCV50E-6CS144) controller reads bitstream data from Flash memory unit delivers bitstream data more target FPGAs using Slave-Serial SelectMAP FPGA configuration protocols. target FPGAs reconfigured anytime with eight possible user design sets. System supports in-system reprogramming Flash memory unit. Whereas, System solution pre-packages Flash memory unit Virtex-E-based configuration controller single BG388 package, System provides freedom select place individual components desired board. System solution offers System configuration controller technology pre-designed bitstream form file. System controller four major interfaces. (See Figure Boundary Scan JTAG interface provided Boundary Scan test Boundary Scan-based Flash memory programming. system control interface provides input system clock, design selection pins, system configuration control signals, system configuration status signals. Flash memory interface connects external Flash memory unit reading stored FPGA bitstream data reprogramming Flash memory in-system. target FPGA interface provides signals configure target FPGAs Slave-Serial, concurrent Slave-Serial, SelectMAP configuration modes. Separate power pins provide voltage compatibility control target FPGA configuration interface system control/status interface. Refer System data sheet (DS087) descriptions System configuration model, System configuration performance, System software, Flash memory programming support. Differences between System System noted System System Differences section.
2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution
Boundary Scan Interface
System Configuration Controller
(XCV50E-6CS144)
System Control Interface
JTAG
Controller State Machine
Configuration Formatter SelectMAP Target FPGA Interface
Flash
Decompressor Flash Memory Interface
Slave Serial
ds088_01_091701
Figure System Interfaces
System Solution Components
complete System solution comprised Virtex-E (XCV50E-6CS144) configuration controller, XC17V01 configuration PROM, Flash memory unit, passive components. Figure complete view components schematic signals between System components. Specific information described Pinout Descriptions section.
XCV50E-6CS144 Configuration Controller
System configuration controller design available Virtex-E (XCV50E-6CS144) FPGA (Table Table Configuration Controller Device Information Device Type XCV50E Speed Grade Package CS144
Notes: System configuration controller design available only CS144 package.
System Solution
Specific information XCV50E available Virtex-E FPGA Family data sheets (Table
Flash Memory
Configuration Controller (XCV50E-6CS144)
XC17V01 PROM
Target Trge Target FPGAs FPGAs FPGAs
ds088_02_091701
Figure System Components
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table Virtex-E Data Sheets Description Virtex-E Introduction Ordering Information Virtex-E Detailed Functional Description Virtex-E Switching Characteristics Virtex-E Pinout Tables Location
XC17V01 Configuration PROM
System configuration controller design available Intel Extended Hexadecimal Format (Xilinx extension) file format. controller design stored XC17V01 PROM. power-up, XC17V01 PROM configures XCV50E-6CS144 FPGA with System configuration controller design. Specific information XC17V01 PROM available XC17V00 Series Configuration PROM data sheet
Flash Memory
System stores target FPGA bitstream data Flash memory. Flash memory densities supported. Table Flash memory data sheets additional information.
Table Supported Flash Memory Device Product Numbers Flash Device Product Number Am29LV160DT-90 Am29LV160DB-90 AM29LV320DT90 AM29LV320DB90 AM29LV641DH90R AM29LV641DL90R Flash Density Flash Speed Grade Flash Organization 16-bit 8-bit) 16-bit 8-bit) 16-bit
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution
Pinout Descriptions
components System solution connected shown Figure Specific information shown tables below. Separate power pins provide voltage compatibility control target FPGA configuration interface system control/status interface.
System
JTAG Interface
RESET
4.7k
Flash
RESET A0-A21 DQ0-DQ15 /BYTE ACC/WP RY/BY
FLASH_IO_LEVEL
Native Flash Interface
Voltage
A0-A21 DQ0-DQ15 RY/BY FCM_ENABLE FLASH_VCCO CFG_VCCO CTRL_VCCO
3.3v 4.7k RESET CCLK A0-A21 DQ0-DQ15 INIT DONE PROGRAM RY/BY FCM_ENABLE SYSRESET SYSCLK BITSTRSEL[0-2] STATUS[0-3] CFG_MODE[0-2] CFG_CLK CFG_BUSY CFG_INIT CFG_DONE VCCO2,3, CFG_PROG CFG_WRITE VCCO6,7 CFG_CS[0-3] VCCO0,1 CFG_DATA[0-7]
XCV50E Controller
3.3v 3.3v 4.7k
XC17V01
DATA OE/Reset
DEVRDY FCMRESET SYSRESET SYSCLK BITSTRSEL[0-2] STATUS[0-3] CFG_MODE[0-2] CFG_CLK CFG_BUSY CFG_INIT CFG_DONE CFG_PROG CFG_WRITE CFG_CS[0-3] CFG_DATA[0-7]
System Control Interface
FPGA Configuration Interface
Am29LV641D only; Am29LV320D Am29LV641D only; Am29LV641D, /BYTE Am29LV160D Am29LV320D; Am29LV641D. connect Am29LV160D; apply ACC/WP Am29LV320D; Am29LV641D. RY/BY Am29LV160D Am29LV320D; Am29LV641D. Am29LV641D only. apply /RESET.
ds088_03_091701
Figure System Schematic
XCV50E Control Status Pins
Table provides control status pins. Table XCV50E Control Status Pins CS144 Name FCM_ENABLE Type Input Description Enables System flash controller module. FCM_ENABLE disable flash control signals allow external device access Flash memory. Controller system clock (maximum frequency MHz). Controller system reset. When pulsed High, SYSRESET resets target FPGAs, samples BITSTRSEL[2:0] pins, downloads corresponding data set. Data select Data select Data select Status Status
SYSCLK SYSRESET
Input Input
BITSTRSEL[0] BITSTRSEL[1] BITSTRSEL[2] STATUS[0] STATUS[1]
Input Input Input Output Output
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table XCV50E Control Status Pins (Continued) CS144 Name STATUS[2] STATUS[3] Type Output Output Status Status Description
Notes: XCV50E pins listed tables below connects.
XCV50E Configuration Pins Target FPGAs
Table provides configuration pins target FPGAs. Table XCV50E Configuration Pins Target FPGAs CS144 Name CFG_MODE[0] CFG_MODE[1] CFG_MODE[2] CFG_CLK CFG_PROG CFG_INIT CFG_BUSY CFG_DONE CFG_DATA[0] CFG_DATA[1] CFG_DATA[2] CFG_DATA[3] CFG_DATA[4] CFG_DATA[5] CFG_DATA[6] CFG_DATA[7] CFG_WRITE CFG_CS[0] Type Output Output Output Output Output Input Input Input Output Output Output Output Output Output Output Output Output Output Description FPGA configuration mode control signal, FPGA configuration mode control signal, FPGA configuration mode control signal, FPGA configuration clock (CCLK). half SYSCLK rate. FPGA configuration reset signal, PROGRAM. external pull-up resistor CFG_VCCO recommended. FPGA configuration INIT signal monitor. external pull-up resistor CFG_VCCO required. FPGA SelectMAP configuration BUSY signal monitor. FPGA configuration DONE signal monitor. external pull-up resistor CFG_VCCO required. SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP configuration bus; first FPGA Slave-Serial chain SelectMAP read/write control signal (RDWR_B). connect Slave-Serial configuration. SelectMAP chip select Connect SelectMAP FPGA connect Slave-Serial configuration.
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution Table XCV50E Configuration Pins Target FPGAs (Continued) CS144 Name CFG_CS[1] CFG_CS[2] CFG_CS[3] Type Output Output Output Description SelectMAP chip select Connect SelectMAP FPGA connect Slave-Serial configuration. SelectMAP chip select Connect SelectMAP FPGA connect Slave-Serial configuration. SelectMAP chip select Connect SelectMAP FPGA connect Slave-Serial configuration.
XCV50E Boundary Scan Pins
Table provides Boundary Scan pins. Table XCV50E Boundary Scan Pins CS144 Name
XCV50E Power Ground Pins
Table provides XCV50E power ground pins. Table XCV50E Power Ground Pins XCV50E Name VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO (Bank CS144 System Name VCCint1 VCCint1 VCCint1 VCCint1 VCCint1 VCCint1 VCCint1 VCCint1 CTRL_VCCO Description 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V power supply XCV50E core. 1.8V, 2.5V, 3.3V power supply control status pins. voltage that compatible with system control monitoring logic. 1.8V, 2.5V, 3.3V power supply control status pins. voltage that compatible with system control monitoring logic. 1.8V, 2.5V, 3.3V power supply control status pins. voltage that compatible with system control monitoring logic. 3.3V power supply flash interface pins. 3.3V power supply flash interface pins.
VCCO (Bank
CTRL_VCCO
VCCO (Bank
CTRL_VCCO
VCCO (Bank VCCO (Bank
FLASH_VCCO FLASH_VCCO
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table XCV50E Power Ground Pins (Continued) XCV50E Name VCCO (Bank VCCO (Bank VCCO (Bank VCCO (Bank VCCO (Bank CS144 System Name FLASH_VCCO FLASH_VCCO FLASH_VCCO FLASH_VCCO CFG_VCCO Description 3.3V power supply flash interface pins. 3.3V power supply flash interface pins. 3.3V power supply flash interface pins. 3.3V power supply flash interface pins. 1.8V, 2.5V, 3.3V power supply target FPGA configuration interface pins. voltage that compatible with target FPGA configuration pins. 1.8V, 2.5V, 3.3V power supply target FPGA configuration interface pins. voltage that compatible with target FPGA configuration pins. 1.8V, 2.5V, 3.3V power supply target FPGA configuration interface pins. voltage that compatible with target FPGA configuration pins. Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
VCCO (Bank
CFG_VCCO
VCCO (Bank
CFG_VCCO
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution
XCV50E XC17V01 Configuration Connections
Table provides XCV50E configuration connections from XC17V01 device. Table XCV50E Configuration Connections from XC17V011 Device XCV50E Name PROGRAM (FCMRESET) DIN/D0 CCLK INIT DONE (DEVRDY) CS144 DATA OE/Reset /CEO pull-up resistor 3.3V pull-up resistor 3.3V connect 3.3V 3.3V XC17V01 Name SO20 PC20 External Connection pull-up resistor 3.3V
Notes: Unlisted XC17V01 pins connects, i.e., must externally connected. XC17V01 device must programmed with active-low Reset polarity.
Flash Memory Configuration Storage Devices
System supports configuration data storage Flash memories.
XCV50E Am29LV160D Flash Memory Connections
Table provides XCV50E Am29LV160D Flash memory connections. Table XCV50E Am29LV160D Flash Memory Connections XCV50E CS144 Am29LV160D Name 48-Pin TSOP 48-Pin Reverse TSOP 48-Ball FBGA External Connection
44-Pin
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table XCV50E Am29LV160D Flash Memory Connections (Continued) XCV50E CS144 Am29LV160D Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 BYTE RESET RY/BY 48-Pin TSOP 48-Pin Reverse TSOP 48-Ball FBGA External pull-down resistor required. 3.3V External Connection
44-Pin
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution Table XCV50E Am29LV160D Flash Memory Connections (Continued) XCV50E CS144 Am29LV160D Name 48-Pin TSOP 48-Pin Reverse TSOP 48-Ball FBGA External Connection 3.3V
44-Pin
XCV50E Am29LV320D Flash Memory Connections
Table provides XCV50E device connections Am29LV320D Flash memory. Table XCV50E Am29LV320D Flash Memory Connections XCV50E CS144 Am29LV320D Name 48-Pin TSOP 48-Ball FBGA External Connection
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table XCV50E Am29LV320D Flash Memory Connections (Continued) XCV50E CS144 Am29LV320D Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 BYTE WP/ACC RESET RY/BY 48-Pin TSOP 48-Ball FBGA 3.3V Connect 3.3V migration Flash. External pull-down resistor required. 3.3V External Connection
XCV50E Am29LV641D Flash Memory Connections
Table provides XCV50E connections Am29LV641D Flash memory. Table XCV50E Am29LV641D Flash Memory Connections XCV50E CS144 Am29LV641D Name 48-Pin TSOP 48-Pin Reverse TSOP External Connection
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution Table XCV50E Am29LV641D Flash Memory Connections (Continued) XCV50E CS144 Am29LV641D Name DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 48-Pin TSOP 48-Pin Reverse TSOP 3.3V External Connection
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DS088 (v1.2) June 2002 Advance Product Specification
System Solution
Table XCV50E Am29LV641D Flash Memory Connections (Continued) XCV50E CS144 Am29LV641D Name RESET 48-Pin TSOP 48-Pin Reverse TSOP 3.3V External pull-down resistor required. 3.3V External Connection
System System Differences
IEEE 1149.1 Boundary Scan
System solution pairs XC17V01 one-time programmable (OTP) PROM with XCV50E configuration controller. Whereas System includes XC18V01 in-system programmable (ISP) PROM Boundary Scan chain with configuration controller,
System controller does have companion PROM scan chain. Thus, performance System Boundary Scan capable operating faster Boundary Scan frequencies supported Virtex-E devices. Figure
Flash
A0-A21 DQ0-DQ15 /BYTE ACC/WP RY/BY RESET
XCV50E Controller
A0-A21 DQ0-DQ15 RY/BY RESET Boundary-Scan Register
Am29LV641D only; Am29LV320D Am29LV641D only; Am29LV641D, BYTE Am29LV160D Am29LV320D; Am29LV641D. connect Am29LV160D; ACC/WP Am29LV320D; Am29LV641D. RY/BY Am29LV160D Am29LV320D; Am29LV641D. Am29LV641D only. Boundary-scan register only conceptually depicted. System BSDL file accurate boundaryscan register information. ds088_04_091701
Figure System Boundary Scan Model
DS088 (v1.2) June 2002 Advance Product Specification
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System Solution
Boundary Scan Parameters
Table provides System Boundary Scan parameters. Table System Boundary Scan Parameters Symbol TTAPTK TTCKTAP TTCKTDO FTCK Description setup times before hold times after Delay from Maximum frequency Value Units MHz,
System Files
Table lists System files System controller solutions. file program XC17V01 PROM that configures System controller. Table System Files System Controller XCV50E-6CS144 XCV50E-6CS144 XCV50E-6CS144 Flash Memory Am29LV160D Am29LV320D Am29LV641D Density File XCCACEM16-CS144-AM.MCS XCCACEM32-CS144-AM.MCS XCCACEM64-CS144-AM.MCS
Revision History
following table shows revision history this document. Date 09/25/01 01/21/02 06/07/02 Version Initial Xilinx release. Minor edits done. Added "Virtex Series FPGAs" "Virtex-II Platform FPGAs" Summary. Revision
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DS088 (v1.2) June 2002 Advance Product Specification
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