VirtexTM-E Extended Memory Field Programmable Gate Arrays DS025-1

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VirtexTM-E Extended Memory Field Programmable Gate Arrays DS025-1

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VirtexTM-E Extended Memory Field Programmable Gate Arrays
DS025-1 (v1.5) July 2002
Production Product Specification
Features
Fast, Extended Block RAM, FPGA Family 1,120 embedded block internal performance (four levels) compliant 32/64-bit, 33/66-MHz Sophisticated SelectRAM+Memory Hierarchy internal configurable distributed 1,120 synchronous internal block True Dual-Port block Memory bandwidth 2.24 Tb/s (equivalent bandwidth over RAMBUS channels) Designed high-performance Interfaces external memories ZBT* SRAMs Mb/s SDRAMs Highly Flexible SelectIO+Technology Supports high-performance interface standards singled-ended I/Os differential pairs aggregate bandwidth >100 Gb/s Complete Industry-Standard Differential Signalling Support LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL signals input, output, bi-directional
trademark Integrated Device Technology, Inc.
LVPECL LVDS clock inputs 300+ clocks Proprietary High-Performance SelectLinkTechnology Gb/s chip-to-chip communication link Support Double Data Rate (DDR) interface Web-based generation methodology Eight Fully Digital Delay-Locked Loops (DLLs) IEEE 1149.1 boundary-scan logic Supported Xilinx Foundation Seriesand Alliance SeriesDevelopment Systems Internet Team Design (Xilinx iTDTM) tool ideal million-plus gate density designs Wide selection workstation platforms SRAM-based In-System Configuration Unlimited re-programmability Advanced Packaging Options FG676 FG900 1.27 BG560 0.18 6-layer Metal Process with Copper Interconnect 100% Factory Tested
Introduction
VirtexTM-E Extended Memory (Virtex-EM) family FPGAs extension highly successful Virtex-E family architecture. Virtex-EM family (devices shown Table includes features Virtex-E, plus additional block RAM, useful applications such network switches high-performance video graphic systems. Xilinx developed Virtex-EM product family enable customers design systems requiring high memory bandwidth, such Gb/s network switches. Unlike traditional ASIC devices, this family also supports fast time-to-market delivery, because development engineering already completed. Just complete design program device. There NRE, silicon production cycles, additional delays design re-work. addition, designers update design over network time, providing product upgrades updates customers even sooner. Virtex-EM family result more than fifteen years FPGA design experience. Xilinx history supporting customer applications providing highest level logic, RAM, features available industry. Virtex-EM family, first FPGAs deploy copper interconnect, offers performance high memory bandwidth advanced system integration without initial investment, long development cycles, inventory risk expected traditional ASIC development.
2000-2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS025-1 (v1.5) July 2002 Production Product Specification
www.xilinx.com 1-800-255-7778
Module
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Table Virtex-E Extended Memory Field-Programmable Gate Array Family Members Device XCV405E XCV812E Logic Gates 129,600 254,016 Array Logic Cells 10,800 21,168 Differential Pairs User BlockRAM Bits 573,440 1,146,880 Distributed Bits 153,600 301,056
Virtex-E Compared Virtex Devices
Virtex-E family offers 43,200 logic cells devices faster than Virtex family. performance increased Mb/s using Source Synchronous data transmission architectures synchronous system performance using singled-ended SelectI/O technology. Additional standards supported, notably LVPECL, LVDS, BLVDS, which pins signal. Almost signal pins used these standards. Virtex-E devices have faster (250MHz) block SelectRAM, individual RAMs same size structure Virtex family. They also have eight DLLs instead four Virtex devices. Each individual slightly improved with easier clock mirroring frequency multiplication. VCCINT, supply voltage internal logic memory, instead Virtex devices. Advanced processing 0.18 design rules have resulted smaller dice, faster speed, lower power consumption. pins tolerant, tolerant with external resistor. supported. With addition appropriate external resistors, tolerate voltage desired. Banking rules different. With Virtex devices, input buffers powered VCCINT. With Virtex-E devices, LVTTL, LVCMOS2, input buffers powered supply voltage VCCO. Virtex-E family bitstream-compatible with Virtex family, Virtex designs compiled into equivalent Virtex-E devices. same device same package Virtex-E Virtex families pin-compatible with some minor exceptions. data sheet pinout section details.
natives mask-programmed gate arrays. Virtex-E family includes nine members Table Building experience gained from Virtex FPGAs, Virtex-E family evolutionary step forward programmable logic design. Combining wide variety programmable system features, rich hierarchy fast, flexible interconnect resources, advanced process technology, Virtex-E family delivers high-speed high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature flexible, regular architecture that comprises array configurable logic blocks (CLBs) surrounded programmable input/output blocks (IOBs), interconnected rich hierarchy fast, versatile routing resources. abundance routing resources permits Virtex-E family accommodate even largest most complex designs. Virtex-E FPGAs SRAM-based, customized loading configuration data into internal memory cells. Configuration data read from external SPROM (master serial mode), written into FPGA (SelectMAPTM, slave serial, JTAG modes). standard Xilinx Foundation Seriesand Alliance SeriesDevelopment systems deliver complete design support Virtex-E, covering every aspect from behavioral schematic entry, through simulation, automatic design translation implementation, creation downloading configuration stream.
Higher Performance
Virtex-E devices provide better performance than previous generations FPGAs. Designs achieve synchronous system clock rates including Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with specifications, interfaces implemented that operate MHz. While performance design-dependent, many designs operate internally speeds excess achieve over MHz. Table page shows performance data representative circuits, using worst-case timing parameters.
General Description
Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases silicon efficiency result from optimizing architecture place-and-route efficiency exploiting aggressive 6-layer metal 0.18 CMOS process. These advances make Virtex-E FPGAs powerful flexible alter-
Module
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DS025-1 (v1.5) July 2002 Production Product Specification
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Table Performance Common Circuit Functions Function
Register-to-Register
Bits
Virtex-E
Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree
Chip-to-Chip
HSTL Class LVTTL,16mA, fast slew LVDS LVPECL
Virtex-E Extended Memory Device/Package Combinations Maximum
Table Virtex-EM Family Maximum User Device/Package (Excluding Dedicated Clock Pins) Package BG560 FG676 FG900 XCV405E XCV812E
Virtex-E Extended Memory Ordering Information
Example: XCV405E-6BG560C
Device Type Temperature Range Commercial +85°C) Industrial -40°C +100°C) Number Pins Package Type Ball Grid Array Fine Pitch Ball Grid Array
DS025_001_11200
Speed Grade (-6,
Figure Virtex Ordering Information
DS025-1 (v1.5) July 2002 Production Product Specification
www.xilinx.com 1-800-255-7778
Module
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Revision History
following table shows revision history this document. Date 03/23/00 08/01/00 Version Initial Xilinx release. Accumulated edits fixes. Upgrade Preliminary. Preview numbers added. Reformatted adhere corporate documentation style guidelines. Minor changes BG560 pin-out table. 04/02/01 07/17/02 Table (Module FG676 Fine-Pitch XCV405E, following pins longer labeled VREF: G16, G26, W26, AF20, AF8, values added Virtex-E Electrical Characteristics tables. Updated speed grade numbers Virtex-E Electrical Characteristics tables (Module Updated minimums Table (Module added notes Table (Module Added note Absolute Maximum Ratings (Module Changed minimum hold times -0.4 Global Clock Set-Up Hold LVTTL Standard, with (Module Revised maximum TDLLPW speed grade Timing Parameters (Module Table FG676 Fine-Pitch XCV405E, longer labeled VREF, labeled VREF. Updated values Virtex-E Switching Characteristics tables. Converted data sheet modularized format. Virtex-E Extended Memory Data Sheet, below. Data sheet designation upgraded from Preliminary Production. Revision
09/19/0
11/20/0
Virtex-E Extended Memory Data Sheet
Virtex-E Extended Memory Data Sheet contains following modules: DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction Ordering Information (Module
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
Switching Characteristics (Module
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module
Module
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DS025-1 (v1.5) July 2002 Production Product Specification

VirtexTM-E Extended Memory Field Programmable Gate Arrays DS025-1

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