VirtexTM-E Extended Memory Field Programmable Gate Arrays DS025-1
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
DS025-1 (v1.5) July 2002
Production Product Specification
Features
Fast, Extended Block RAM, FPGA Family 1,120 embedded block internal performance (four levels) compliant 32/64-bit, 33/66-MHz Sophisticated SelectRAM+Memory Hierarchy internal configurable distributed 1,120 synchronous internal block True Dual-Port block Memory bandwidth 2.24 Tb/s (equivalent bandwidth over RAMBUS channels) Designed high-performance Interfaces external memories ZBT* SRAMs Mb/s SDRAMs Highly Flexible SelectIO+Technology Supports high-performance interface standards singled-ended I/Os differential pairs aggregate bandwidth >100 Gb/s Complete Industry-Standard Differential Signalling Support LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL signals input, output, bi-directional
trademark Integrated Device Technology, Inc.
LVPECL LVDS clock inputs 300+ clocks Proprietary High-Performance SelectLinkTechnology Gb/s chip-to-chip communication link Support Double Data Rate (DDR) interface Web-based generation methodology Eight Fully Digital Delay-Locked Loops (DLLs) IEEE 1149.1 boundary-scan logic Supported Xilinx Foundation Seriesand Alliance SeriesDevelopment Systems Internet Team Design (Xilinx iTDTM) tool ideal million-plus gate density designs Wide selection workstation platforms SRAM-based In-System Configuration Unlimited re-programmability Advanced Packaging Options FG676 FG900 1.27 BG560 0.18 6-layer Metal Process with Copper Interconnect 100% Factory Tested
Introduction
VirtexTM-E Extended Memory (Virtex-EM) family FPGAs extension highly successful Virtex-E family architecture. Virtex-EM family (devices shown Table includes features Virtex-E, plus additional block RAM, useful applications such network switches high-performance video graphic systems. Xilinx developed Virtex-EM product family enable customers design systems requiring high memory bandwidth, such Gb/s network switches. Unlike traditional ASIC devices, this family also supports fast time-to-market delivery, because development engineering already completed. Just complete design program device. There NRE, silicon production cycles, additional delays design re-work. addition, designers update design over network time, providing product upgrades updates customers even sooner. Virtex-EM family result more than fifteen years FPGA design experience. Xilinx history supporting customer applications providing highest level logic, RAM, features available industry. Virtex-EM family, first FPGAs deploy copper interconnect, offers performance high memory bandwidth advanced system integration without initial investment, long development cycles, inventory risk expected traditional ASIC development.
2000-2002 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS025-1 (v1.5) July 2002 Production Product Specification
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Table Virtex-E Extended Memory Field-Programmable Gate Array Family Members Device XCV405E XCV812E Logic Gates 129,600 254,016 Array Logic Cells 10,800 21,168 Differential Pairs User BlockRAM Bits 573,440 1,146,880 Distributed Bits 153,600 301,056
Virtex-E Compared Virtex Devices
Virtex-E family offers 43,200 logic cells devices faster than Virtex family. performance increased Mb/s using Source Synchronous data transmission architectures synchronous system performance using singled-ended SelectI/O technology. Additional standards supported, notably LVPECL, LVDS, BLVDS, which pins signal. Almost signal pins used these standards. Virtex-E devices have faster (250MHz) block SelectRAM, individual RAMs same size structure Virtex family. They also have eight DLLs instead four Virtex devices. Each individual slightly improved with easier clock mirroring frequency multiplication. VCCINT, supply voltage internal logic memory, instead Virtex devices. Advanced processing 0.18 design rules have resulted smaller dice, faster speed, lower power consumption. pins tolerant, tolerant with external resistor. supported. With addition appropriate external resistors, tolerate voltage desired. Banking rules different. With Virtex devices, input buffers powered VCCINT. With Virtex-E devices, LVTTL, LVCMOS2, input buffers powered supply voltage VCCO. Virtex-E family bitstream-compatible with Virtex family, Virtex designs compiled into equivalent Virtex-E devices. same device same package Virtex-E Virtex families pin-compatible with some minor exceptions. data sheet pinout section details.
natives mask-programmed gate arrays. Virtex-E family includes nine members Table Building experience gained from Virtex FPGAs, Virtex-E family evolutionary step forward programmable logic design. Combining wide variety programmable system features, rich hierarchy fast, flexible interconnect resources, advanced process technology, Virtex-E family delivers high-speed high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Virtex-E Architecture
Virtex-E devices feature flexible, regular architecture that comprises array configurable logic blocks (CLBs) surrounded programmable input/output blocks (IOBs), interconnected rich hierarchy fast, versatile routing resources. abundance routing resources permits Virtex-E family accommodate even largest most complex designs. Virtex-E FPGAs SRAM-based, customized loading configuration data into internal memory cells. Configuration data read from external SPROM (master serial mode), written into FPGA (SelectMAPTM, slave serial, JTAG modes). standard Xilinx Foundation Seriesand Alliance SeriesDevelopment systems deliver complete design support Virtex-E, covering every aspect from behavioral schematic entry, through simulation, automatic design translation implementation, creation downloading configuration stream.
Higher Performance
Virtex-E devices provide better performance than previous generations FPGAs. Designs achieve synchronous system clock rates including Mb/s using Source Synchronous data transmission architechtures. Virtex-E I/Os comply fully with specifications, interfaces implemented that operate MHz. While performance design-dependent, many designs operate internally speeds excess achieve over MHz. Table page shows performance data representative circuits, using worst-case timing parameters.
General Description
Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases silicon efficiency result from optimizing architecture place-and-route efficiency exploiting aggressive 6-layer metal 0.18 CMOS process. These advances make Virtex-E FPGAs powerful flexible alter-
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DS025-1 (v1.5) July 2002 Production Product Specification
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Table Performance Common Circuit Functions Function
Register-to-Register
Bits
Virtex-E
Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree
Chip-to-Chip
HSTL Class LVTTL,16mA, fast slew LVDS LVPECL
Virtex-E Extended Memory Device/Package Combinations Maximum
Table Virtex-EM Family Maximum User Device/Package (Excluding Dedicated Clock Pins) Package BG560 FG676 FG900 XCV405E XCV812E
Virtex-E Extended Memory Ordering Information
Example: XCV405E-6BG560C
Device Type Temperature Range Commercial +85°C) Industrial -40°C +100°C) Number Pins Package Type Ball Grid Array Fine Pitch Ball Grid Array
DS025_001_11200
Speed Grade (-6,
Figure Virtex Ordering Information
DS025-1 (v1.5) July 2002 Production Product Specification
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Revision History
following table shows revision history this document. Date 03/23/00 08/01/00 Version Initial Xilinx release. Accumulated edits fixes. Upgrade Preliminary. Preview numbers added. Reformatted adhere corporate documentation style guidelines. Minor changes BG560 pin-out table. 04/02/01 07/17/02 Table (Module FG676 Fine-Pitch XCV405E, following pins longer labeled VREF: G16, G26, W26, AF20, AF8, values added Virtex-E Electrical Characteristics tables. Updated speed grade numbers Virtex-E Electrical Characteristics tables (Module Updated minimums Table (Module added notes Table (Module Added note Absolute Maximum Ratings (Module Changed minimum hold times -0.4 Global Clock Set-Up Hold LVTTL Standard, with (Module Revised maximum TDLLPW speed grade Timing Parameters (Module Table FG676 Fine-Pitch XCV405E, longer labeled VREF, labeled VREF. Updated values Virtex-E Switching Characteristics tables. Converted data sheet modularized format. Virtex-E Extended Memory Data Sheet, below. Data sheet designation upgraded from Preliminary Production. Revision
09/19/0
11/20/0
Virtex-E Extended Memory Data Sheet
Virtex-E Extended Memory Data Sheet contains following modules: DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction Ordering Information (Module
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
Switching Characteristics (Module
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module
Module
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DS025-1 (v1.5) July 2002 Production Product Specification
VirtexTM-E Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.3) November 2002
Production Product Specification
Architectural Description
Virtex-E Array
Virtex-E user-programmable gate array (see Figure comprises major configurable elements: configurable logic blocks (CLBs) input/output blocks (IOBs). CLBs provide functional elements constructing logic. IOBs provide interface between package pins CLBs. CLBs interconnect through general routing matrix (GRM). comprises array routing switches located intersections horizontal vertical routing channels. Each nests into VersaBlockthat also provides local routing resources connect GRM. VersaRingI/O interface provides additional routing resources around periphery device. This routing improves routability facilitates locking. Virtex-E architecture also includes following circuits that connect GRM: Dedicated block memories 4096 bits each Clock DLLs clock-distribution delay compensation clock domain control 3-State buffers (BUFTs) associated with each that drive dedicated segmentable horizontal routing resources
DLLDLL
DLLDLL
Values stored static memory cells control configurable logic elements interconnect resources. These values load into memory cells power-up, reload necessary change function device.
Input/Output Block
Virtex-E IOB, Figure features SelectIO+inputs outputs that support wide variety signalling standards (see Table
Weak Keeper
OBUFT
Programmable Delay IBUF Vref
ds022_02_09130
Figure Virtex-E Input/Output Block (IOB)
VersaRing
three storage elements function either edge-triggered D-type flip-flops level-sensitive latches. Each clock signal (CLK) shared three flip-flops independent clock enable signals each flip-flop.
BRAMs CLBs
BRAMs
BRAMs
BRAMs
CLBs
CLBs
CLBs
IOBs
IOBs
VersaRing
DLLDLL
DLLDLL
ds022_001_121099
Figure Virtex-E Architecture Overview
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DS025-2 (v2.3) November 2002
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VirtexTM-E Extended Memory Field Programmable Gate Arrays Table Supported Standards Board Termination Voltage (VTT) 1.50 1.25 1.20 1.50 0.75 1.50 1.50
Virtex-E IOBs support IEEE 1149.1-compatible boundary scan testing.
Input Path
Virtex-E input path routes input signal directly internal logic and/ through optional input flip-flop. optional delay element D-input this flip-flop eliminates pad-to-pad hold time. delay matched internal clock-distribution delay FPGA, when used, assures that pad-to-pad hold time zero. Each input buffer configured conform low-voltage signalling standards supported. some these standards input buffer utilizes user-supplied threshold voltage, VREF. need supply VREF imposes constraints which standards used close proximity each other. "I/O Banking" page There optional pull-up pull-down resistors each user input after configuration. Their value range
Standard LVTTL LVCMOS2 LVCMOS18 SSTL3 SSTL2 GTL+ HSTL HSTL AGP-2X PCI33_3 PCI66_3 BLVDS LVDS LVPECL
Output VCCO
Input VCCO
Input VREF 1.50 1.25 0.80 0.75 0.90 1.50 1.32
Output Path
output path includes 3-state output buffer that drives output signal onto pad. output signal routed buffer directly from internal logic through optional output flip-flop. 3-state control output also routed directly from internal logic through flip-flip that provides synchronous enable disable. Each output driver individually programmed wide range low-voltage signalling standards. Each output buffer source sink Drive strength slew rate controls minimize transients. most signalling standards, output High voltage depends externally supplied VCCO voltage. need supply VCCO imposes constraints which standards used close proximity each other. "I/O Banking" page optional weak-keeper circuit connected each output. When selected, circuit monitors voltage weakly drives High match input signal. connected multiple-source signal, weak keeper holds signal last state drivers disabled. Maintaining valid logic level this eliminates chatter. Since weak-keeper circuit uses input buffer monitor input level, appropriate VREF voltage must provided signalling standard requires one. provision this voltage must comply with banking rules.
addition control signals, three flip-flops share Set/Reset (SR). each flip-flop, this signal independently configured synchronous Set, synchronous Reset, asynchronous Preset, asynchronous Clear. output buffer control signals have independent polarity controls. pads protected against damage from electrostatic discharge (ESD) from over-voltage transients. After configuration, clamping diodes connected VCCO with exception LVCMOS18, LVCMOS25, GTL, GTL+, LVDS, LVPECL. Optional pull-up, pull-down weak-keeper circuits attached each pad. Prior configuration outputs involved configuration forced into their high-impedance state. pull-down resistors weak-keeper circuits inactive, optionally pulled activation pull-up resistors prior configuration controlled global basis configuration mode pins. pull-up resistors activated, pins high-impedance state. Consequently, external pull-up pull-down resistors must provided pins required well-defined logic level prior configuration.
Banking
Some standards described above require VCCO and/or VREF voltages. These voltages externally supplied connected device pins that serve groups
DS025-2 (v2.3) November 2002
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VirtexTM-E Extended Memory Field Programmable Gate Arrays Some input standards require user-supplied threshold voltage, VREF. this case, certain user-I/O pins automatically configured inputs VREF voltage. Approximately pins bank assume this role. VREF pins within bank interconnected internally consequently only VREF voltage used within each bank. VREF pins bank, however, must connected external voltage source correct operation. Within bank, inputs that require VREF mixed with those that not. However, only VREF voltage used within bank. Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards supplied VCCO rather than VCCINT. these standards, only input output buffers that have same VCCO mixed together. VCCO VREF pins each bank appear device pin-out tables diagrams. diagrams also show bank affiliation each I/O. Within given package, number VREF VCCO pins vary depending size device. larger devices, more pins convert VREF pins. Since these always super VREF pins used smaller devices, possible design that permits migration larger device necessary. VREF pins largest device anticipated must connected VREF voltage, used I/O. smaller devices, some VCCO pins used larger devices connect within package. These unconnected pins left unconnected externally, they connected VCCO voltage permit migration larger device, necessary.
IOBs, called banks. Consequently, restrictions exist about which standards combined within given bank. Eight banks result from separating each edge FPGA into banks, shown Figure Each bank multiple VCCO pins, which must connected same voltage. This voltage determined output standards use.
Bank Bank Bank Bank
ds022_03_121799
GCLK3 GCLK2
VirtexE Device
Bank GCLK1 GCLK0 Bank Bank Bank
Figure Virtex-E Banks Within bank, output standards mixed only they same VCCO. Compatible standards shown Table GTL+ appear under voltages because their open-drain outputs depend VCCO. Table VCCO Compatible Output Standards Compatible Standards PCI, LVTTL, SSTL3 SSTL3 CTT, AGP, GTL, GTL+, LVPECL SSTL2 SSTL2 LVCMOS2, GTL, GTL+, BLVDS, LVDS LVCMOS18, GTL, GTL+ HSTL HSTL III, HSTL GTL, GTL+
Configurable Logic Block
basic building block Virtex-E logic cell (LC). includes 4-input function generator, carry logic, storage element. output from function generator each drives both output input flip-flop. Each Virtex-E contains four LCs, organized similar slices, shown Figure Figure shows more detailed view single slice.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
COUT
COUT
Carry Control
Carry Control
Slice Carry Control
Carry Control
Slice
ds022_04_121799
Figure 2-Slice Virtex-E
COUT
INIT F5IN INIT
ds022_05_09200
Figure Detailed View Virtex-E Slice addition four basic LCs, Virtex-E contains logic that combines function generators provide functions five inputs. Consequently, when estimating number system gates provided given device, each counts LCs.
Look-Up Tables
Virtex-E function generators implemented 4-input look-up tables (LUTs). addition operating function generator, each provide 1-bit synchronous RAM. Furthermore, LUTs within slice com-
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DS025-2 (v2.3) November 2002
VirtexTM-E Extended Memory Field Programmable Gate Arrays
bined create 2-bit 1-bit synchronous RAM, 1-bit dual-port synchronous RAM. Virtex-E also provide 16-bit shift register that ideal capturing high-speed burst-mode data. This mode also used store data applications such Digital Signal Processing.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capability high-speed arithmetic functions. Virtex-E supports separate carry chains, Slice. height carry chains bits CLB. arithmetic logic includes gate that allows 2-bit full adder implemented within slice. addition, dedicated gate improves efficiency multiplier implementation. dedicated carry path also used cascade function generators implementing wide logic functions.
Storage Elements
storage elements Virtex-E slice configured either edge-triggered D-type flip-flops level-sensitive latches. inputs driven either function generators within slice directly from slice inputs, bypassing function generators. addition Clock Clock Enable signals, each Slice synchronous reset signals BY). forces storage element into initialization state specified configuration. forces into opposite state. Alternatively, these signals configured operate asynchronously. control signals independently invertible, shared flip-flops within slice.
BUFTs
Each Virtex-E contains 3-state drivers (BUFTs) that drive on-chip busses. "Dedicated Routing" page Each Virtex-E BUFT independent 3-state control independent input pin.
Block SelectRAM+ Memory
Virtex-E FPGAs incorporate large block SelectRAM memories. These complement Distributed SelectRAM memories that provide shallow structures implemented CLBs. Block SelectRAM memory blocks organized columns, starting left (column right outside edges inserted every four columns (see notes smaller devices). Each memory block four CLBs high, each memory column extends full height chip, immediately adjacent right, except column column locations indicated Table
Additional Logic
multiplexer each slice combines function generator outputs. This combination provides either function generator that implement 5-input function, multiplexer, selected functions nine inputs. Similarly, multiplexer combines outputs four function generators selecting F5-multiplexer outputs. This permits implementation 6-input function, multiplexer, selected functions inputs. Each four direct feedthrough paths, slice. These paths provide extra data input lines additional local routing that does consume logic resources. Table CLB/Block Column Locations
Virtex-E Device XCV405E XCV812E
Table shows amount block SelectRAM memory that available each Virtex-E device. Table Virtex-E Block SelectRAM Amounts Blocks Block SelectRAM Bits 573,440 1,146,88
Virtex-E Device XCV405E XCV812E
Each block SelectRAM cell, illustrated Figure fully synchronous dual-ported (True Dual Port) 4096-bit with independent control signals each port. data widths ports configured independently, providing built-in bus-width conversion.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays delay
RAMB4_S#_S#
RSTA CLKA ADDRA[#:0] DIA[#:0]
Adjacent
DOA[#:0]
Adjacent Adjacent
RSTB CLKB ADDRB[#:0] DIB[#:0]
DOB[#:0]
Adjacent Direct Connection Adjacent Direct Connection Adjacent
XCVE_ds_007
ds022_06_121699
Figure Dual-Port Block SelectRAM Table shows depth width aspect ratios block SelectRAM. Virtex-E block SelectRAM also includes dedicated routing provide efficient interface with both CLBs other block SelectRAM modules. Refer XAPP130 block SelectRAM timing waveforms. Table Width Block SelectRAM Port Aspect Ratios Depth 4096 2048 1024 ADDR ADDR<11:0> ADDR<10:0> ADDR<9:0> ADDR<8:0> ADDR<7:0> Data DATA<0> DATA<1:0> DATA<3:0> DATA<7:0> DATA<15:0>
Figure Virtex-E Local Routing
General Purpose Routing
Most Virtex-E signals routed general purpose routing, consequently, majority interconnect resources associated with this level routing hierarchy. general routing resources located horizontal vertical routing channels associated with rows columns. general-purpose routing resources listed below. Adjacent each General Routing Matrix (GRM). switch matrix through which horizontal vertical routing resources connect, also means which gains access general purpose routing. single-length lines route signals adjacent GRMs each four directions. buffered lines route signals another GRMs six-blocks away each four directions. Organized staggered pattern, lines driven only their endpoints. Hex-line signals accessed either endpoints midpoint (three blocks from source). third lines bidirectional, while remaining ones uni-directional. Longlines buffered, bidirectional wires that distribute signals across device quickly efficiently. Vertical Longlines span full height device, horizontal ones span full width device.
Programmable Routing Matrix
longest delay path that limits speed worst-case design. Consequently, Virtex-E routing architecture place-and-route software were defined joint optimization process. This joint optimization minimizes long-path delays, consequently, yields best system performance. joint optimization also reduces design compilation times because architecture software-friendly. Design cycles correspondingly reduced shorter design iteration times.
Local Routing
VersaBlock, shown Figure provides local routing resources with following types connections: Interconnections among LUTs, flip-flops, Internal feedback paths that provide high-speed connections LUTs within same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating
Routing
Virtex-E devices have additional routing resources around their periphery that form interface between array IOBs. This additional routing, called VersaRing, facilitates pin-swapping pin-locking, such that logic redesigns adapt existing layouts. Time-to-market reduced, since PCBs other system components manufactured while logic design still progress.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Dedicated Routing
Some signal classes require dedicated routing resources maximize performance. Virtex-E architecture, dedicated routing resources provided signal classes. Horizontal routing resources provided on-chip 3-state busses. Four partitionable lines provided row, permitting multiple busses within row, shown Figure dedicated nets propagate carry signals vertically adjacent CLB. Global Clock Distribution Network. Location
Tri-State Lines
buft_c.eps
Figure BUFT Connections Dedicated Horizontal LInes
Clock Routing
Clock Routing resources distribute clocks other signals with very high fanout throughout device. Virtex-E devices include tiers clock routing resources referred global local clock routing resources. global routing resources four dedicated global nets with dedicated input pins that designed distribute high-fanout clock signals with minimal skew. Each global clock drive CLB, IOB, block clock pins. global nets driven only global buffers. There four global buffers, each global net. local clock routing resources consist backbone lines, across chip across bottom. From these lines, unique signals column distributed longlines column. These local resources more flexible than global resources since they restricted routing only clock pins.
Global Clock Distribution
Virtex-E provides high-speed, low-skew clock distribution through global routing resources described above. typical clock distribution shown Figure
GCLKPAD3 GCLKBUF3 Global Clock Rows GCLKPAD2 GCLKBUF2 Global Clock Column
Four global buffers provided, center device bottom center. These drive four global nets that turn drive clock pin. Four dedicated clock pads provided, adjacent each global buffers. input global buffer selected either from these pads from signals general purpose routing.
Digital Delay-Locked Loops
There eight DLLs (Delay-Locked Loops) device, with four located four bottom, Figure DLLs used eliminate skew between clock input internal clock input pins throughout device. Each drive global clock networks.The monitors input clock distributed clock, automatically adjusts clock delay element. Additional delay introduced such that clock edges arrive internal flip-flops synchronized with clock edges arriving input. addition eliminating clock-distribution delay, provides advanced control multiple clock domains.
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Global Clock Spine
GCLKBUF1 GCLKPAD1
GCLKBUF0 GCLKPADXCVE_009
Figure Global Clock Distribution Network
DS025-2 (v2.3) November 2002
VirtexTM-E Extended Memory Field Programmable Gate Arrays provides four quadrature phases source clock, double clock divide clock 1.5, 2.5, also operates clock mirror. driving output from off-chip then back again, used de-skew board level clock among multiple devices. order guarantee that system clock operating correctly prior FPGA starting after configuration, delay completion configuration process until after achieved lock. more information about functionality, Design Consideration section data sheet.
DLLDLL
DLLDLL
XCVE_001
DLLDLL
DLLDLL
Secondary DLLs
Secondary DLLs
Primary DLLs
Figure Locations
Boundary Scan
Virtex-E devices support mandatory boundary-scan instructions specified IEEE standard 1149.1. Test Access Port (TAP) registers provided that implement EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, HIGHZ instructions. also supports internal scan chains configuration/readback device. JTAG input pins (TDI, TMS, TCK) have VCCO requirement, operate with either input signalling levels. output (TDO) sourced from VCCO bank proper operation LVTTL levels, bank should supplied with Boundary-scan operation independent individual configurations, unaffected package type. IOBs, including un-bonded ones, treated independent 3-state bidirectional pins single scan chain. Retention bidirectional test capability after configuration facilitates testing external interconnections, provided user design application turned off. Table lists boundary-scan instructions supported Virtex-E FPGAs. Internal signals captured during EXTEST connecting them un-bonded unused IOBs. They also connected unused outputs IOBs defined unidirectional input pins. Before device configured, instructions except USER1 USER2 available. After configuration, instructions available. During configuration, recommended that those operations using boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) performed. addition test instructions outlined above, boundary-scan circuitry used configure FPGA, also read back configuration data.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Figure diagram Virtex-E Series boundary scan logic. includes three bits Data Register IOB, IEEE 1149.1 Test Access Port controller, Instruction Register with decodes.
DATA IOB.T
IOB.I
IOB.Q IOB.T
BYPASS REGISTER INSTRUCTION REGISTE
IOB.I
DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTE
UPDATE
EXTEST
X9016
Figure Virtex-E Family Boundary Scan Logic
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VirtexTM-E Extended Memory Field Programmable Gate Arrays Table Boundary Scan Instructions Binary Code (4:0) 00000 00001 Description Enable boundary-scan EXTEST operation. Enable boundary-scan SAMPLE/PRELOAD operation. Access user-defined register Access user-defined register Access configuration read operations. Access configuration write operations. Enable boundary-scan INTEST operation. Enable shifting USER code. Enable shifting Code. 3-state output pins while enabling Bypass Register. Clock start-up sequence when StartupClk TCK. Enable BYPASS. Xilinx reserved instructions.
Boundary-Scan Command EXTEST SAMPLE/ PRELOAD USER1 USER2 CFG_OUT
Each EXTEST CAPTURED-OR state captures Out, 3-state pins. other standard data register single flip-flop BYPASS register. synchronizes data being passed through FPGA next downstream boundary scan device. FPGA supports additional internal scan chains that specified using BSCAN macro. macro provides user pins (SEL1 SEL2) which decodes USER1 USER2 instructions respectively. these instructions, corresponding pins TDO2) allow user scan data shifted TDO. Likewise, there individual clock pins (DRCK1 DRCK2) each user register. There common input (TDI) shared output pins that represent state controller (RESET, SHIFT, UPDATE).
00010 00011 0010
CFG_IN
00101
Sequence
order within each Out, 3-State. input-only pins contribute only boundary scan data register, while output-only pins contributes three bits. From cavity-up view chip shown EPIC), starting upper right chip corner, boundary scan data-register bits ordered shown Figure BSDL (Boundary Scan Description Language) files Virtex-E Series devices available Xilinx site File Download area.
INTEST USERCODE IDCODE HIGHZ
00111 01000 01001 0101
JSTART
0110
end)
Right half top-edge IOBs (Right Left) GCLK2 GCLK3 Left half top-edge IOBs (Right Left) Left-edge IOBs (Top Bottom) Left half bottom-edge IOBs (Left Right) GCLK1 GCLK0 Right half bottom-edge IOBs (Left Right) DONE PROG Right-edge IOBs (Bottom Top)
BYPASS RESERVED
11111 other codes
Instruction
Virtex-E Series boundary scan instruction also includes instructions configure device read back configuration data (CFG_IN, CFG_OUT, JSTART). complete instruction coded shown Table
(TDI end)
CCLK
990602001
Data Registers
primary data register boundary scan register. each FPGA, bonded not, includes three bits Out, 3-State Control. Non-IOB pins have appropriate partial population input-only output-only.
Figure Boundary Scan Sequence
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DS025-2 (v2.3) November 2002
VirtexTM-E Extended Memory Field Programmable Gate Arrays Table IDCODEs Assigned Virtex-E FPGAs FPGA XCV405EM XCV812EM IDCODE v0C28093h v0C38093h
Identification Registers
IDCODE register supported. using IDCODE, device connected JTAG port determined. IDCODE register following binary format: where version number family code Virtex-E family) number rows (ranges from XCV50E XCV3200E) company code (49h Xilinx) USERCODE register supported. using USERCODE, user-programmable identification code loaded shifted examination. identification code (see Table embedded bitstream during bitstream generation valid only after configuration.
Note: Attempting load incorrect bitstream causes configuration fail damage device.
Including Boundary Scan Design
Since boundary scan pins dedicated, special element needs added design unless internal data register (USER1 USER2) desired. internal data register used, insert boundary scan symbol connect necessary pins appropriate.
Development System
Virtex-E FPGAs supported Xilinx Foundation Alliance Series tools. basic methodology Virtex-E design consists three interrelated steps: design entry, implementation, verification. Industry-standard tools used design entry simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools implementation. Xilinx development system integrated under Xilinx Design Manager (XDMTM) software, providing designers with common user interface regardless their choice entry verification tools. software simplifies selection implementation options with pull-down menus on-line help. Application programs ranging from schematic capture Placement Routing (PAR) accessed through software. program command sequence generated prior execution, stored documentation. Several advanced software features facilitate Virtex-E design. RPMs, example, schematic-based macros with relative location constraints guide their placement. They help ensure optimal implementation common functions. design entry, Xilinx FPGA Foundation development system provides interfaces following synthesis design environments. Synopsys (FPGA Compiler, FPGA Express) Exemplar (Spectrum) Synplicity (Synplify) standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into development system. Virtex-E FPGAs supported unified library standard functions. This library contains over primitives macros, ranging from 2-input gates 16-bit accumulators, includes arithmetic functions, comparators, counters, data registers, decoders, encoders, functions, latches, Boolean functions, multiplexers, shift registers, barrel shifters. "soft macro" portion library contains detailed descriptions common logic functions, does contain partitioning placement information. performance these macros depends, therefore, partitioning placement obtained during implementation. RPMs, other hand, contain predetermined partitioning placement information that permits optimal implementation these functions. Users create their library soft macros RPMs based macros primitives standard library. design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define logic these blocks. These hierarchical design elements automatically combined implementation tools. Different design entry tools combined within hierarchical design, thus allowing most convenient entry method used each portion design.
schematic design entry, Xilinx FPGA Foundation Alliance development system provides interfaces following schematic-capture design environments. Mentor Graphics (Design Architect, QuickSim Viewlogic Systems (Viewdraw)
Design Implementation
place-and-route tools (PAR) automatically provide implementation flow described this section. partitioner takes EDIF list design maps logic into architectural resources FPGA (CLBs IOBs, example). placer then determines best locations these blocks based their interconnecModule
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VirtexTM-E Extended Memory Field Programmable Gate Arrays tions desired performance. Finally, router interconnects blocks. algorithms support fully automatic implementation most designs. demanding applications, however, user exercise various degrees control over process. User partitioning, placement, routing information optionally specified during design-entry process. implementation highly structured designs benefit greatly from basic floor planning. implementation software incorporates Timing Wizard® timing-driven placement routing. Designers specify timing requirements along entire paths during design entry. timing path analysis routines then recognize these user-specified requirements accommodate them. Timing requirements entered schematic form directly relating system requirements, such targeted clock frequency, maximum allowable delay between registers. this way, overall performance system along entire signal paths automatically tailored user-generated specifications. Specific timing information individual nets unnecessary.
Design Verification
addition conventional software simulation, FPGA users in-circuit debugging techniques. Because Xilinx devices infinitely reprogrammable, designs verified real time without need extensive sets software simulation vectors. development system supports both software simulation in-circuit debugging techniques. simulation, system extracts post-layout timing information from design database, back-annotates this information into list simulator. Alternatively, user verify timing-critical portions design using TRCE® static timing analyzer. in-circuit debugging, optional download readback cable available. This cable connects FPGA target system workstation. After downloading design into FPGA, designer single-step logic, readback contents flip-flops, observe internal logic state. Simple modifications downloaded into system matter minutes.
Configuration
Virtex-E devices configured loading configuration data into internal configuration memory. Note that attempting load incorrect bitstream causes configuration fail damage device. Some pins used configuration dedicated pins, while others re-used general purpose inputs outputs once configuration complete. following dedicated pins: Mode pins (M2, Configuration clock (CCLK) PROGRAM DONE Boundary-scan pins (TDI, TDO, TMS, TCK) Depending configuration mode chosen, CCLK output generated FPGA, generated externally provided FPGA input. PROGRAM must pulled High prior reconfiguration. Note that some configuration pins outputs. correct operation, these pins require VCCO permit LVTTL operation. pins affected banks Table Configuration Codes CCLK Direction Data Width Serial Dout Configuration Pull-ups Configuration Mode Master-serial mode Boundary-scan mode SelectMAP mode Slave-serial mode Master-serial mode configuration pins needed SelectMap (CS, Write) located bank
Configuration Modes
Virtex-E supports following four configuration modes. Slave-serial mode Master-serial mode SelectMAP mode Boundary-scan mode (JTAG) Configuration mode pins (M2, select among these configuration modes with option each case having pins either pulled left floating prior configuration. selection codes listed Table Configuration through boundary-scan port always available, independent mode selection. Selecting boundary-scan mode simply turns other modes. three mode pins have internal pull-up resistors, default logic High left unconnected. However, recommended drive configuration mode pins externally.
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Table
Configuration Codes CCLK Direction Data Width Serial Dout Configuration Pull-ups
Configuration Mode Boundary-scan mode SelectMAP mode Slave-serial mode
Table lists total number bits required configure each device. Table Virtex-E Bitstream Lengths Configuration Bits 3,430,400 6,519,648
ured, data next device routed DOUT pin. Data DOUT changes rising edge CCLK. change DOUT rising edge CCLK differs from previous families does cause problem mixed configuration chains. This change made improve serial configuration rates Virtex Virtex-E only chains. Figure shows full master/slave system. Virtex-E device slave-serial mode should connected shown right-most device. Slave-serial mode selected applying <111> <011> mode pins (M2, M0). weak pull-up mode pins makes slave-serial default mode pins left unconnected. However, recommended drive configuration mode pins externally. Figure shows slave-serial mode programming switching characteristics. Table provides more detail about characteristics shown Figure Configuration must delayed until INIT pins daisy-chained FPGAs High.
Device XCV405E XCV812E
Slave-Serial Mode
slave-serial mode, FPGA receives configuration data bit-serial form from serial PROM other source serial configuration data. serial bitstream must input short time before each rising edge externally generated CCLK. more detailed information serial PROMs PROM data sheet Multiple FPGAs daisy-chained configuration from single source. After particular FPGA been configTable
Master/Slave Serial Mode Programming Switching Description Figure References
Symbol
TDCC/TCCD TDSCK/TCKDS TCCO TCCH TCCL
Values
5.0/0.0 5.0/0.0 12.0 +45% -30%
Units
MHz,
setup/hold, slave mode setup/hold, master mode DOUT
CCLK
High time time Maximum Frequency Frequency Tolerance, master mode with respect nominal
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3.3V DOUT VIRTEX-E MASTER SERIAL CCLK PROGRAM DONE INIT
CCLK
DOUT
XC1701L DATA RESET/OE (Low Reset Option Used)
VIRTEX-E, XC4000XL, SLAVE PROGRAM DONE
INIT
PROGRAM
XCVE_ds_013
Figure Master/Slave Serial Mode Circuit Diagram
TDCC CCLK TCCH TCCO DOUT (Output)
X5379_a
TCCD
TCCL
Figure Slave-Serial Mode Programming Switching Characteristics
Master-Serial Mode
master-serial mode, CCLK output FPGA drives Xilinx Serial PROM that feeds bit-serial data input. FPGA accepts this data each rising CCLK edge. After FPGA been loaded, data next device daisy-chain presented DOUT after rising CCLK edge. interface identical slave-serial except that internal oscillator used generate configuration clock (CCLK). wide range frequencies selected CCLK which always starts slow default frequency. Configuration bits then switch CCLK higher frequency remainder configuration. Switching lower frequency prohibited. CCLK frequency using ConfigRate option bitstream generation software. maximum CCLK frequency that selected MHz. When selecting CCLK frequency, ensure that serial PROM daisy-chained FPGAs fast enough support clock rate. power-up, CCLK frequency approximately MHz. This frequency used until ConfigRate bits have been loaded when frequency changes selected ConfigRate. Unless different frequency specified design, default ConfigRate MHz. Figure shows full master/slave system. this system, left-most device operates master-serial mode. remaining devices operate slave-serial mode. SPROM RESET driven INIT, input driven DONE. There potential contention DONE pin, depending start-up sequence options chosen.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays Figure shows timing master-serial configuration. Master-serial mode selected <000> <100> mode pins (M2, M0). Table shows timing information Figure
sequence operations necessary configure Virtex-E FPGA serially appears Figure
Apply Power FPGA starts clear configuration memory. PROGRAM High FPGA makes final clearing pass releases INIT when finished.
Release INIT
used delay configuration
INIT?
High
Load Configuration Once bitstream, FPGA checks data using pulls INIT error.
Bitstream?
errors found, FPGA enters start-up phase causing DONE High.
Configuration Completed
ds009_15_111799
Figure Serial Configuration Flowchart
CCLK (Output) TCKDS TDSCK Serial Data
Serial DOUT (Output)
DS022_44_071201
Figure Master-Serial Mode Programming Switching Characteristics power-up, must rise from less than otherwise delay configuration pulling PROGRAM until valid. retention selected, PROHIBIT constraints required prevent SelectMAP-port pins from being used user I/O. Multiple Virtex-E FPGAs configured using SelectMAP mode, made start-up simultaneously. configure multiple devices this way, wire individual CCLK, Data, WRITE, BUSY pins devices parallel. individual devices loaded separately asserting each device turn writing appropriate data. Table SelectMAP Write Timing Characteristics.
SelectMAP Mode
SelectMAP mode fastest configuration option. Byte-wide data written into FPGA with BUSY flag controlling flow data. external data source provides byte stream, CCLK, Chip Select (CS) signal Write signal (WRITE). BUSY asserted (High) FPGA, data must held until BUSY goes Low. Data also read using SelectMAP mode. WRITE asserted, configuration data read FPGA part readback operation. After configuration, pins SelectMAP port used additional user I/O. Alternatively, port retained permit high-speed 8-bit readback. Retention SelectMAP port selectable design-by-design basis when bitstream generated.
Write
Write operations send packets configuration data into FPGA. sequence operations multi-cycle write operation shown below. Note that configuration packet split into many such sequences. packet does have complete within assertion illustrated Figure Assert WRITE Low. Note that when asserted successive CCLKs, WRITE must remain
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VirtexTM-E Extended Memory Field Programmable Gate Arrays either asserted de-asserted. Otherwise abort initiated, described below. Drive data onto D[7:0]. Note that avoid contention, data source should enabled while WRITE High. Similarly, while WRITE High, more that should asserted.
rising edge CCLK: BUSY Low, data accepted this clock. BUSY High (from previous write), data accepted. Acceptance instead occurs first clock after BUSY goes Low, data must held until this happened. Repeat steps until data been sent. De-assert WRITE.
Table
SelectMAP Write Timing Characteristics Description D0-7 Setup/Hold Setup/Hold WRITE Setup/Hold Symbol TSMDCC/TSMCCD TSMCSCC/TSMCCCS TSMCCW/TSMWCC TSMCKBY FCCNH Values 12.0 Units MHz, MHz,
CCLK BUSY Propagation Delay Maximum Frequency Maximum Frequency with handshake
CCLK
WRITE
DATA[0:7]
BUSY
Write
Write
Write
Write
DS022_45_071702
Figure Write Operations flowchart write operation appears Figure Note that CCLK slower than fCCNH, FPGA never asserts BUSY, this case, above handshake unnecessary, data simply entered into FPGA every CCLK cycle. Abort During given assertion user cannot switch from write read, vice-versa. This action causes current packet command aborted. device remains BUSY until aborted operation completed. Following abort, data assumed unaligned word boundaries, FPGA requires synchronization word prior accepting packets. initiate abort during write operation, de-assert WRITE. rising edge CCLK, abort initiated, shown Figure
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Apply Power FPGA starts clear configuration memory.
PROGRAM from High
FPGA makes final clearing pass releases INIT when finished.
Release INIT used delay configuration
INIT?
High WRITE
Enter Data Source Sequence
first FPGA
Apply Configuration Byte Once bitstream, FPGA checks data using pulls INIT error.
Busy?
High
Data? errors, first FPGAs enter start-up phase releasing DONE. High
first FPGA
errors, later FPGAs enter start-up phase releasing DONE.
Repeat Sequence
other FPGAs
Disable Data Source
WRITE High When DONE pins released, DONE goes High start-up sequences complete.
Configuration Completed
ds003_17_090602
Figure SelectMAP Flowchart Write Operations
CCLK
WRITE
DATA[0:7]
BUSY
Abort
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Figure SelectMAP Write Abort Waveforms
Boundary-Scan Mode
boundary-scan mode, configuration done through IEEE 1149.1 Test Access Port. Note that
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PROGRAM must pulled High prior reconfiguration. PROGRAM resets controller JTAG operations performed.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays Configuration through uses CFG_IN instruction. This instruction allows data input converted into data packets internal configuration bus. following steps required configure FPGA through boundary-scan port (when using start-up clock). Load CFG_IN instruction into boundary-scan instruction register (IR) Enter Shift-DR (SDR) state Shift configuration bitstream into Return Run-Test-Idle (RTI) Load JSTART instruction into Enter state Clock through startup sequence Return Configuration readback always available. boundary-scan mode selected <101> <001>
mode pins (M2, M0). details characteristics, refer XAPP139.
Configuration Sequence
configuration Virtex-E devices three-phase process. First, configuration memory cleared. Next, configuration data loaded into memory, finally, logic activated start-up process. Configuration automatically initiated power-up unless delayed user, described below. configuration process also initiated asserting PROGRAM. memory-clearing phase signalled INIT going High, completion entire process signalled DONE going High. power-up timing configuration signals shown Figure
PROGRAM
INIT TICCK CCLK OUTPUT INPUT
(Required)
VALI
ds022_020_071201
Figure Power-Up Timing Configuration Signals corresponding timing characteristics listed Table Table Power-up Timing Characteristics Symbol TPOR TICCK TPROGRAM Value 100.0 CCLK (output) Delay Program Pulse Width Units
Delaying Configuration
INIT held using open-drain driver. open-drain required since INIT bidirectional open-drain that held FPGA while configuration memory being cleared. Extending time that causes configuration sequencer wait. Thus, configuration delayed preventing entry into phase where data loaded.
Description Power-on Reset1 Program Latency
Start-Up Sequence
default Start-up sequence that CCLK cycle after DONE goes High, global 3-state signal (GTS) released. This permits device outputs turn necessary. CCLK cycle later, Global Set/Reset (GSR) Global Write Enable (GWE) signals released. This permits
Notes: TPOR delay initialization time required after VCCINT reaches recommended operating voltage.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays dent DONE pins multiple devices going High, forcing devices start synchronously. sequence also paused stage until lock been achieved DLLs.
internal storage elements begin changing state response logic user clock. relative timing these events changed. addition, GTS, GSR, events made depen-
Readback
configuration data stored Virtex-E configuration memory readback verification. Along with configuration data possible readback contents flip-flops/latches, RAMs, block RAMs. This capability used real-time debugging. more detailed information, application note XAPP138 "Virtex FPGA Series Configuration Readback".
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Design Considerations
This section contains more detailed design information following features. Delay-Locked Loop page BlockRAM page SelectI/O page order guarantee system clock establishes prior device "waking up," delay completion device configuration process until after achieves lock. taking advantage remove on-chip clock delay, designer greatly simplify improve system level design involving high-fanout, high-performance clocks.
Using DLLs
Virtex-E FPGA series provides eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits which provide zero propagation delay, clock skew between output clock signals distributed throughout device, advanced clock domain control. These dedicated DLLs used implement several circuits which improve simplify system level design.
Library Symbols
Figure shows simplified Xilinx library macro symbol, BUFGDLL. This macro delivers quick efficient provide system clock with zero propagation delay throughout device. Figure Figure show library primitives. These symbols provide access complete features when implementing more complex applications.
Introduction
FPGAs grow size, quality on-chip clock distribution becomes increasingly important. Clock skew clock delay impact device performance task managing clock skew clock delay with conventional clock trees becomes more difficult large devices. Virtex-E series devices resolve this potential problem providing eight fully digital dedicated on-chip circuits which provide zero propagation delay clock skew between output clock signals distributed throughout device. Each drive global clock routing networks within device. global clock distribution network minimizes clock skews loading differences. monitoring sample output clock, compensate delay routing network, effectively eliminating delay from external input port individual clock loads within device. addition providing zero delay with respect user source clock, provide multiple phases source clock. also clock doubler divide user source clock Clock multiplication gives designer number design alternatives. instance, source clock doubled drive FPGA design operating MHz. This technique simplify board design because clock path board longer distributes such high-speed signal. multiplied clock also provides designers option time-domain-multiplexing, using circuit twice clock cycle, consuming less area than copies same circuit. DLLs connected series increase effective clock multiplication factor four. also clock mirror. driving output off-chip then back again, used de-skew board level clock between multiple devices.
ds022_25_121099
Figure Simplified Macro Symbol BUFGDLL
CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK27
CLK2X CLKDV LOCKED
ds022_26_121099
Figure Standard Symbol CLKDLL
CLKDLLHF
CLKIN CLKFB CLK0 CLK18
CLKDV LOCKED
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Figure High Frequency Symbol
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VirtexTM-E Extended Memory Field Programmable Gate Arrays DLLs. This makes total eight usable input pins DLLs Virtex-E family.
BUFGDLL Descriptions
BUFGDLL macro simplest provide zero propagation delay high-fanout on-chip clock from external input. This macro uses IBUFG, CLKDLL BUFG primitives implement most basic application shown Figure
IBUFG CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK27
Feedback Clock Input CLKFB
requires reference feedback signal provide delay-compensated output. Connect only CLK0 CLK2X outputs feedback clock input (CLKFB) provide necessary feedback DLL. feedback clock input also provided through following pins. IBUFG Global Clock Input IO_LVDS_DLL adjacent IBUFG IBUFG sources CLKFB pin, following special rules apply.
BUFG
CLK2X CLKDV LOCKED
ds022_28_121099
Figure BUFGDLL Schematic This symbol does provide access advanced clock domain controls clock multiplication clock division features DLL. This symbol also does provide access RST, LOCKED pins DLL. access these features, designer must library primitives described following sections.
external input port must source signal that drives IBUFG pin. CLK2X output must feedback device both CLK0 CLK2X outputs driving chip devices. That signal must directly drive only OBUFs nothing else.
Source Clock Input
provides user source clock, clock signal which operates, BUFGDLL. BUFGDLL macro source clock frequency must fall frequency range specified data sheet. BUFGDLL requires external signal source clock. Therefore, only external input port source signal that drives BUFGDLL pin.
These rules enable software determine which clock output sources CLKFB pin.
Reset Input
When reset activates LOCKED signal deactivates within four source clock cycles. pin, active High, must either connect dynamic signal tied ground. delay taps reset zero, glitches occur clock output pins. Activation also severely affect duty cycle clock output pins. Furthermore, output clocks longer de-skew with respect another. these reasons, rarely reset unless re-configuring device changing input frequency.
Clock Output
clock output represents delay-compensated version source clock signal. This signal, sourced global clock buffer BUFG symbol, takes advantage dedicated global clock routing resources device. output clock 50-50 duty cycle unless deactivate duty cycle correction property.
Clock Output CLK2X
output CLK2X provides frequency-doubled clock with automatic 50/50 duty-cycle correction. Until CLKDLL achieved lock, CLK2X output appears version input clock with 25/75 duty cycle. This behavior allows lock correct edge with respect source clock. This available CLKDLLHF primitive.
CLKDLL Primitive Descriptions
library CLKDLL primitives provide access complete features needed when implementing more complex applications with DLL.
Source Clock Input CLKIN
CLKIN provides user source clock (the clock signal which operates) DLL. CLKIN frequency must fall ranges specified data sheet. global clock buffer (BUFG) driven from another CLKDLL, global clock input buffers (IBUFG), IO_LVDS_DLL same edge device (top bottom) must source this clock signal. There four IO_LVDS_DLL input pins that used inputs
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Clock Divide Output CLKDV
clock divide output CLKDV provides lower frequency version source clock. CLKDV_DIVIDE property controls CLKDV such that source clock divided where either 1.5, 2.5, This feature provides automatic duty cycle correction such that CLKDV output always 50/50 duty cycle, with exception noninteger divides mode, where duty cycle N=1.5 N=2.5.
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Clock Outputs CLK[0|90|180|270]
clock output CLK0 represents delay-compensated version source clock (CLKIN) signal. CLKDLL primitive provides three phase-shifted versions CLK0 signal while CLKDLLHF provides only phase-shifted version. relationship between phase shift corresponding period shift appears Table Table Relationship Phase-Shifted Output Clock Period Shift Period Shift (percent)
clock outputs drive OBUF, BUFG, they route directly destination clock pins. clock outputs only drive BUFGs that reside same edge (top bottom).
Locked Output LOCKED
achieve lock, might need sample several thousand clock cycles. After achieves lock, LOCKED signal activates. timing parameter section data sheet provides estimates locking times. guarantee that system clock established prior device "waking up," delay completion device configuration process until after locks. STARTUP_WAIT property activates this feature. Until LOCKED signal activates, output clocks valid exhibit glitches, spikes, other spurious movement. particular CLK2X output appears clock with 25/75 duty cycle.
Phase (degrees)
timing diagrams Figure illustrate clock output characteristics.
Properties
Properties provide access some Virtex-E series features, (for example, clock division duty cycle correction).
CLKIN CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 CLK90 CLK180 CLK270 DUTY_CYCLE_CORRECTION=TRUE CLK0 CLK90 CLK180 CLK27ds022_29_121099
Duty Cycle Correction Property
clock outputs, CLK0, CLK90, CLK180, CLK270, duty-cycle corrected default, exhibiting 50/50 duty cycle. DUTY_CYCLE_CORRECTION property default TRUE) controls this feature. deactivate duty-cycle correction clock outputs, attach DUTY_CYCLE_CORRECTION=FALSE property symbol.
Clock Divide Property
CLKDV_DIVIDE property specifies signal CLKDV frequency divided with respect CLK0 pin. values allowed this property 1.5, 2.5, default value
Startup Delay Property
This property, STARTUP_WAIT, takes value TRUE FALSE (the default value). When TRUE device configuration DONE signal waits until locks before going High.
Virtex-E Location Constraints
shown Figure there four additional DLLs Virtex-E devices, total eight Virtex-E device. These DLLs located silicon, bottom innermost block SelectRAM columns. location constraint LOC, attached symbol with identifier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S, DLL3P, controls location. property uses following form: DLL0P
Figure Output Characteristics provides duty cycle correction clock outputs such that clock outputs default have 50/50 duty cycle. DUTY_CYCLE_CORRECTION property (TRUE default), controls this feature. order deactivate duty cycle correction, attach DUTY_CYCLE_CORRECTION=FALSE property symbol. When duty cycle correction deactivates, output clock same duty cycle source clock.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays similar manner, phase shift input clock also possible. phase shift propagates four clocks output after original shift, with disruption CLKDLL control.
DLL-3S
DLL-3P
DLL-2P
DLL-2S
Output Clocks
mentioned earlier descriptions, some restrictions apply regarding connectivity output pins. clock outputs drive OBUF, global clock buffer BUFG, they route directly destination clock pins. only BUFGs that clock outputs drive same edge device (top bottom). addition, CLK2X output secondary connect directly CLKIN primary same quadrant. output clock signals until after activation LOCKED signal. Prior activation LOCKED signal, output clocks valid exhibit glitches, spikes, other spurious movement.
DLL-1S
DLL-1P
DLL-0P
DLL-0S
Bottom Right Half Edge
x132_14_100799
Figure Virtex Series DLLs
Design Factors
following design considerations avoid pitfalls improve success designing with Xilinx devices.
Input Clock
output clock signal DLL, essentially delayed version input clock signal, reflects instability input clock output waveform. this reason quality input clock relates directly quality output clock waveforms generated DLL. input clock requirements specified data sheet. most systems crystal oscillator generates system clock. used with commercially available quartz crystal oscillator. example, most crystal oscillators produce output waveform with frequency tolerance PPM, meaning 0.01 percent change clock period. operates reliably input waveform with frequency drift orders magnitude excess that needed support crystal oscillator industry. However, cycle-to-cycle jitter must kept less than frequencies high frequencies.
Useful Application Examples
Virtex-E used variety creative useful applications. following examples show some more common applications. Verilog VHDL example files available
Standard Usage
circuit shown Figure resembles BUFGDLL macro implemented provide access LOCKED pins CLKDLL.
IBUFG CLKIN CLKFB
CLKDLL
CLK0 CLK90 CLK180 CLK27
BUFG
Input Clock Changes
Changing period input clock beyond maximum drift amount requires manual reset CLKDLL. Failure reset produces unreliable lock signal output clock. possible stop input clock with little impact DLL. Stopping clock should limited less than keep device cooling minimum. clock should stopped during phase, when restored full High period should seen. During this time LOCKED stays High remains High when clock restored. When clock stopped, four more clocks still observed delay line flushed. When clock restarted, output clocks observed four clocks delay line filled. most common case three clocks.
IBUF
CLK2X CLKDV OBUF LOCKED
ds022_028_121099
Figure Standard Implementation
Board Level De-Skew Multiple Non-Virtex-E Devices
circuit shown Figure used de-skew system clock between Virtex-E chip other non-Virtex-E chips same board. This application commonly used when Virtex-E device used conjunction with other standard products such SRAM DRAM devices. While designing board level route, ensure that return delay source equals delay other chips involved.
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Virtex-E Device IBUFG CLKIN CLKFB IBUFG CLKDLL CLK0 CLK90 CLK180 CLK270 OBUF
Because single access only BUFGs most, additional output clock signals must routed from this example high speed backbone routing. dll_2x files xapp132.zip file show VHDL Verilog implementation this circuit.
CLK2X CLKDV LOCKED
Virtex-E Clock
DLLs located same half-edge (top-left, top-right, bottom-right, bottom-left) connected together, without using BUFG between CLKDLLs, generate clock shown Figure Virtex-E devices, like Virtex devices, have four clock networks that available internal de-skewing clock. Each eight DLLs have access four clock networks. Although DLLs used internal de-skewing, presence GCLKBUFs bottom indicate that only four DLLs (and four DLLs bottom) used this purpose.
IBUFG
CLKDLL CLKIN CLKFB CLK0 CLK90 CLK180 CLK27
BUFG
CLK2X CLKDV LOCKED
Non-Virtex-E Chip Non-Virtex-E Chip
CLKDLL-S CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X
Other Non_Virtex-E Chips
ds022_029_121099
Figure De-skew Board Level Clock Board-level de-skew required low-fanout clock networks. recommended systems that have fanout limitations clock network, clock distribution chip cannot handle load. output clock signals until after activation LOCKED signal. Prior activation LOCKED signal, output clocks valid exhibit glitches, spikes, other spurious movement. dll_mirror_1 files xapp132.zip file show VHDL Verilog implementation this circuit.
CLKDV LOCKED
CLKDLL-P CLKIN CLKFB CLK0 CLK90 CLK180 CLK27BUFG
CLK2X CLKDV LOCKED
OBUF
ds022_031_041901
De-Skew Clock Multiple
circuit shown Figure implements clock multiplier also uses CLK0 clock output with zero skew between registers same chip. clock divider circuit could alternatively implemented using similar connections.
IBUFG CLKIN CLKFB
Figure Generation Clock Virtex-E Devices dll_4xe files xapp 32.zip file show implementation Verilog Virtex-E devices. These files found
CLKDLL
CLK0 CLK90 CLK180 CLK27
BUFG
Using Block SelectRAM+ Features
BUFG OBUF
CLK2X IBUF CLKDV LOCKED
ds022_030_121099
Figure De-skew Clock Multiple
Virtex FPGA Series provides dedicated blocks on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port block SelectRAM+ memory independently configured read/write port, read port, write port, configured specific data width. block SelectRAM+ memory offers capabilities, allowing FPGA designers simplify designs.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Operating Modes
Virtex-E block SelectRAM+ memory supports operating modes. Read Through Write Back
RAMB4_S#_S#
RSTA CLKA ADDRA[#:0] DIA[#:0]
DOA[#:0]
Read Through (one clock edge)
read address registered read port clock edge data appears output after access time. Some memories might place latch/register outputs, depending desire have faster clock-to-out versus set-up time. This generally considered inferior solution, since changes read operation asynchronous function with possibility missing address/control line transition during generation read pulse clock.
RSTB CLKB ADDRB[#:0] DIB[#:0] DOB[#:0]
ds022_032_121399
Figure Dual-Port Block SelectRAM+ Memory
Write Back (one clock edge)
write address registered write port clock edge data input written memory mirrored output.
RAMB4_S#
ADDR[#:0] DI[#:0]
ds022_033_121399
DO[#:0]
Block SelectRAM+ Characteristics
inputs registered with port clock have set-up clock timing specification. outputs have read through write back function depending state port pin. outputs relative port clock available after clock-to-out timing specification. block SelectRAM elements true SRAM memories have combinatorial path from address output. SelectRAM+ cells CLBs still available with this function. ports completely independent from each other (i.e., clocking, control, address, read/write function, data width) without arbitration. write operation requires only clock edge. read operation requires only clock edge. output ports latched with self-timed circuit guarantee glitch-free read. state output port does change until port executes another read write operation.
Figure Single-Port Block SelectRAM+ Memory Table Available Library Primitives Port Width Port Width
Primitive RAMB4_S1 RAMB4_S1_S1 RAMB4_S1_S2 RAMB4_S1_S4 RAMB4_S1_S8 RAMB4_S1_S16 RAMB4_S2 RAMB4_S2_S2 RAMB4_S2_S4 RAMB4_S2_S8 RAMB4_S2_S16 RAMB4_S4 RAMB4_S4_S4 RAMB4_S4_S8 RAMB4_S4_S16 RAMB4_S8 RAMB4_S8_S8 RAMB4_S8_S16 RAMB4_S16 RAMB4_S16_S16
Library Primitives
Figure Figure show generic library block SelectRAM+ primitives. Table describes available primitives synthesis simulation.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Port Signals
Each block SelectRAM+ port operates independently others while accessing same 4096 memory cells. Table describes depth width aspect ratios block SelectRAM+ memory. Table Width Block SelectRAM+ Port Aspect Ratios Depth 4096 2048 1024 ADDR ADDR<11:0> ADDR<10:0> ADDR<9:0> ADDR<8:0> ADDR<7:0> Data DATA<0> DATA<1:0> DATA<3:0> DATA<7:0> DATA<15:0>
Data Output Bus-DO[A|B]<#:0>
data reflects contents memory cells referenced address last active clock edge. During write operation, data reflects data bus. width this equals width port. allowed widths appear Table
Inverting Control Pins
four control pins (CLK, RST) each port have independent inversion control configuration option.
Address Mapping
Each port accesses same 4096 memory cells using addressing scheme dependent width port. physical location addressed particular width described following formula interest only when ports different aspect ratios). Start ((ADDRport Widthport) ADDRport Widthport Table shows order address mapping each port width. Table Port Width
4095. 2047. 1023. 511. 255.
Clock-CLK[A|B]
Each port fully synchronous with independent clock pins. port input pins have setup time referenced port pin. data output clock-to-out time referenced pin.
Enable-EN[A|B]
enable affects read, write reset functionality port. Ports with inactive enable keep output pins previous state write data memory cells. Port Address Mapping Port Addresses
0Write Enable-WE[A|B]
Activating write enable allows port write memory cells. When active, contents data input written address pointed address bus, data also reflects data bus. When inactive, read operation occurs contents memory cells referenced address reflect data bus.
Creating Larger Structures
block SelectRAM+ columns have specialized routing allow cascading blocks together with minimal routing delays. This achieves wider deeper structures with smaller timing penalty than when using normal routing channels.
Reset-RST[A|B]
reset forces data output latches zero synchronously. This does affect memory cells does disturb write operation other port.
Address Bus-ADDR[A|B]<#:0>
address selects memory cells read write. width port determines required width this shown Table
Location Constraints
Block SelectRAM+ instances have properties attached them constrain placement. block SelectRAM+ placement locations separate from location naming convention, allowing properties transfer easily from array array. properties following form. RAMB4_R#C# RAMB4_R0C0 upper left RAMB4 location device.
Data Bus-DI[A|B]<#:0>
data provides data value written into RAM. This port have same width, shown Table
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
Conflict Resolution
block SelectRAM+ memory true dual-read/write port that allows simultaneous access same memory cell from both ports. When port writes given memory cell, other port must address that memory cell (for write read) within clock-to-clock setup window. following lists specifics port memory cell write conflict resolution. both ports write same memory cell simultaneously, violating clock-to-clock setup requirement, consider data stored invalid. port attempts read same memory cell other simultaneously writes, violating clock-to-clock setup requirement, following occurs. write succeeds data writing port accurately reflects data written. data reading port invalid. indicating read operation. contains contents memory location 0x7E indicated ADDR bus. fourth rising edge pin, ADDR, pins sampled again. indicating that block SelectRAM+ memory disabled. retains last value.
Dual Port Timing
Figure shows timing diagram true dual-port read/write block SelectRAM+ memory. clock port longer period than clock Port timing parameter TBCCS, (clock-to-clock set-up) shown this diagram. parameter, TBCCS violated once diagram. other timing parameters identical single port version shown Figure TBCCS only importance when address both ports same least port performing write operation. When clock-to-clock set-up parameter violated WRITE-WRITE condition, contents memory that location invalid. When clock-to-clock set-up parameter violated WRITE-READ condition, contents memory correct, read port invalid data. first rising edge CLKA, memory location 0x00 written with value 0xAAAA mirrored bus. last operation Port read same memory location 0x00. Port does change with value Port retains last read value. short time later, Port executes another read memory location 0x00, reflects memory value written Port second rising edge CLKA, memory location 0x7E written with value 0x9999 mirrored bus. Port then executes read operation same memory location without violating TBCCS parameter reflects memory values written Port
Conflicts cause physical damage.
Single Port Timing
Figure shows timing diagram single port block SelectRAM+ memory. block SelectRAM+ switching characteristics specified data sheet. block SelectRAM+ memory initially disabled. first rising edge pin, ADDR, pins sampled. High indicating read operation. contains contents memory location, 0x00, indicated ADDR bus. second rising edge pin, ADDR, pins sampled again. pins High indicating write operation. mirrors bus. written memory location 0x0F. third rising edge pin, ADDR, pins sampled again. High
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TBPWH
TBPWL
TBACK
ADDR DOUT
TBDCK DDDD TBCKO (00) TBECK
CCCC CCCC
BBBB (7E)
2222
TBWCK
DISABLED READ WRITE READ DISABLED
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Figure Timing Diagram Single Port Block SelectRAM+ Memory
TBCCS VIOLATION
CLK_A ADDR_A PORT EN_A WE_A DI_A DO_A
AAAA 9999 AAAA 0000 1111
TBCCS TBCCS
AAAA
9999
AAAA
UNKNOWN
2222
CLK_B ADDR_B EN_B WE_B DI_B DO_B
1111 1111 1111 BBBB 1111 2222 FFFF
PORT
(00)
AAAA
9999
BBBB
UNKNOWN
2222
FFFF
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Figure Timing Diagram True Dual-port Read/Write Block SelectRAM+ Memory third rising edge CLKA, TBCCS parameter violated with writes memory location 0x0F. busses reflect contents busses, stored value 0x0F invalid. fourth rising edge CLKA, read operation performed memory location 0x0F invalid data present bus. Port also executes read operation memory location 0x0F also reads invalid data. fifth rising edge CLKA read operation performed that does violate TBCCS parameter previous write 0x7E Port reflects recently written value Port
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Initialization
block SelectRAM+ memory initialize during device configuration sequence. initialization properties values each total 4096 bits) initialization each RAM. These properties appear Table initialization properties explicitly configure zeros. Partial initialization strings with zeros. Initialization strings greater than values generate error. RAMs simulated with initialization values using generics VHDL simulators parameters Verilog simulators.
Design Examples
Creating 32-bit Single-Port
true dual-read/write port functionality block SelectRAM+ memory allows single port, deep 32-bit wide created using single block SelectRAM+ cell shown inTable Interleaving memory space, setting address Port (VCC), address Port (GND), allows 32-bit wide single port created.
RAMB4_S16_S16
ADDR[6:0], DI[31:16] RSTA CLKA ADDRA[7:0] DIA[15:0]
Initialization VHDL Synopsys
block SelectRAM+ structures initialized VHDL both simulation synthesis inclusion EDIF output file. simulation VHDL code uses generic pass initialization. Synopsys FPGA compiler does presently support generics. initialization values instead attach attributes built-in Synopsys dc_script. translate_off statement stops synthesis translation generic statements. following code illustrates module that employs these techniques. Table Initialization Properties Property INIT_00 INIT_01 INIT_02 INIT_03 INIT_04 INIT_05 INIT_06 INIT_07 INIT_08 INIT_09 INIT_0a INIT_0b INIT_0c INIT_0d INIT_0e INIT_0f Memory Cells 1023 1279 1024 1535 1280 1791 2047 2047 1792 2303 2048 2559 2304 2815 2560 3071 2816 3327 3072 3583 3328 3839 3584 4095
DOA[15:0]
DO[31:16]
ADDR[6:0], DI[15:0]
RSTB CLKB ADDRB[7:0] DIB[15:0]
DOB[15:0]
DO[15:0]
ds022_036_121399
Figure Single Port
Creating Single-Port RAMs
true dual-read/write port functionality block SelectRAM+ memory allows single split into single port memories bits each shown Figure
RAMB4_S4_S16
RST1 CLK1 ADDR1[8:0] DI1[3:0] RSTA CLKA ADDRA[9:0] DIA[3:0]
DOA[3:0]
DO1[3:0]
RST2 CLK2 GND, ADDR2[6:0] DI2[15:0]
RSTB CLKB ADDRB[7:0] DIB[15:0]
DOB[15:0]
DO2[15:0]
ds022_037_121399
Figure this example, 512K (Port (Port created single block SelectRAM+. address space split fixing Port (VCC) upper bits Port (GND) lower bits.
Initialization Verilog Synopsys
block SelectRAM+ structures initialized Verilog both simulation synthesis inclusion EDIF output file. simulation Verilog code uses defparam pass initialization. Synopsys FPGA compiler does presently support defparam. initialization values instead attach attributes built-in Synopsys dc_script. translate_off statement stops synthesis translation defparam statements. following code illustrates module that employs these techniques.
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Block Memory Generation
CoreGen program generates memory structures using block SelectRAM+ features. This program outputs VHDL Verilog simulation code templates EDIF file inclusion design.
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VHDL Initialization Example
library IEEE; IEEE.std_logic_1164.all; entity MYMEM port (CLK, WE:in std_logic; ADDR: std_logic_vector(8 downto DIN: std_logic_vector(7 downto DOUT: std_logic_vector(7 downto 0)); MYMEM; architecture BEHAVE MYMEM signal logic0, logic1: std_logic; component RAMB4_S8 -synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f BIT_VECTOR(255 downto -synopsys translate_on port (WE, RST, CLK: STD_LOGIC; ADDR: STD_LOGIC_VECTOR(8 downto STD_LOGIC_VECTOR(7 downto STD_LOGIC_VECTOR(7 downto 0)); component; -synopsys dc_script_begin -set_attribute ram0 INIT_00 -type string -set_attribute ram0 INIT_01 -type string -synopsys dc_script_end begin logic0 <='0'; logic1 <='1'; ram0: RAMB4_S8 -synopsys translate_off generic INIT_00 INIT_01 -synopsys translate_on port (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); BEHAVE;
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Verilog Initialization Example
module MYMEM (CLK, ADDR, DIN, DOUT); input CLK, input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 -type string //set_attribute ram0 INIT_01 -type string //synopsys dc_script_end assign logic0 1'b0; assign logic1 1'b1; RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN), .DO(DOUT)); //synopsys translate_off defparam ram0.INIT_00 defparam ram0.INIT_01 //synopsys translate_on endmodule
Using SelectI/O
Virtex-E FPGA series includes highly configurable, high-performance resource, called SelectI/Oto provide support wide variety standards. SelectI/O resource robust features including programmable control output drive strength, slew rate, input delay hold time. Taking advantage flexibility SelectI/O features design considerations described this document improve simplify system level design. with high performance previously available only with ASICs custom ICs. Each SelectI/O block support standards. Supporting such variety standards allows support wide variety applications, from general purpose standard applications high-speed low-voltage memory busses. SelectI/O blocks also provide selectable output drive strengths programmable slew rates LVTTL output buffers, well optional, programmable weak pull-up, weak pull-down, weak "keeper" circuit ideal external bussing applications. Each input/output block (IOB) includes three registers, each input, output, 3-state signals within IOB. These registers optionally configurable either D-type flip-flop level sensitive latch. input buffer optional delay element used guarantee zero hold time requirement input signals registered within IOB. Virtex-E SelectI/O features also provide dedicated resources input reference voltage (VREF) output source voltage (VCCO), along with convenient banking system that simplifies board design. taking advantage built-in features wide variety standards supported SelectI/O features, system-level design board design greatly simplified improved.
Module
Introduction
FPGAs continue grow size capacity, larger more complex systems designed them demand increased variety standards. Furthermore, system clock speeds continue increase, need high performance becomes more important. While chip-to-chip delays have increasingly substantial impact overall system speed, task achieving desired system performance becomes more difficult with proliferation low-voltage standards. SelectI/O, revolutionary input/output resource Virtex-E devices, resolved this potential problem providing highly configurable, high-performance alternative resources more conventional programmable devices. Virtex-E SelectI/O features combine flexibility time-to-market advantages programmable logic
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Fundamentals
Modern applications, pioneered largest most influential companies digital electronics industry, commonly introduced with standard tailored specifically needs that application. standards provide specifications other vendors create products designed interface with these applications. Each standard often specifications current, voltage, buffering, termination techniques. ability provide flexibility time-to-market advantages programmable logic increasingly dependent capability programmable logic device support ever increasing variety standards SelectI/O resources feature highly configurable input output buffers which provide support wide variety standards. shown Table each buffer type support variety voltage requirements. Table Standard LVTTL LVCMOS2 LVCMOS18 SSTL3 SSTL2 GTL+ HSTL HSTL AGP-2X PCI33_3 PCI66_3 BLVDS LVDS LVPECL Virtex-E Supported Standards Output VCCO Input VCCO Input VREF 1.50 1.25 0.80 0.75 0.90 1.50 1.32 Board Termination Voltage (VTT) 1.50 1.25 1.20 1.50 0.75 1.50 1.50
Overview Supported Standards
This section provides brief overview standards supported Virtex-E devices. While most standards specify range allowed voltages, this document records typical voltage values only. Detailed information each specification found Electronic Industry Alliance Jedec website http://www.jedec.org
LVTTL Low-Voltage
Low-Voltage TTL, LVTTL standard general purpose EIA/JESDSA standard applications that uses LVTTL input buffer Push-Pull output buffer. This standard requires output source voltage (VCCO), does require reference voltage (VREF) termination voltage (VTT).
LVCMOS2 Low-Voltage CMOS Volts
Low-Voltage CMOS Volts lower, LVCMOS2 standard extension LVCMOS standard (JESD 8.-5) used general purpose applications. This standard requires output source voltage (VCCO), does require reference voltage (VREF) board termination voltage (VTT).
LVCMOS18 Voltage CMOS
This standard extension LVCMOS standard. used general purpose applications. reference voltage (VREF) board termination voltage (VTT) required.
Peripheral Component Interface
Peripheral Component Interface, standard specifies support both applications. uses LVTTL input buffer Push-Pull output buffer. This standard does require reference voltage (VREF) board termination voltage (VTT), however, does require output source voltage (VCCO).
Gunning Transceiver Logic Terminated
Gunning Transceiver Logic, standard high-speed standard (JESD8.3) invented Xerox. Xilinx implemented terminated variation this standard. This standard requires differential amplifier input buffer Open Drain output buffer.
GTL+ Gunning Transceiver Logic Plus
Gunning Transceiver Logic Plus, GTL+ standard high-speed standard (JESD8.3) first used Pentium processor.
HSTL High-Speed Transceiver Logic
High-Speed Transceiver Logic, HSTL standard general purpose high-speed, standard sponsored (EIA/JESD 8-6). This standard four variations classes. SelectI/O devices support Class III, This
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VirtexTM-E Extended Memory Field Programmable Gate Arrays
standard requires Differential Amplifier input buffer Push-Pull output buffer.
Library Symbols
Xilinx library includes extensive list symbols designed provide support variety SelectI/O features. Most these symbols represent variations five generic SelectI/O symbols. IBUF (input buffer) IBUFG (global clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer)
SSTL3 Stub Series Terminated Logic 3.3V
Stub Series Terminated Logic SSTL3 standard general purpose memory standard also sponsored Hitachi (JESD8-8). This standard classes, SelectI/O devices support both classes SSTL3 standard. This standard requires Differential Amplifier input buffer Push-Pull output buffer.
SSTL2 Stub Series Terminated Logic 2.5V
Stub Series Terminated Logic SSTL2 standard general purpose memory standard sponsored Hitachi (JESD8-9). This standard classes, SelectI/O devices support both classes SSTL2 standard. This standard requires Differential Amplifier input buffer Push-Pull output buffer.
IBUF
Signals used inputs Virtex-E device must source input buffer (IBUF) external input port. generic Virtex-E IBUF symbol appears Figure extension base name defines which standard IBUF uses. assumed standard LVTTL when generic IBUF specified extension.
Center Terminated
Center Terminated, standard memory standard sponsored Fujitsu (JESD8-4). This standard requires Differential Amplifier input buffer Push-Pull output buffer.
IBUF
x133_01_111699
AGP-2X Advanced Graphics Port
Intel standard Advanced Graphics Port-2X standard used with Pentium processor graphics applications. This standard requires Push-Pull output buffer Differential Amplifier input buffer.
Figure Input Buffer (IBUF) Symbols following list details variations IBUF symbol: IBUF IBUF_LVCMOS2 IBUF_PCI33_3 IBUF_PCI66_3 IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_III IBUF_HSTL_IV IBUF_SSTL3_I IBUF_SSTL3_II IBUF_SSTL2_I IBUF_SSTL2_II IBUF_CTT IBUF_AGP IBUF_LVCMOS18 IBUF_LVDS IBUF_LVPECL
LVDS Voltage Differential Signal
LVDS differential standard. requires that data carried through signal lines. with differential signaling standards, LVDS inherent noise immunity over single-ended standards. voltage swing between signal lines approximately reference voltage (VREF) board termination voltage (VTT) required. LVDS requires pins input output. LVDS requires external resistor termination.
BLVDS LVDS
This standard allows bidirectional LVDS communication between more devices. external resistor termination different than standard LVDS.
LVPECL Voltage Positive Emitter Coupled Logic
LVPECL another differential standard. requires signal lines transmitting data bit. This standard specifies pins input output. voltage swing between these signal lines approximately reference voltage (VREF) board termination voltage (VTT) required. LVPECL standard requires external resistor termination.
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When IBUF symbol supports standard that requires VREF, IBUF automatically configures differential amplifier input buffer. VREF voltage must supplied VREF pins. case LVDS, LVPECL, BLVDS, VREF required.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays voltage reference signal "banked" within Virtex-E device half-edge basis such that packages there eight independent VREF banks internally. Figure representation Virtex-E banks. Within each bank approximately every pins automatically configured VREF input. After placing differential amplifier input signal within given VREF bank, same external source must drive pins configured VREF input. IBUF placement restrictions require that differential amplifier input signals within bank same standard. specify specific location IBUF property described below. Table summarizes Virtex-E input standards compatibility requirements. optional delay element associated with each IBUF. When IBUF drives flip-flop within IOB, delay element default activates ensure zero hold-time requirement. NODELAY=TRUE property overrides this default. When IBUF does drive flip-flop within IOB, delay element de-activates default provide higher performance. delay input signal, activate delay element with DELAY=TRUE property.
CLKDLLHF, BUFG symbol. generic Virtex-E IBUFG symbol appears Figure
IBUFG
x133_03_111699
Figure Virtex-E Global Clock Input Buffer (IBUFG) Symbol extension base name determines which standard used IBUFG. With extension specified generic IBUFG symbol, assumed standard LVTTL. following list details variations IBUFG symbol. IBUFG IBUFG_LVCMOS2 IBUFG_PCI33_3 IBUFG_PCI66_3 IBUFG_GTL IBUFG_GTLP IBUFG_HSTL_I IBUFG_HSTL_III IBUFG_HSTL_IV IBUFG_SSTL3_I IBUFG_SSTL3_II IBUFG_SSTL2_I IBUFG_SSTL2_II IBUFG_CTT IBUFG_AGP IBUFG_LVCMOS18 IBUFG_LVDS IBUFG_LVPECL
Bank Bank GCLK3
Bank GCLK2 Bank Bank
Virtex-E Device
Bank
GCLK1 Bank
GCLK0 Bank
ds022_42_01210
Figure Virtex-E Banks
Table Rule
Xilinx Input Standards Compatibility Requirements Standards with same input VCCO, output VCCO, VREF placed within same bank.
When IBUFG symbol supports standard that requires differential amplifier input, IBUFG automatically configures differential amplifier input buffer. low-voltage standards with differential amplifier input require external reference voltage input VREF. voltage reference signal "banked" within Virtex-E device half-edge basis such that packages there eight independent VREF banks internally. Figure representation Virtex-E banks. Within each bank approximately every pins automatically configured VREF input. After placing differential amplifier input signal within given VREF bank, same external source must drive pins configured VREF input. IBUFG placement restrictions require differential amplifier input signals within bank same standard. property specify location IBUFG.
IBUFG
Signals used high fanout clock inputs Virtex-E device should drive global clock input buffer (IBUFG) external input port order take advantage four dedicated global clock distribution networks. output IBUFG should only drive CLKDLL,
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VirtexTM-E Extended Memory Field Programmable Gate Arrays OBUF_F_24 OBUF_LVCMOS2 OBUF_PCI33_3 OBUF_PCI66_3 OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_III OBUF_HSTL_IV OBUF_SSTL3_I OBUF_SSTL3_II OBUF_SSTL2_I OBUF_SSTL2_II OBUF_CTT OBUF_AGP OBUF_LVCMOS18 OBUF_LVDS OBUF_LVPECL
added convenience, BUFGP used instantiate high fanout clock input. BUFGP symbol represents combination LVTTL IBUFG BUFG symbols, such that output BUFGP connect directly clock pins throughout design. Unlike previous architectures, Virtex-E BUFGP symbol only placed global clock location. property specify location BUFGP.
OBUF
OBUF must drive outputs through external output port. generic output buffer (OBUF) symbol appears Figure
OBUF
x133_04_111699
Figure Virtex-E Output Buffer (OBUF) Symbol extension base name defines which standard OBUF uses. With extension specified generic OBUF symbol, assumed standard slew rate limited LVTTL with drive strength. LVTTL OBUF additionally support slew rate modes minimize transients. default, slew rate each output buffer reduced minimize power transients when switching non-critical signals. LVTTL output buffers have selectable drive strengths. format LVTTL OBUF symbol names follows. <slew_rate> either (Fast), (Slow) <drive_strength> specified milliamps 24). following list details variations OBUF symbol. OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 OBUF_F_16
Virtex-E series supports eight banks packages. packages support four VCCO banks. OBUF placement restrictions require that within given VCCO bank each OBUF share same output source drive voltage. Input buffers type output buffers that require VCCO placed within VCCO bank. Table summarizes Virtex-E output compatibility requirements. property specify location OBUF. Table Rule Rule VCCO Output Standards Compatibility Requirements Only outputs with standards that share compatible VCCO used within same bank. There placement restrictions outputs with standards that require VCCO. Compatible Standards LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL, GTL+, PCI33_3, PCI66_3 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+ HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
OBUFT
generic 3-state output buffer OBUFT, shown Figure typically implements 3-state outputs bidirectional I/O. extension base name defines which standard OBUFT uses. With extension specified generic OBUFT symbol, assumed standard slew rate limited LVTTL with drive strength.
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VirtexTM-E Extended Memory Field Programmable Gate Arrays LVTTL OBUFT additionally support slew rate modes minimize transients. default, slew rate each output buffer reduced minimize power transients when switching non-critical signals. LVTTL 3-state output buffers have selectable drive strengths. format LVTTL OBUFT symbol names follows. <slew_rate> either (Fast), (Slow) <drive_strength> specified milliamps 24).
Virtex-E series supports eight banks packages. package supports four VCCO banks. SelectI/O OBUFT placement restrictions require that within given VCCO bank each OBUFT share same output source drive voltage. Input buffers type output buffers that require VCCO placed within same VCCO bank. property specify location OBUFT. 3-state output buffers bidirectional buffers have either weak pull-up resistor, weak pull-down resistor, weak "keeper" circuit. Control this feature adding appropriate symbol output OBUFT (PULLUP, PULLDOWN, KEEPER). weak "keeper" circuit requires input buffer within sample signal. OBUFTs programmed standard that requires VREF have automatic placement VREF bank with OBUFT configured with weak "keeper" circuit. This restriction does affect most circuit design applications using OBUFT configured with weak "keeper" typically implement bidirectional I/O. this case IBUF (and corresponding VREF) explicitly placed. property specify location OBUFT.
OBUFT
x133_05_111699
Figure 3-State Output Buffer Symbol (OBUFT) following list details variations OBUFT symbol. OBUFT OBUFT_S_2 OBUFT_S_4 OBUFT_S_6 OBUFT_S_8 OBUFT_S_12 OBUFT_S_16 OBUFT_S_24 OBUFT_F_2 OBUFT_F_4 OBUFT_F_6 OBUFT_F_8 OBUFT_F_12 OBUFT_F_16 OBUFT_F_24 OBUFT_LVCMOS2 OBUFT_PCI33_3 OBUFT_PCI66_3 OBUFT_GTL OBUFT_GTLP OBUFT_HSTL_I OBUFT_HSTL_III OBUFT_HSTL_IV OBUFT_SSTL3_I OBUFT_SSTL3_II OBUFT_SSTL2_I OBUFT_SSTL2_II OBUFT_CTT OBUFT_AGP OBUFT_LVCMOS18 OBUFT_LVDS OBUFT_LVPECL
Module
IOBUF
IOBUF symbol bidirectional signals that require both input buffer 3-state output buffer with active high 3-state pin. generic input/output buffer IOBUF appears Figure extension base name defines which standard IOBUF uses. With extension specified generic IOBUF symbol, assumed standard LVTTL input buffer slew rate limited LVTTL with drive strength output buffer. LVTTL IOBUF additionally support slew rate modes minimize transients. default, slew rate each output buffer reduced minimize power transients when switching non-critical signals. LVTTL bidirectional buffers have selectable output drive strengths. format LVTTL IOBUF symbol names follows. <slew_rate> either (Fast), (Slow) <drive_strength> specified milliamps 24).
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DS025-2 (v2.3) November 2002
VirtexTM-E Extended Memory Field Programmable Gate Arrays voltage reference signal "banked" within Virtex-E device half-edge basis such that packages there eight independent VREF banks internally. Figure page representation Virtex-E banks. Within each bank approximately every pins automatically configured VREF input. After placing differential amplifier input signal within given VREF bank, same external source must drive pins configured VREF input. IOBUF placement restrictions require differential amplifier input signals within bank same standard. Virtex-E series supports eight banks packages. package supports four VCCO banks. Additional restrictions Virtex-E SelectI/O IOBUF placement require that within given VCCO bank each IOBUF must share same output source drive voltage. Input buffers type output buffers that require VCCO placed within same VCCO bank. property specify location IOBUF. optional delay element associated with input path each IOBUF. When IOBUF drives input flip-flop within IOB, delay element activates default ensure zero hold-time requirement. Override this default with NODELAY=TRUE property. case when IOBUF does drive input flip-flop within IOB, delay element de-activates default provide higher performance. delay input signal, activate delay element with DELAY=TRUE property. 3-state output buffers bidirectional buffers have either weak pull-up resistor, weak pull-down resistor, weak "keeper" circuit. Control this feature adding appropriate symbol output IOBUF (PULLUP, PULLDOWN, KEEPER).
IOBUF
x133_06_111699
Figure Input/Output Buffer Symbol (IOBUF) following list details variations IOBUF symbol. IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 IOBUF_F_8 IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_LVCMOS2 IOBUF_PCI33_3 IOBUF_PCI66_3 IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_SSTL3_I IOBUF_SSTL3_II IOBUF_SSTL2_I IOBUF_SSTL2_II IOBUF_CTT IOBUF_AGP IOBUF_LVCMOS18 IOBUF_LVDS IOBUF_LVPECL
SelectI/O Properties
Access some SelectI/O features (for example, location constraints, input delay, output drive strength, slew rate) available through properties associated with these features.
Input Delay Properties
optional delay element associated with each IBUF. When IBUF drives flip-flop within IOB, delay element activates default ensure zero hold-time requirement. NODELAY=TRUE property override this default. case when IBUF does drive flip-flop within IOB, delay element default de-activates provide higher performance. delay input signal, activate delay element with DELAY=TRUE property.
When IOBUF symbol used supports standard that requires differential amplifier input, IOBUF automatically configures with differential amplifier input buffer. low-voltage standards with differential amplifier input require external reference voltage input VREF.
DS025-2 (v2.3) November 2002
www.xilinx.com 1-800-255-7778
Module
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Flip-Flop/Latch Property
Virtex-E series block (IOB) includes optional register input path, optional register output path, optional register 3-state control pin. design implementation software automatically takes advantage these registers when following option program specified. <filename> Alternatively, TRUE property placed register force mapper place register IOB.
Design Considerations
Reference Voltage (VREF) Pins
Low-voltage standards with differential amplifier input buffer require input reference voltage (VREF). Provide VREF external signal device. voltage reference signal "banked" within device half-edge basis such that packages there eight independent VREF banks internally. Figure representation Virtex-E banks. Within each bank approximately every pins automatically configured VREF input. After placing differential amplifier input signal within given VREF bank, same external source must drive pins configured VREF input. Within each VREF bank, input buffers that require VREF signal must same type. Output buffers type input buffers placed without requiring reference voltage within same VREF bank.
Location Constraints
Specify location each SelectI/O symbol with location constraint attached SelectI/O symbol. external port identifier indicates value location constrain. format port identifier depends package chosen specific design. properties following form. LOC=A42 LOC=P37
Output Drive Source Voltage (VCCO) Pins
Many voltage standards supported SelectI/O devices require different output drive source voltage (VCCO). result each device often have support multiple output drive source voltages. Virtex-E series supports eight banks packages. package supports four VCCO banks. Output buffers within given VCCO bank must share same output drive source voltage. Input buffers LVTTL, LVCMOS2, LVCMOS18, PCI33_3, 66_3 VCCO voltage Input VCCO voltage.
Output Slew Rate Property
mentioned above, variety symbol names provide option choosing desired slew rate output buffers. case LVTTL output buffers (OBUF, OBUFT, IOBUF), slew rate control alternatively programed with SLEW= property. default, slew rate each output buffer reduced minimize power transients when switching non-critical signals. SLEW= property following values. SLEW=SLOW SLEW=FAST
Transmission Line Effects
delay electrical signal along wire dominated rise fall times when signal travels short distance. Transmission line delays vary with inductance capacitance, well-designed board experience delays approximately inch. Transmission line effects, reflections, typically start 1.5" fast (1.5 rise fall times. Poor non-existent) termination changes transmission line impedance cause these reflections cause additional delay longer traces. system speeds continue increase, effect delays become limiting factor therefore transmission line termination becomes increasingly more important.
Output Drive Strength Property
desired output drive strength additionally specified choosing appropriate library symbol. Xilinx library also provides alternative method specifying this feature. LVTTL output buffers (OBUF, OBUFT, IOBUF, desired drive strength specified with DRIVE= property. This property could have following seven values. DRIVE=2 DRIVE=4 DRIVE=6 DRIVE=8 DRIVE=12 (Default) DRIVE=16 DRIVE=24
Termination Techniques
variety termination techniques reduce impact transmission line effects. following output termination techniques: None Series Parallel (Shunt) Series Parallel (Series-Shunt)
DS025-2 (v2.3) November 2002
Module
www.xilinx.com 1-800-255-7778
VirtexTM-E Extended Memory Field Programmable Gate Arrays
Input termination techniques include following: None Parallel (Shunt) Table Guidelines Maximum Number Simultaneously Switching Outputs Power/Ground Pair Package Standard LVTTL Slow Slew Rate, drive LVTTL Slow Slew Rate, drive
Z=50 VREF
These termination techniques applied combination. generic example each combination termination methods appears Figure
Unterminated
BGA,
Double Parallel Terminated
LVTTL Slow Slew Rate, drive
Unterminated Output Driving Parallel Terminated Input
Series Terminated Output Driving Parallel Terminated Input
LVTTL Slow Slew Rate, drive LVTTL Slow Slew Rate, drive LVTTL Slow Slew Rate, drive
Z=50 VREF
Z=50 VREF
Series-Parallel Terminated Output Driving Parallel Terminated Input Series Terminated Output
Z=50 Z=50 VREF VREF
x133_07_111699
LVTTL Slow Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVTTL Fast Slew Rate, drive LVCMOS GTL+ HSTL Class HSTL Class HSTL Class SSTL2 Class SSTL2 Class SSTL3 Class SSTL3 Class
Figure Overview Standard Input Output Termination Methods
Simultaneous Switching Guidelines
Ground bounce occur with high-speed digital when multiple outputs change states simultaneously, causing undesired transient behavior output, internal logic. This problem also referred Simultaneous Switching Output (SSO) problem. Ground bounce primarily current changes combined inductance ground pins, bond wires, ground metallization. internal ground level deviates from external system ground level short duration nanoseconds) after multiple outputs change state simultaneously. Ground bounce affects stable outputs inputs because they interpret incoming signal comparing internal ground. ground bounce amplitude exceeds actual instantaneous noise margin, then non-changing input interpreted short pulse with polarity opposite ground bounce. Table provides guidelines maximum number simultaneously switching outputs allowed output power/ground pair avoid effects ground bounce. Refer Table number effective output power/ground pairs each Virtex-E device package combination.
Note: This analysis assumes load each output.
Table
Virtex-E Extended Memory Family Equivalent Power/Ground Pairs Pkg/Part BG560 FG676 FG900 XCV405E XCV812E
DS025-2 (v2.3) November 2002
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