March 1994 DS3886A 9-Bit Latching Data Transceiver MIL-STD-883

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

March 1994 DS3886A 9-Bit Latching Data Transceiver MIL-STD-883

Datasheet Thumbnail

Top Searches for this datasheet

DS3886A 9-Bit Latching Data Transceiver MIL-STD-883
March 1994
DS3886A 9-Bit Latching Data Transceiver MIL-STD-883
General Description
DS3886A higher speed lower power compatible version DS3886 DS3886A series transceivers designed specifically implementation high performance Futurebus proprietary interfaces DS3886A 9-Bit Latching Data Transceiver designed conform IEEE 1194 (Backplane Transceiver Logic BTL) DS3886A incorporates edge-triggered latch driver path which bypassed during fall-through mode operation transparent latch receiver path Utilization DS3886A simplifies implementation byte wide address data with parity lines also used Futurebus status command lines DS3886A driver output configuration open collector which allows Wired-OR connection Each driver output incorporates Schottky diode series with it's collector isolate transistor output capacitance from thus reducing loading inactive state combined output capacitance driver output receiver input less than driver also high sink current capability comply with loading requirements defined within IEEE 1194 specification (Continued)
Features
Fast propagation delay 9-BIT Latched Transceiver Driver incorporates edge triggered latches Receiver incorporates transparent latches Meets IEEE 1194 Standard Backplane Transceiver Logic (BTL) Supports Live Insertion Glitch free Power-up down protection Typically less than Bus-port capacitance Bus-port voltage swing (typically Open collector Bus-port outputs allows Wired-OR connection Controlled rise fall time reduce noise coupling adjacent lines compatible Driver Control inputs Built Bandgap reference with separate QVCC QGND pins precise receiver thresholds Individual Bus-port ground pins Product offered glass sealed CERPAK package style Tight skew
Connection Diagrams
11974
Order Number DS3886AW Package Number WA48A
TRI-STATE registered trademark National Semiconductor Corporation C1995 National Semiconductor Corporation
11974
RRD-B30M105 Printed
Logic Diagram
11974
Absolute Maximum Ratings (Notes
specifications written reflect Reliability Electrical Test Specifications (RETS) established National Semiconductor this product copy latest RETS please contact your local National Semiconductor sales office distributor Supply Voltage Control Input Voltage Driver Input Receiver Output Receiver Input Current Termination Voltage Power Dissipation Units Storage Temperature Range Lead Temperature (Soldering
Recommended Operating Conditions
Supply Voltage (VCC) Termination Voltage (VT) Operating Free Temperature Units
Electrical Characteristics (Notes
Symbol Parameter Conditions DRIVER CONTROL INPUT ACLK RBYP) Minimum Input High Voltage Maximum Input Voltage Input Leakage Current Input High Current Input Current Input Current Input Diode Clamp Voltage Port RBYp ICLAMP
DRIVER OUTPUT RECEIVER INPUT (Bn) VOLB IOLB IOHB IOLBZ IOHBZ VCLP Output Voltage (Note Output Current Output High Current Output Current Disabled Output High Current Disabled Receiver Input Threshold Positive Clamp Voltage VCLN Negative Clamp Voltage ICLAMP
Electrical Characteristics (Notes
Symbol Parameter Conditions RECEIVER OUTPUT (An) Voltage Output High Voltage Output b2mA TRI-STATE Leakage Current
(Continued) Units
Output Short Circuit Current
(Note
SUPPLY CURRENT ICCT ICCT Power Supply Current High Input (VIN Supply Current QVCC Live Insertion Current ACLK RBYP ACLK RBYP ACLK RBYB ACLK
Note ``Absolute maximum ratings'' those beyond which safety device cannot guaranteed They meant imply that device should operated these limits table ``Electrical Characteristics'' provides conditions actual device operation Note input output pins shall exceed plus shall exceed absolute maximum rating anytime including power-up power down This prevents structure from being damaged excessive currents flowing from input output pins QVCC There diode between each input output which forward biased when incorrect sequencing applied Alternatively current limiting resistor used when pulling-up inputs prevent damage current into input output shall greater than Exception pins have power sequencing requirements with respect QVCC Furthermore difference between QVCC should never greater than time including power-up Note currents into device pins positive currents device pins negative voltages referenced device ground unless otherwise specified typical values specified under these conditions unless otherwise stated Note Only output should shorted time duration short should exceed second Note Referenced appropriate signal ground exceed maximum power dissipation package
Electrical Characteristics
Symbol DRIVER tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tskew Fall-through mode ACLK Latch mode Enable Time Disable Time Enable Time Disable Time Transition Time-Rise Fall Slew Rate calculated from ACLK Same Package Same Package Propagation Delay Propagation Delay Parameter
(Note Units
Conditions
RBYP (Figures RBYP (Figures (Figures (Figures RBYP (Figures RBYP RBYP (Figures (Note RBYP (Figures (Note (Note (Note
Electrical Characteristics
Symbol Parameter DRIVER TIMING REQUIREMENTS (Figure RECEIVER tPHL tPLH tPHL tPLH tPLZ tPZL tPHZ tPZH tPLZ tPZL tPHZ tPZH tskew Bypass Mode Latch Mode Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Disable Time Enable Time Same Package Same Package Propagation Delay Propagation Delay ACLK ACLK ACLK Pulse Width Set-up Time Hold Time
(Note (Continued) Units
Conditions
RBYP RBYP RBYP
(Figures (Figures (Figures (Figures (Figures (Figures (Note (Note
RECEIVER TIMING REQUIREMENTS (Figure Pulse Width Set-up Time Hold Time
PARAMETERS TESTED Coutput Capacitance Noise Rejection (Note (Note
Note Input waveforms shall have rise fall time Note tskew absolute value defined differences seen propagation delay between drivers same package with identical load conditions Note parameter tested using techniques described P1194 Backplane Design Guide Note This parameter tested during device characterization measurements revealed that part will typically reject pulse width Note Futurebus transceivers required limit signal rise fall times faster than measured between (approximately nominal voltage swing) rise fall times measured with transceiver loading equivalent tied
Description
Name ACLK B0GND B8GND QGND QVCC RBYP Number Pins Input Output Description TRI-STATE receiver output driver input Clock input latch receiver input driver output Driver output ground reduces ground bounce high current switching driver outputs (Note Chip Disable Ground reference switching circuits (Note Latch Enable Power supply live insertion Boards that require live insertion should connect live insertion connector (Note Connect Ground reference receiver input bandgap reference non-switching circuits (Note supply bandgap reference non-switching circuits (Note Register bypass enable Transmit Receive Transmit Receive
supply switching circuits (Note
Note multiplicity grounds reduces effective inductance bonding wires leads which then reduces noise caused transients ground path various ground pins tied together provided that external ground iductance ground plane with power pins many signal pins connected backplane ground) external ground floats considerably during transients precautionary steps should taken prevent QGND from moving with reference backplane ground receiver threshold should have same ground reference signal coming from backplane voltage offset between their grounds will degrade noise margin Note same considerations ground used reducing lead inductance (see Note QVCC should tied together externally live insertion supported tied together with QVCC
Truth Table
RBYP
High logic state High impedance state state High state high transition change from previous state change from previous state high state nominally respectively high state nominally respectively
Typical Application
11974
Test Circuits Timing Waveforms
11974
FIGURE Driver Propagation Delay Set-up
11974
FIGURE Driver
11974
FIGURE Driver
11974
FIGURE Driver ACLK
Switch Position
tPLH tPHL
open close
11974 11974
FIGURE Receiver Propagation Delay Set-up
FIGURE Receiver
Test Circuits Timing Waveforms (Continued)
Switch Position
tPZL tPLZ tPZH tPHZ
close open open close
11974
FIGURE Receiver Enable Disable Set-up
11974
FIGURE Receiver Enable Disable Set-up
11974
FIGURE
11974
FIGURE Receiver (tPHZ tPZH only)
11974
FIGURE (tPHLand tPLH only) (tPZLand tPLZ only)
General Description (Continued)
Backplane Transceiver Logic (BTL) signaling standard that invented first introduced National Semiconductor then developed IEEE enhance performance backplane buses compatible transceivers feature output capacitance drivers minimize loading nominal signal swing reduced power consumption receivers with precision thresholds maximum noise immunity standard eliminates settling time delays that severely limit performance thus provide significantly higher transfer rates backplane intended operated with termination resistors (selected match impedance) connected both ends voltage typically Separate ground pins provided each output minimize induced ground noise during simultaneous switching unique driver circuitry meets maximum slew rate which allows controlled rise fall times reduce noise coupling adjacent lines transceiver's high impedance control driver inputs fully compatible receiver high speed comparator that utilizes Bandgap reference precision threshold control allowing maximum noise immunity signaling level Separate QVCC QGND pins provided minimize effects high current switching noise output TRI-STATE fully compatible DS3886A supports live insertion defined IEEE through (Live Insertion) implement live insertion should connected live insertion power connector this function supported must tied DS3886A also provides glitch free power down protection during power sequencing DS3886A types power connections addition They Logic (VCC) Quiet (QVCC) There Logic pins DS3886A that provide supply voltage logic control circuitry Multiple connections provided reduce effects package inductance thereby minimize switching noise these pins common internal device voltage delta should never exist between these pins voltage difference between QVCC should never exceed because circuitry When (Chip Disable) high high impedance state high transmit data signal high When RBYP high positive edge triggered flip-flop transparent mode When RBYP positive edge ACLK signal clocks data addition circuitry between pins other pins except pins requires that voltage these pins should exceed voltage There three different types ground pins DS3886A logic ground (GND) grounds (B0GND B8GND) Bandgap reference ground (QGND) these ground reference pins isolated within chip minimize effects high current switching transients optimum performance QGND should returned connector through quiet channel that does carry transient switching current B0GND B8GND should connected nearest backplane ground with shortest possible path Since many different grounding schemes could implemented circuitry exists DS3886A important note that voltage difference between ground pins QGND B0GND B8GND should exceed including power down sequencing Additional transceivers included Military Futurebus family DS3884A Handshake Transceiver featuring selectable Wired-OR glitch filtering DS3885 Arbitration Transceiver with arbitration competition logic ABk7 signal lines DS3875 Arbitration Controller included Futurebus family supports required optional modes Futurebus arbitration protocol designed used conjunction with DS3884A DS3885 transceivers Logical Interface Futurebus Engine (LIFE) high performance Futurebus Protocol Controller designed IEEE 1991 LIFE will handle handshaking signals between Futurebus local interface Protocol Controller supports Futurebus compelled mode data transfer both master slave Protocol Controller configured operate compliance IEEE Profile mode LIFE IEEE compatible LIFE incorporates controller 64-bit FIFO's fast queuing transceivers offered 48-pin CERPAK high density package styles
DS3886A 9-Bit Latching Data Transceiver MIL-STD-883
Physical Dimensions inches (millimeters)
Order Number DS3886AW Package Number WA48A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
National Semiconductor Europe (a49) 0-180-530 Email cnjwge tevm2 Deutsch (a49) 0-180-530 English (a49) 0-180-532 Fran (a49) 0-180-532 Italiano (a49) 0-180-534
National Semiconductor Hong Kong 13th Floor Straight Block Ocean Centre Canton Tsimshatsui Kowloon Hong Kong (852) 2737-1600 (852) 2736-9960
National Semiconductor Japan 81-043-299-2309 81-043-299-2408
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

March 1994 DS3886A 9-Bit Latching Data Transceiver MIL-STD-883

Top Searches for this datasheet

Other recent searches