July 1993 NSBMC290 Burst Mode Memory Controller NSBMC290 fun
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NSBMC290-16 Burst Mode Memory Controller
July 1993
NSBMC290 Burst Mode Memory Controller
NSBMC290 functionally equivalent V29BMCThe NSBMC290 Burst Mode Memory Controller single chip device designed simplify implementation burst mode access high performance systems using Am29000Streamlined Instruction Processor extremely high instruction rate achieved this processor places extraordinary demands memory system designs maximum throughput sustained costs minimized most obvious solution problem access speed implement system memory using high-speed static memories However high cost density these devices make them expensive space consumptive solution more cost effective method solving this problem dynamic RAMs Their high density cost make their extremely attractive impediment their their relatively slow access times However when operated page mode dynamic RAMs behave more like static memories Properly managed they yield access times approaching those fully static RAMs function NSBMC290 interface page mode access protocol dynamic RAMs with more general burst mode access protocol supported Am29000 local channel device manages double banked arrangment dynamic RAMs such that when burst accesses permitted data read written rate word system clock cycle Packaged PQFP NSBMC290 drives memory arrays directly thus minimizing design complexity package count
Features
Interfaces directly Am29000 Local Channel Manages Page Mode Dynamic Memory devices Supports DRAMs from Manages Instruction Data Memory Very Power Consumption On-Chip Memory Address Multiplexer Drivers Flexible Instruction Data Buffer Management Software-Configured operational parameters Auto-Configured Bank Size Location High-Speed CMOS Technology
Block Diagram
Typical System Configuration
Logic Symbol
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This document contains information concerning product that been developed National Semiconductor Corporation Corporation This information intended help evaluating this product National Semiconductor Corporation Corporation reserves right change improve specifications this product without notice
TRI-STATE registered trademark National Semiconductor Corporation NSBMC290is trademark National Semiconductor Corporation V29BMCis trademark Corporation Am29000is trademark Advanced Micro Devices Sunnyvale California C1995 National Semiconductor Corporation 11803 RRD-B30M115 Printed
Connection Diagrams
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PQFP Order Number NSBMC290VF Package Number VF132A
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Bottom View Order Number NSBMC290UP Package Number UP124A
Descriptions
Signal Signal AA10 AB10 BINV CASA0 CASA1 CASA2 CASA3 CASB0 CASB1 CASB2 CASB3 DBACK DBLEA DBLEB DBREQ DBTXA DBTXB DRDY DREQ DREQT0 DREQT1 IBACK IBREQ IBTXA IBTXB IRDY IREQ IREQT MWEA MWEB Signal OPT0 OPT1 OPT2 RASA RASB Reserved Reserved Reserved Reserved RESET RSTOUT SYSCLK
Note order switching characteristics this device guaranteed necessary connect power pins (VCC VSS) appropriate power levels impedance wiring power pins required systems using Am29000 with attendant high switching rates multi-layer printed circuit boards with buried power ground planes required
Descriptions
Am29000 INTERFACE following pins have same function their counterparts Am29000 designed connected directly Am29000 Synchronous Channel Interface A0-31 Description Address (Input) address transfers byte addresses accesses memory array except burst mode NSBMC290 software configured memory block address within Gbyte address range Invalid (Input Active Low) This input indicates that address related control signals invalid This signal must (high) order NSBMC290 accept data instruction requests READ WRITE (Input) This input indicates whether data being transferred data memory array low) high)
BINV DBACK DBREQ DRDY DREQ DREQT0 OPT0
Data Burst Acknowledge (Output 3-State Active Low) This output signals that burst mode accesses between memory array data continued Data Burst Request (Input Active Low) This input used indicate when burst mode access data desired Data Ready (Output 3-State Active Low) This output used signal completion data access cycle Data Request (Input Active Low) This input signal initiation memory access cycle data Data Request Type (Input Active Low) These inputs specify address space data access They must both (low) order NSBMC290 accept data request Data Options (Input Active Low) These inputs specify data transfer size operating mode NSBMC290 responds only cycles which values asserted these signals compatible with specifications In-Circuit Emulators Pipelined Data Access (Input Active Low) This input indicates that address address next data access prior completion present data request Instruction Burst Acknowledge (Output 3-State Active Low) This output signals that burst mode accesses between memory array instruction continued Instruction Burst Request (Input Active Low) This input used request burst mode instruction access Instruction Ready (Output 3-state Active Low) This output signals completion each instruction access Instruction Request (Input Active Low) This input signals beginning instruction access cycle Instruction Request Type (Input Active High) This input specifies address space instruction access must (low) order NSBMC290 accept instruction request Pipelined Instruction Access (input Active Low) This input indicates that address address next instruction access prior completion present instruction request Pipeline Enable (Output 3-State Active Low) This output indicates that NSBMC290 capable accepting address next access before completion present access Reset (Input Active Low) This input initializes NSBMC290 accept software configuration information more than NSBMC290 used controlling memory NSBMC290 chips should daisy chained with RSTOUT from NSBMC290 chip connecting RESET next NSBMC290 Chip Reset (Output Active Low) This output active (low) whenever RESET active remains active until NSBMC290 been software configured System Clock (Input) This input used synchronize NSBMC290 Am29000 local channel interface
IBACK IBREQ IRDY IREQ IREQT RESET
RSTOUT SYSCLK
Descriptions (Continued)
MEMORY INTERFACE NSBMC290 designed drive memory array organized banks each bits address control signals memory array output through high current RAS(A drivers order minimize propagation delay memory input impedance trace capacitance External array drivers required address control signals however must externally terminated Description Multiplexed Addresses (Output High Current) These buses transfer multiplexed column addresses memory array banks respectively Address Strobes (Output High Current Active Low) These signals strobes that indicate existence valid address These signals connected interleaved banks memory assigned each bank Column Address Strobe (Output High Current Active Low) These signals strobes that indicate valid column address B)0-10 each these assigned each memory bank within each assigned each byte 32-bit memory Memory Write Enable (Output High Current Active Low) These signals write strobes DRAM memories supplied each banks memory although they logically identical performance criteria dictate order maintain separation data buffers required order maximize performance these buffers controlled directly NSBMC290 Description Data Latch Enable (Output Active High) These outputs used enable transparent latches latch data from Processor data each bank memory during write cycle (Data access only) following buffer control outputs multi-mode signals signal names they appear logic symbol default signal names (Mode more complete description presented configuration section DBTX(A IBTX(A Data Transmit (Output Active Low) These outputs used during read cycles enable data from individual banks memory drive data Instruction Transmit (Output Active Low) These outputs used during instruction cycles enable data from individual banks memory drive instruction
CAS(A B)0-3
MWE(A
BUFFER CONTROLS order limit system implementation strategies instruction data organization NSBMC290 permits designer keep these busses separate DBLE(A
Functional Description
PRODUCT OVERVIEW NSBMC290 designed simplify interface between Am29000 high-speed synchronous channel dynamic memories This integrated circuit responds defined instruction data access modes Am29000 handles required address decoding multiplexing DRAM memory array addition NSBMC290 automatically generates refresh cycles memory array Software configuration used setup memory block address refresh rate byte order buffer control type DRAM memory chip size parameters NSBMC290 more memory blocks used implement Am29000 memory sub-system processor simultaneously access memory block data second memory block instruction both accesses directed same memory block NSBMC290 will hold second access until first completed only then will process second access SYSTEM INTERFACE NSBMC290 connects directly Am29000 address instruction data controls signals interface handles simple pipelined burst mode access both data instruction according Am29000 channel specification requires external logic implement synchronous channel connection Thus avoids propagation delays signal skews that detract from system performance increase system complexity MEMORY INTERFACE NSBMC290 directly drives array DRAM devices which support page mode accesses array organized banks bits each supported devices standard memory size from Kbit Mbit Selection device done software During burst accesses NSBMC290 executes interleaved page mode accesses banks This allows memory full processor speed memory cycle processor cycle data accesses NSBMC290 controls memory four independent 8-bit bytes order allow 32-bit accesses byte order interpreting byte address software configurable However NSBMC290 does detect access overflows word boundary software operating Am29000 should manage correct alignment memory accesses that word aligned Systems using Am29000 processors whose revision level previous Revision ``C'' must manage alignment byte data through software that data will retain correct justification NSBMC290 allows flexibility control instruction data buffers memory array Propagation delay minimized providing these controls directly allowing control strategy software programmable example 74F245 high current Am29861 buffers used without external ``glue'' circuitry CONFIGURATION NSBMC290 configured first 32-bit memory read access following deassertion RESET signal multiple NSBMC290 devices used circuit they should daisy chained together with RSTOUT from chip connecting RESET next chip When NSBMC290 been configured deasserts RSTOUT signal allowing next NSBMC290 chain then configured NSBMC290 devices must configured before memory accesses attempted
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FIGURE NSBMC290 Configuration Word
Functional Description (Continued)
BLOCK ADDRESS Once configured NSBMC290 only responds addresses within block address range configured programmed value corresponds starting address block while size block determined size devices used example DRAM devices selected memory block size bytes always located byte boundary Figure shows least significant block address each block size BYTE ORDER When configuration word convention used numbering sequential bytes word that byte address selects bits byte address selects bits configuration word this ordering reversed byte address selects order data within byte unaffected byte order selected This feature facilitates implementation multi-processor systems which programmable Little Endian byte order supported processors BURST WRITE CYCLES NSBMC290 supports instruction data reads rate access SYSCLK cycle during bursts However flexibility data buffer strategy such that buffer memory device combinations selected which data hold time during single clock write cycles cannot guaranteed across system operating conditions temperature voltage clock write cycle thus been provided order support these combinations Configuration clock data burst write cycle required single clock write cycle possible NSBMC290 Application Guide details factors that influence selection this parameter ACCESS CYCLES maximize choice memory device speeds that used with various system clock rates NSBMC290 configured such that Address Strobe (RAS) period lasts either clock periods during simple accesses When configuration indicates that clock cycles used when required Calculation number cycles required detailed NSBMC290 Application Guide BUFFER CONTROL MODES combination programmable period burst write cycle duration permit system designer trade memory device speed organization order optimize system performance cost storage capacity This flexibility further enhanced providing multiple methods buffering memory sub-system Am29000 Local Channel TABLE Interpretation Buffer Control Signals Various Control Modes
Modes Bits Signal
Signal
Signal Signal IBTxA IBTxA IBTx IBTx IBTxB IBTxB IBTx IBTx
DBTxA DBTxB DBCeA DBCeB DBTx BankB DBCe BankB
Note mode signal names defaults used reference purposes
transfer Instructions Data from memory subsystem Local Channel occurs through buffers controlled NSBMC290 signals provided this purpose four operate multiple modes remaining (DBLeA DBLeB) have fixed interpretation These signals provide latch enable controls transparent latches during data transfers from Am29000 memory functions performed remaining four signals change according programmed mode Table presents these signals using names that function derived Signals with prefix used control Data operations while those starting with control instruction operations Signals containing Buffer transmit controls which typically used with buffers that have output enables (transmit relative memory system) Buffers such 74F245 74F646 which have direction enable pins controlled with (chip enable) signal (DBCE DBCEa DBCEb) Signals ending with specific other interleaved banks memory controlled NSBMC290 signals without suffixes apply both banks signal BankB required some configurations indicates which DRAM memory bank will next selected
Functional Description (Continued)
TABLE Buffer Control Signals Memory Bank Which they active Simple Pipeline Cycle Signal Name DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb BankB (Note Read Write Read (Note (Note (Note (Note (Note (Note (Note (Note (Note Memory Bank next active Bank next (Note (Note (Note Burst Cycle Write
Note Remains active over entire burst cycle regardless bank being accessed Note Asserted only when specific bank being accessed Note Must externally synchronized SYSCLK
memory buffer strategy required will depend type DRAMs being used (bit wide nibble wide components) access time these memories desired burst write speed system clock speed Table presents some possible configurations with corresponding mode settings comprehensive discussion selection buffer strategy lease refer NSBMC290 Application Guide This document expands rationale selection process presents specific application examples circuit diagrams TABLE Possible NSBMC290 Memory Buffer Configurations Buffer Type 74F245 74F245 74F245 74F646 74F245 74F646 Am29C983 29827 29861 DRAM Organization Nibble Nibble Burst Write Cycle Cycle Cycle Cycle Cycle Cycle Buffer Mode Mode Mode Mode Mode Mode Mode
example system clock programmed value NSBMC20 will execute refresh cycles 256k DRAM configuration word frequency field while refresh algorithm employed NSBMC290 guarantees time complete device refresh however time individual refreshes held prevent preemption burst DRAM SIZE This field configures NSBMC290 correct memory address size hence total memory block size Note that memory both banks block required same size organization order correct operation occur Table lists supported device sizes TABLE Size Code Settings DRAM Density Address Range Size
Memory Size Code Bits
DRAM Address Size
Memory Block Size KBytes MBytes MBytes MBytes
SYSTEM CLOCK FREQUENCY system clock frequency used derive period DRAM refresh cycles refresh rate given (system clock frequency) (programmed value This meets nominal refresh requirements DRAM devices
Functional Description (Continued)
INTERCONNECT DETAILS NSBMC290 applied designs where instruction data memories separated designs where single memory space used both instruction data split instruction data designs control signals address space required simply pulled levels connected corresponding local channel signals TABLE Control Signal Unique Instruction Accesses Signal Type Input Output Buffer Control Signal Names IREQ IBREQ IREQT IBACK IRDY IBTXA IBTXB IBTX BANKB
Typical Application
SYSTEM IMPLEMENTATION DESIGN ease with which NSBMC290 integrated into system design illustrated diagram Figure system shown supports Am29000 with between memory (depending storage devices selected) managed single NSBMC290 This specific example accommodates 256k devices minimal system configuration only NSBMC290 required This because NSBMC290 manages both instruction data access memory block However with single memory block instruction data accesses cannot overlapped number burst access restarts function which software designed therefore difficult predict performance degradation maximum performance required addition more NSBMC290s effective solution bench marks indicate that systems with physically separated instruction data space performance degraded approximately over theoretical rate achieved system designs employing high speed static RAMs device count cost these solutions however differ least factor With exception data buffers external components required except terminate address control lines memory array passive components arranged serial parallel terminating network simple effective method implementing this requirement
TABLE Control Signal Unique Data Accesses Signal Type Input Output Buffer Control Signal Names DREQ DBREQ DREQT DBACK DRDY DBCEA DBCE DBTXA DBTX BANKB
mixed instruction data designs local channel signals must connected Tables detail control signal sets required NSBMC290 control corresponding address spaces recommended that control signals connected that instruction data space segregation done software allocation Am29000 internal Translation Look-Aside Buffer
Typical Application (Continued)
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FIGURE Possible System Interconnection Using NSBMC290
INTERFACE NSBMC290 interface Am29000 been designed direct interconnect Normally necessary place other logic devices between processor NSBMC290 memory with exception Instruction Data buffers introduction intermediate buffers result skews delays that will require that system clock frequency derated operation under worst case conditions SIMPLE ACCESS SEQUENCE NSBMC290 return data processor only clocks clocks simple access depending mode chosen (Configuration multiple access
cycles requested back back then will pause minimum clocks between cycles insure that precharge time resulting clocks clocks between successive simple cycles (depending Configuration access modes begin their cycle same fashion simple access simple access become either pipelined burst access appropriate inputs driven Figure shows timing relationship between system clock processor control signals NSBMC290 outputs NSBMC290 outputs derived synchronously with exception tARA7 (processor address memory address delay) shaded section Figure represents extra cycle inserted when configuration register initialized with cleared
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DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb
FIGURE Simple Access Sequence
Typical Application (Continued)
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FIGURE Burst Read Sequence (Illustrating Burst Suspension) BURST ACCESS SEQUENCE When Burst access been established NSBMC290 generates signal sequence Figure This access sequence will continue until either canceled suspended Am29000 normal burst termination occurs NSBMC290 will preempt burst sequence only case that refresh cycle been requested been outstanding time excess refresh period FUNCTIONAL OVERVIEW BURST ACCESS Figure diagrams sequence events that take place during typical burst sequence This specific example describes operations surrounding instruction data reads example illustrates burst operation established suspended cycle subsequently terminated master sequence commences when NSBMC290 selected Once selected drives memory bank which contains data initial access burst cycle (Bank this case) During next period (T1) CASa asserted other memory bank (RASb) activated Access second memory bank offset cycle order that bank interleave will occur correctly first word data available processor indicated asserted Data from memory must propagate through data buffers meet setup time processor extra cycle inserted into start-up phase burst sequence configuration register programed ``0'' This increases assertion time from cycles cycles resulting delay inserted during
Absolute Maximum Ratings
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Supply Voltage (VCC) Input Voltage (VIN) Input Current (IIN) Storage Temperature (TSTG)
Recommended Operating Conditions
Supply Voltage (VCC) Ambient Temperature (TA) Plastic Package Ceramic Package
Electrical Characteristics
Symbol IOZL IOZH ICC(Max) COUT Description Level Input Voltage High Level Input Voltage Level Input Current High Level Input Current Level Output Voltage High Level Output Voltage Level TRI-STATE Output Current Level TRl-STATE Output Current Maximum Supply Current Input Capacitance Output Capacitance Conditions Continuous Simple Access Continuous Burst Access
Units
Timing Parameters
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DBTX DBTXa DBTXb DBCE DBCEa DBCEb IBTX IBTXa IBTXb
FIGURE Simple Access Timing
Timing Parameters (Unless otherwise stated
Symbol tBSU tRQSU tRQH tBRH tARA tRAH tDRAH tCAV tCAH tRSHL tRSLH tCHL tCLH tPZH Description BlNV Setup BINV Hold Request Sync Setup Time Request Sync Hold Time Synchronous Input Setup Synchronous Input Setup DBREQ only Synchronous Input Hold SYSCLK Burst Request Input Hold Address Input Address output delay (Note SYSCLK address hold DRAM Address Hold (Note SYSCLK Column Address Valid Delay (Note SYSCLK Column Address Hold SYSCLK Asserted Delay (Note SYSCLK De-asserted Delay (Note SYSCLK Asserted Delay (Note SYSCLK De-asserted (Note 3-state Valid Delay Relative SYSCLK Synchronous Assertion Delay Synchronous Deassertion Delay Valid 3-state Delay Relative SYSCLK 3-state Valid Delay Relative SYSCLK Synchronous Assertion Delay Synchronous De-assertion Delay Valid 3-state Delay Relative SYSCLK Synchronous Latch Enable Assertion delay Synchronous Latch Enable De-assertion Delay Synchronous Buffer Enable Assertion Delay Synchronous Buffer Enable De-assertion Delay Synchronous Input Setup Time Synchronous Input Hold Time Synchronous Write Enable Valid Delay Relative SYSCLK Synchronous DBACK Valid Delay Synchronous DBACK Assertion Delay Synchronous DBACK Deassertion Delay Synchronous DBACK Valid 3-state Delay Asynchronous DBACK Deassertion delay relative DREQ tCLK-4
tCLK-4
tCLK-3
tCLK-2
Units
tPHL tPLH tPHZ tRZH tRHL tRLH tRHZ tLEHL tLELH tBHL tBLH tRWSU
tRWH tWEV tBKZH tBKHL tBKLH tBKHZ tABKLH
Signal output delays measured relative SYSCLK (except indicated) using load Note Derate given delays load excess Note Where tCLK Clock Frequency)
Timing Parameters (Continued)
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IBTXa DBTXa IBCEa DBCE IBTXb DBTXb IBCEb DBCEb BANKb
Note Buffer control signal timing illustrated using mode dependent signal naming convention (See page shown switching behavior typical modes modes timing signals DBTX DBCE IBTX remain unchanged
FIGURE Burst Access Timing TABLE VIII Burst Access Timing Parameters Symbol tCHL tCLH tCAV tCAH tBHL tBLH tLEHL tLELH Description SYSCLK Assertion (Note SYSCLK De-Assertion (Note SYSCLK Column Address Valid Delay (Note SYSCLK Column Address Hold Time (Note SYSCLK Buffer Control Assertion Delay SYSCLK Buffer Control De-Assertion Delay SYSCLK Latch Enable Assertion SYSCLK Latch Enable De-Assertion Units
Signal output delays measured relative SYSCLK (except indicated) using load Note Derate given delays load excess
Release Notes NSBMC290 Revision ``A''
NOTE OPERATION Am29000 characteristic Am29000 (Rev that deassert IBREQ signal independently current state IRDY IBACK V29BMC (Rev accommodates this behavior cases with exception ERRATUM IBREQ de-asserted clock cycles before IRDY returned instruction access cycle followed next clock cycle data write write enable signals from V29BMC memory asserted clock cycle before de-asserted memory location following last completed instruction access corrupted primary difference between recommended solutions that given Figure makes high current drivers V29BMC driving write enable signal memory array systems using organized memories this type drive capability desired ``or'' function implemented 'F32 moved inside appropriately modifying equations maximum performance should discrete gate shown This modification only required V29BMC controlling memories from which instructions being This modification however implemented will affect timing Pipeline Cycles connect V29BMC whose write timing modified connect only pull-up resistor V29BMC controlling data only memory changes write enable timing required pipeline access used Using data pipelining performance improvements order have been observed ERRATUM buffer mode selected then possible DBCE(a asserted during refresh cycle This will happen data write cycle accessing followed next cycle read cycle also accessing such that refresh starts with read result that data driven buffers controlled V29BMC when other devices using RECOMMENDED There number possible fixes which outlined below first solution mode buffer control signals generate DBCE(a signal from WE(a DBTX(a Make sure that mode 2(or operation selected V29BMC configuration word
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RECOMMENDED ``write enables'' memory must delay clock cycle This achieved following ways signals used latch write enable from V29BMC shown Figure write enable into V29BMC delayed Figure
FIGURE logic shown Figure implemented using following positive true logic equation RASa RASa MWEa MWEb since they identical
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FIGURE Generation DBCE from DBTX Signals second solution DBCE(a signal qualify using DBLE signals shown below
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FIGURE Modification DBCE Signal Using V29BMC Latch Enable Signals
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FIGURE shown Figure programmed with following equations depending which dotted paths connected ONLY RASa RASb ONLY RASa RASb IREQ
Ordering Code Information
National Semiconductor Mode Burst Mode Controller Processor 29000 Family Frequency Packaging 124-Lead PPGA 132-Lead PQFP
Physical Dimensions inches (millimeters)
Grid Array (PGA) Order Number NSBMC290UP Package Number UP124A
NSBMC290-16 Burst Mode Memory Controller
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Flatpak (PQFP) Order Number NSBMC290VF Package Number VF132A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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