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NM27P040 4 194 304-Bit 512K x 8 Processor Oriented CMOS EPROM

NM27P040 4 194 304-Bit (512K x 8) Processor Oriented CMOS EPROM

NM27P040 4 194 304-Bit (512K x 8) Processor Oriented CMOS EPROM
December 1993
NM27P040 4 194 304-Bit (512K x 8) Processor Oriented CMOS EPROM
General Description
Features
Block Diagram
TRI-STATE is a registered trademark of National Semiconductor Corporation POP is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL D 11367 RRD-B30M105 Printed in U S A
Connection Diagrams
27C080 A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 27C020 XX VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 27C010 XX VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
DIP NM27P040
27C010 VCC XX PGM XX A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
27C020 VCC XX PGM A17 A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3
27C080 VCC A18 A17 A14 A13 A8 A9 A11 OE VPP A10 CE PGM O7 O6 O5 O4 O3
Note Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27P040 pin
Package Types NM27P040 QXXX Q e Quartz-Windowed Ceramic DIP All packages conform to the JEDEC standard All versions are guaranteed to function for slower speeds
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature All Input Voltages except A9 with Respect to Ground (Note 10) VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground
Operating Range
Range Commercial Industrial Military Temperature 0 C to a 70 C b 40 C to a 85 C b 55 C to a 125 C VCC
Tolerance
b 0 6V to a 7V l 2000V ESD Protection All Output Voltages with Respect to Ground (Note 10) VCC a 1 0V to GND b0 6V
Read Operation DC Electrical Characteristics Over operating range with VPP e VCC
Symbol VIL VIH VOL VOH ISB1 ISB2 ICC IPP VPP ILI ILO Parameter Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) (Note 11) VCC Standby Current VCC Active Current VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current VIN e 5 5V or GND VOUT e 5 5V or GND IOL e 2 1 mA IOH e b2 5 mA CE e VCC g 0 3V CE e VIH CE e OE e VIL I O e 0 mA f e 5 MHz VPP e VCC VCC b 0 4
Test Conditions
AC Electrical Characteristics Over operating range with VPP e VCC
Symbol tACC tCE tOE tDF (Note 2) tCF (Note 2) tOH (Note 2) Parameter Min Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Chip Disable to Output Float Output Hold from Addresses CE or OE Whichever Occurred First 7 120 Max 120 120 50 35 35 Min 150 Max 150 150 50 25 30 7 7 Min 170 Max 170 170 50 25 30 7 Min 250 Max 250 250 50 25 30 ns Units
Capacitance TA e a 25 C
Symbol CIN COUT Parameter Input Capacitance Output Capacitance
f e 1 MHz (Note 2) Conditions VIN e 0V VOUT e 0V Typ 9 12 Max 15 15 Units pF pF
AC Test Conditions
Output Load Input Rise and Fall Times Input Pulse Levels 1 TTL Gate and CL e 100 pF (Note 8) s 5 ns 0 45V to 2 4V Timing Measurement Reference Level Inputs Outputs 0 8V and 2V 0 8V and 2V
AC Waveforms (Notes 6
Programming Waveform (Note 3)
Programming Characteristics (Notes 1
Symbol tAS tOES tDS tVPS tVCS tAH tDH tDF tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT Parameter Address Setup Time OE Setup Time Data Setup Time VPP Setup Time VCC Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
CE PGM e VIH
CE PGM e VIH CE PGM e VIL
Fast Programming Algorithm Flow Chart
FIGURE 1
Functional Description
Functional Description (Continued)
Mode Selection
The modes of operation of the NM27P040 are listed in Table I A single 5V power supply is required in the read mode All inputs are TTL levels except for VPP and A9 for device signature
TABLE I Modes Selection Pins Mode Read Output Disable Standby Programming Program Verify Program Inhibit
Note 1 X can be VIL or VH
CE PGM VIL X VIH VIL VIH VIH
OE VIL VIH X VIH VIL VIH
VPP X (Note 1) X X 12 75V 12 75V 12 75V
Outputs DOUT High Z High Z DIN DOUT High Z
NM27P040 4 194 304-Bit (512K x 8) Processor Oriented CMOS EPROM
Physical Dimensions inches (millimeters)
32-Lead EPROM Ceramic Dual-In-Line Package (JQ) Order Number NM27P040QXXX NS Package Number J32AQ
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