NM27P512 288-Bit (64K Processor Oriented CMOS EPROM NM27P512 512K

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NM27P512 288-Bit (64K Processor Oriented CMOS EPROM NM27P512 512K

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NM27P512 288-Bit (64K Processor Oriented CMOS EPROM
NM27P512 288-Bit (64K Processor Oriented CMOS EPROM
NM27P512 512K Processor Oriented EPROM configured It's designed simplify microprocessor interfacing while remaining compatible with standard EPROMs reduce both wait states glue logic when specification improvements taken advantage system design NM27P512 implemented National's advanced CMOS EPROM process provide excellent reliability access times fast interface improvements address areas eliminate need additional devices adapt EPROM microprocessor eliminate wait states termination access cycle Even with these improvements NM27P512 remains compatible with industry standard JEDEC pinout EPROMs maximum specification output turn-off time been reduced eliminating need wait states read cycle Also minimum specification output hold time been increased eliminating need external circuitry hold data
Features
Fast output turn eliminate wait states Extended data hold time microprocessor compatibility High performance CMOS access time JEDEC standard configuration Manufacturer's identification code
Block Diagram
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TRI-STATE registered trademark National Semiconductor Corporation NSC800is trademark National Semiconductor Corporation C1995 National Semiconductor Corporation 11365 RRD-B30M105 Printed
Connection Diagrams
27C080 27C040 27C020 27C010 27C256
NM27P512
27C256
27C010
27C020
27C040
27C080
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Note Compatible EPROM configurations shown blocks adjacent NM27P512 pins
Commercial Temp Range Parameter Order Number NM27P512 NM27P512 NM27P512 Access Time (ns)
Extended Temp Range (b40 Parameter Order Number NM27P512 NM27P512 NM27P512 Access Time (ns)
Military Temp Range (b55 Parameter Order Number NM27P512 Access Time (ns)
Note Surface mount PLCC package available commercial extended temperature ranges only versions guaranteed function slower speeds
Package Types NM27P512 Quartz-Windowed Ceramic Package Plastic Package PLCC Package packages conform JEDEC standard PLCC
Names Addresses Chip Enable Output Enable Outputs Program Don't Care (During Read)
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Absolute Maximum Ratings (Note
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature Input Voltages Except with Respect Ground with Respect Ground
Supply Voltage with Respect Ground Protection (MIL Method 3015 Output Voltages with Respect Ground
2000V
Operating Range
Range Comm'l Industrial Military Temperature
Tolerance
Read Operation Electrical Characteristics
Symbol ISB1(10) ISB2 Parameter Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current Active Current Supply Current Read Voltage Input Load Current Output Leakage Current VOUT
Test Conditions
Units
Electrical Characteristics
Symbol tACC tDF(2) tCF(2) tOH(2) Parameter Address Output Delay Output Delay Output Delay Output Disable Output Float Chip Disable Output Float Output Hold from Addresses Whichever Occurred First Units
Capacitance
Symbol CIN1 COUT CIN2
(Note Parameter Input Capacitance except Output Capacitance Input Capacitance Conditions VOUT Units
Test Conditions
Output Load Input Rise Fall Times Input Pulse Levels Gate (Note Timing Measurement Reference Level (Note Inputs Outputs
Waveforms (Notes
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Note Stresses above those listed under ``Absolute Maximum Ratings'' cause permanent damage device This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied Exposure absolute maximum rating conditions extended periods affect device reliability Note This parameter only sampled 100% tested Note delayed tACC after falling edge without impacting tACC Note compare level determined follows High TRI-STATE measured VOH1 (DC) TRI-STATE measured VOL1 (DC) Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling recommended that least ceramic capacitor used every device between Note outputs must restricted avoid latch-up device damage Note Gate includes fixture capacitance Note Inputs outputs undershoot Note CMOS inputs
Programming Characteristics (Notes
Symbol tOES tVCS tOEH tPRT tOUT Parameter Address Setup Time Setup Time Data Setup Time Setup Time Address Hold Time Data Hold Time Chip Enable Output Float Delay Program Pulse Width Hold Time Data Valid from Pulse Rise Time during Programming Recovery Time Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage Conditions Units
Programming Waveforms
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Note National's standard product warranty applies devices programmed specifications described herein Note must applied simultaneously before removed simultaneously after EPROM must inserted into removed from board with voltage applied Note maximum absolute allowable voltage which applied during programming Care must taken when switching supply prevent overshoot from exceeding this maximum specification least capacitor required across suppress spurious voltage transients which damage device Note Programming program verify tested with fast Program Algorithm typical power supply voltages timings
Fast Programming Algorithm Flow Chart
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FIGURE
Functional Description
DEVICE OPERATION modes operation EPROM listed Table should noted that inputs modes levels power supplies required power supply must during three programming modes must other three modes power supply must during three programming modes other three modes Read Mode EPROM control functions both which must logically active order obtain data outputs Chip Enable PGM) power control should used device selection Output Enable VPP) output control should used gate data output pins independent device selection Assuming that addresses stable address access time (tACC) equal delay from output (tCE) Data available outputs after falling edge assuming that been addresses have been stable least tACC Standby Mode EPROM standby mode which reduces active power dissipation over from EPROM placed standby mode applying CMOS high signal input When standby mode outputs high impedance state independent input Output Disable EPROM placed output disable applying high signal input When output disable circuitry enabled except outputs high impedance state (TRI-STATE) Output OR-Typing Because EPROM usually used larger memory arrays National provided 2-line control function that accommodates this multiple memory connections 2-line control function allows lowest possible memory power dissipation complete assurance that output contention will occur most efficiently these control lines recommended that decoded used primary device selecting function while made common connection devices array connected READ line from system control This assures that deselected memory devices their power standby modes that output pins active only when data desired from particular memory device Programming CAUTION Exceeding VPP) will damage EPROM Initially after each erasure bits EPROM ``1's'' state Data introduced selectively programming ``0's'' into desired locations Although only ``0's'' will programmed both ``1's'' ``0's'' presented data word only change ``0'' ``1'' ultraviolet light erasure EPROM programming mode when required that least capacitor placed across ground suppress spurious voltage transients which damage device data programmed applied bits parallel data output pins levels required address data inputs When address data stable active program pulse applied input program pulse must applied each address location programmed EPROM programmed with Fast Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good maximum pulses Most memory cells will program with single pulse EPROM must programmed with signal applied input Programming multiple EPROM parallel with same data easily accomplished simplicity programming requirements Like inputs parallel EPROM connected together when they programmed with same data level pulse applied input programs paralleled EPROM Program Inhibit Programming multiple EPROMs parallel with different data also easily accomplished Except like inputs (including VPP) parallel EPROMs common level program pulse applied EPROM's input with will program that EPROM high level input inhibits other EPROMs from being programmed
Functional Description (Continued)
Program Verify verify should performed programmed bits determine whether they were correctly programmed verify accomplished with Data should verified after falling edge AFTER PROGRAMMING Opaque labels should placed over EPROM window prevent unintentional erasure Covering window will also prevent temporary functional failure generation photo currents MANUFACTURER'S IDENTIFICATION CODE EPROM manufacturer's identification code programming When device inserted EPROM programmer socket programmer reads code then automatically calls specific programming algorithm part This automatic programming control only possible with programmers which have capability reading code Manufacturer's Identification code shown Table specifically identifies manufacturer device type code NM27P512 ``8F85'' where ``8F'' designates that made National Semiconductor ``85'' designates 512K part code accessed applying address Addresses A1-A8 A10-A16 control pins held Address held manufacturer's code held device code code read eight data pins Proper code access only guaranteed ERASURE CHARACTERISTICS erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths 3000 -4000 range recommended erasure procedure EPROM exposure short wave ultraviolet light which wavelength 2537 integrated dose intensity exposure time) erasure should minimum 15W-sec EPROM should placed within inch lamp tubes during erasure Some lamps have filter their tubes which should removed before erasure Table shows minimum EPROM erasure time various light intensities erasure system should calibrated periodically distance from lamp device should maintained inch erasure time increase square distance from lamp distance doubled erasure time increases factor Lamps lose intensity they When lamp changed distance changed lamp aged system should checked make certain full erasure occurring Incomplete erasure will cause symptoms that misleading Programmers components even system designs have been erroneously suspected when incomplete erasure problem SYSTEM CONSIDERATION power switching characteristics EPROMs require careful decoupling devices supply current three segments that interest system designer standby current level active current level transient current peaks that produced voltage transitions input pins magnitude these transient current peaks dependent output capacitance loading device associated transient voltage peaks suppressed properly selected decoupling capacitors recommended that least ceramic capacitor used every device between This should high frequency capacitor inherent inductance addition least bulk electrolytic capacitor should used between each eight devices bulk capacitor should located near where power supply connected array purpose bulk capacitor overcome voltage drop caused inductive effects board traces
Mode Selection
modes operation NM27P512 listed Table single power supply required read mode inputs levels excepts device signature TABLE Mode Selection Pins Mode Read Output Disable Standby Programming Program Verify Program Inhibit
Note
(Note
Outputs DOUT High High DOUT High
TABLE Manufacturer's Identification Code Pins Manufacturer Code Device Code (10) (24) (19) (18) (17) (16) (15) (13) (12) (11) Data
Physical Dimensions inches (millimeters)
Window Cavity Dual-In-Line Cerdip Package Order Number NM27P512Q Package Number J28CQ
28-Lead Plastic One-Time-Programmable Dual-In-Line Order Number NM27P512N Package Number N28B
NM27P512 288-Bit (64K Processor Oriented CMOS EPROM
Physical Dimensions inches (millimeters) (Continued)
32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27P512V Package Number VA32A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
National Semiconductor Europe (a49) 0-180-530 Email cnjwge tevm2 Deutsch (a49) 0-180-530 English (a49) 0-180-532 Fran (a49) 0-180-532 Italiano (a49) 0-180-534
National Semiconductor Hong Kong 13th Floor Straight Block Ocean Centre Canton Tsimshatsui Kowloon Hong Kong (852) 2737-1600 (852) 2736-9960
National Semiconductor Japan 81-043-299-2309 81-043-299-2408
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

NM27P512 288-Bit (64K Processor Oriented CMOS EPROM NM27P512 512K

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