April 1990 DP83290EB FDDI Physical Layer Evaluation Board In

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April 1990 DP83290EB FDDI Physical Layer Evaluation Board In

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DP83290EB FDDI Physical Layer Evaluation Board
April 1990
DP83290EB FDDI Physical Layer Evaluation Board
Introduction
This document intended provide user with overview concerning design operation installation National Semiconductor DP83290EB FDDI Physical Layer Evaluation Board hereafter referred Link Card Appendix included this document other appendices found DP83290EB FDDI Physical Layer Evaluation Board User's Guide They listed here reference only
Table Contents
INTRODUCTION EVALUATION BOARDS ENVIRONMENT Link Card Description Link Card Features BMAC Card Description Station Environment (PC-AT Platform) SYSTEM DESCRIPTION Block Diagram Description Interface Block Clock Block Device Block Device Block Link Block PLAYERDevice Block Transceiver Block APPENDICES Board Specifics Installation Layout Considerations Pinouts Point Point Applications Configuration Diagrams Board Schematics Circuit Schematics Layout Plots Interface Equations Component Inventory
PLAYERis trademark National Semiconductor Corporation C1995 National Semiconductor Corporation
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RRD-B30M105 Printed
Evaluation Boards Environment
Link Card Description Link Card intended evaluation following three National Semiconductor devices which implement FDDI Physical Layer clock distribution DP83255 Physical Layer Controller (PLAYER device) DP83241 Clock Distribution Device (CDD device) DP83231 Clock Recovery Device (CRD device) design goal Link Card allow user exercise Physical Layer devices device Link Card used tandem with DP83291EB Card (see Section Link Card connected single Card implements single attachment station Dual attachment stations require Link Cards Link Card requires PC-AT compatible machine which readily available platform capable supporting FDDI application Link Card Features Link Card offers many features provide flexible convenient evaluation platform BMAC Card Description National Semiconductor DP83291EB BMAC Evaluation Board hereafter referred BMAC Card intended evaluation DP83261 Basic Media Access Controller (BMAC device) design goal BMAC Card allow user exercise BMAC functions BMAC Card requires PC-AT compatible environment This environment readily available evaluation platform capable supporting FDDI application Station Environment (PC-AT Platform) PC-AT compatible environment chosen National Semiconductor evaluation platform because availability PC-AT compatible machines Although PC-AT does have performance workstation PC-AT does provide relatively simple interface abundance user applications that used support evaluation platform
System Description
Block Diagram Description Link Card block diagram composed following seven blocks Interface Clock Interface Clock Distribution Device (CDD device) Clock Recovery Device (CRD device) Link Interface Physical Layer Controller (PLAYER device) Transceiver Interface Figure detailed representation block diagram
Utilizes National FDDI Chip
DP83255 PLAYER Device DP83241 Device DP83231 Device System modularity supports single attachment dual attachment configurations
Utilizes PC-AT compatible form factor Built-in diagnostic capability fault detection Supports external optical bypass switch Power consumption amps typical Link Card
System Description (Continued)
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FIGURE Link Card Block Diagram
System Description (Continued)
Interface Block function Interface Block interface Link Card with host This block features full 24-bit address flexible Link Card memory placement data bits wide which adequate this demo platform Bits through used base Link Card they have been tapped test points board test points included event that application requires 16-bit data addition address data buses seven interrupts necessary control signals included address data signal lines buffered with independent parity generation supplied data block sole power supply Link Card address decoding scheme accomplished with generic array logic devices (GALs) Equations each four devices included Appendix DP83290EB FDDI Physical Layer Evaluation Board User's Guide Beyond these basic functions Interface offers number modes such autoconfiguration base register area select memory configuration Clock Block Clock Block included Link Card design provide physical among Link Cards that form station construction twenty ribbon cable capable supporting signals Each signal surrounded either side ground line reduce crosstalk Device Block Clock Distribution Device clock generation distribution device intended FDDI networks device provides complete clocks required convert byte wide data serial format fiber medium transmission move byte wide data between PLAYER BMAC devices various station configurations differential clocks generated conversion data serial format clocks generated byte wide data transfers Device Block Clock Recovery Device been designed used this FDDI implementation device receives serial data from Fiber Optic Receiver (FORX) differential NRZI group code format outputs resynchronized NRZI received data received clock differential format PLAYER device Link Block function Link provide data path between Link Cards that form FDDI station Each connection contains 10-bit data buses (Indicate Request) station configuration signals pinout Link been designed allow user build Single Attachment Dual Attachment Single configurations build these configurations user must simply connect cabling manner shown Appendix User's Guide Every other wire Link grounded insure data integrity This cabling scheme been tested resistance data corruption induced crosstalk Player Device Block Physical Layer Controller part National Semiconductor's FDDI Chip implements Physical Layer entity defined ANSI X3T9 standard PLAYER device performs encoding decoding serialization deserialization data repeat filter line state control detection also contains configuration switch PLAYER device supports many types station configurations allowed standard Although tailored FDDI specification PLAYER device also well suited high speed point-to-point communication links over optical fibers coaxial cable Transceiver Block transceiver block consists parts fiber optic receiver fiber optic transmitter Link Card supports following FDDI optical transceiver modules Lightwave Data Links Sumitomo DM-742 1300nm Data Link transceiver pair which supports footprint format composed independent 16-pin (footprints) Appendix User's Guide detailed footprint description
Appendices
Board Specifics Installation Setup
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DP83290EB FDDI Physical Layer Evaluation Board
Appendices (Continued)
Setup (Continued)
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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

April 1990 DP83290EB FDDI Physical Layer Evaluation Board In

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