July 1992 100336 Power 4-Stage Counter Shift Register 100336
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100336 Power 4-Stage Counter Shift Register
July 1992
100336 Power 4-Stage Counter Shift Register
100336 operates either modulo-16 down counter 4-bit bidirectional shift register Three Select (Sn) inputs determine mode operation shown Function Select table Count Enable (CEP CET) inputs provided ease cascading multistage counters Count Enable (CET) input also doubles Serial Data (D0) input shift-up operation shift-down operation Serial Data input counting operations Terminal Count (TC) output goes when counter reaches count mode (zero) count down mode shift modes output repeats output dual nature this output input means that interconnection from stage next higher stage serves link multistage counting shift-up operation individual Preset (Pn) inputs used enter data parallel preset counter programmable counter applications HIGH signal Master Reset (MR) input overrides other inputs asynchronously clears flip-flops addition synchronous clear provided well complement function which synchronously inverts contents flip-flops inputs have pull-down resistors
Features
power reduction 100136 2000V protection function compatible with 100136 Voltage compensated operating range Available industrial grade temperature range Available MIL-STD-883
Logic Symbol
Names Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs
10584
Connection Diagrams
24-Pin SOIC 28-Pin 24-Pin Quad Cerpak
10584 10584-2
10584
C1995 National Semiconductor Corporation
10584
RRD-B30M105 Printed
Logic Diagram
10584
Function Select Table Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Hold
Truth Table
Inputs
Outputs
LLLL HHHH
Mode Preset (Parallel Load) Invert Shift Shift Count Down Count Down with active Count Down with active Clear Count Count with active Count with active Hold
(Q0- minus
(Q0- plus
Asynchronous Master Reset
LLLL HHHH
Before clock After clock
HIGH Voltage Level Voltage Level Don't Care
LOW-to-HIGH Transition
Absolute Maximum Ratings
Above which useful life impaired (Note Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Potential Ground Input Voltage (DC) Output Current Output HIGH) (Note
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE)
2000V
Note Absolute maximum ratings those values beyond which device damaged have useful life impaired Functional operation under these conditions implied Note testing conforms MIL-STD-883 Method 3015
Commercial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1165 1830
1025 1830 1035
1705
1620
Units
Conditions (Max) (Min) VIH(Min) (Max) Loading with Loading with
1610 1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Commercial Version (Continued) Characteristics
VCCA Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL Parameter Shift Frequency Propagation Delay Propagation Delay (Shift) Propagation Delay (Count) Propagation Delay Propagation Delay (Count) Propagation Delay (Shift) Propagation Delay Propagation Delay Transition Time Setup Time (Release Time) Hold Time Pulse Width HIGH Units Conditions
Figures Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note
Figures
Figures
Figure
tpw(H)
Figures
Note propagation delay specified single output switching Delays vary with multiple outputs switching
Commercial Version (Continued) SOIC Cerpak Electrical Characteristics
VCCA Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL Parameter Shift Frequency Propagation Delay Propagation Delay (Shift) Propagation Delay (Count) Propagation Delay Propagation Delay (Count) Propagation Delay (Shift) Propagation Delay Propagation Delay Transition Time Setup Time (Release Time) Hold Time Pulse Width HIGH Maximum Skew Common Edge Output-to-Output Variation Clock Output Path Maximum Skew Common Edge Output-to-Output Variation Clock Output Path Maximum Skew Opposite Edge Output-to-Output Variation Clock Output Path Maximum Skew (Signal) Transition Variation Clock Output Path Units Conditions
Figures Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note
Figures
Figures
Figure
tpw(H) tOSHL
Figures
Only (Note Only (Note Only (Note Only (Note
tOSLH
tOST
Note Output-to-Output Skew defined absolute value difference between actual propagation delay outputs within same packaged device specifications apply outputs switching same direction either HIGH (tOSHL) HIGH (tOSLH) opposite directions both (tOST) Parameters tOST guaranteed design Note propagation delay specified single output switching Delays vary with multiple outputs switching
Industrial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1170 1830
1085 1830 1095 1565 1480
1025 1830 1035 1610 1165 1830 1475
1575
1620
Units
Conditions (Max) (Min) VIH(Min) (Max) Loading with Loading with
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Industrial Version (Continued) Electrical Characteristics
VCCA Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL Parameter Shift Frequency Propagation Delay Propagation Delay (Shift) Propagation Delay (Count) Propagation Delay Propagation Delay (Count) Propagation Delay (Shift) Propagation Delay Propagation Delay Transition Time Setup Time (Release Time) Hold Time Pulse Width HIGH Units Conditions
Figures Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note Figures (Note
Figures
Figure
Figure
tpw(H)
Figures
Note propagation delay specified single output switching Delays vary with multiple outputs switching
Military Version Electrical Characteristics
VCCA Symbol Parameter Output HIGH Voltage
1025 1085
1620 1555
Units
Conditions
Notes
(Max) (Min)
Loading with
Output Voltage
1830 1830
VOHC
Output HIGH Voltage
1035 1085
(Min) (Max)
Loading with
VOLC
Output Voltage
1610 1555
Input HIGH Voltage Input Voltage Input Current Input HIGH Current
1165 1830
1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) VIH(Max) Inputs Open
Power Supply Current
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately without allowing junction temperature stablize heat dissipation after power-up This provides ``cold start'' specs which considered worst case condition cold temperatures Note Screen tested 100% each device Subgroups Note Sample tested (Method 5005 Table each manufactured Subgroups Note Guaranteed applying specified input conditon testing
Military Version (Continued) Characteristics
VCCA Symbol fshift tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL Parameter Shift Frequency Propagation Delay Propagation Delay (Shift) Propagation Delay (Count) Propagation Delay Propagation Delay (Count) Propagation Delay (Shift) Propagation Delay Propagation Delay Transition Time Setup Time (Release Time) Hold Time Pulse Width HIGH Figures Units Conditions Notes
Figures
Figures Figures Figures
Figures Figures
Figures
Figures
Figure
Figure
tpw(H)
Figures
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately after power-up This provides ``cold start'' specs which considered worst case condition cold tempertures Note Screen tested 100% each device temperature only Subgroups Note Sample tested (Method 5005 Table each manufactured Subgroups temperatures Subgroups Note tested temperature (design characterization data) Note propagation delay specified single output switching Delays vary with multiple outputs switching
Test Circuitry
Notes VCCA equal length impedance lines terminator internal scope Decoupling from unused outputs loaded with Fixture stray capacitance numbers shown flatpak logic symbol
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FIGURE Test Circuit
10584
FIGURE Shift Frequency Test Circuit (Shift Left)
Notes shift right mode applied feedback path from output input should short possible
Switching Waveforms
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FIGURE Propagation Delay (Clock) Transition Times
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FIGURE Propagation Delay (Reset)
Switching Waveforms (Continued)
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FIGURE Propagation Delay (Serial Data Selects)
10584
Notes minimum time before transition clock that information must present data input minimum time after transition clock that information must remain unchanged data input
FIGURE Setup Hold Time
10584
Note Shift Right Mode
FIGURE Propagation Delay Clock Terminal Count (Shift Right Mode)
Switching Waveforms (Continued)
Note Shift Left Mode
10584
FIGURE Propagation Delay Clock Terminal Count (Shift Left Mode)
10584
Note Decimal representation binary outputs Count Count Down Measurement taken point waveform
FIGURE Propagation Delay Clock Terminal Count (Count Count Down Modes)
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Note Shift Right Mode
FIGURE Propagation Delay Master Reset Terminal Count (Shift Right Mode)
Switching Waveforms (Continued)
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Note Shift Left Mode
FIGURE Propagation Delay Master Reset Terminal Count (Shift Left Mode)
10584
Note Decimal representation binary outputs Count Mode
10584
Note Decimal representation binary outputs Count Down Mode
FIGURE Propagation Delay Master Reset Terminal Count (Count Count Down Modes)
Applications
3-Stage Divider Preset Count Down Mode
Note then
10584
Slow Expansion Scheme
10584
Fast Expansion Scheme
10584
Ordering Information
device number used form part simplified purchasing code where package type temperature range defined follows 100336 Device Number (Basic) Package Code Ceramic Quad Cerpak Plastic Plastic Leaded Chip Carrier (PCC) Small Outline (SOIC) Special Variation Military grade device with environmental burn-in processing Temperature Range Commercial Industrial (b40 (PCC only) Military (b55
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package Wide) Package Number J24E
24-Lead Molded Package Wide) Package Number M24B
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package Package Number N24E
Package Number V28A
28-Lead Plastic Chip Carrier
OVERFLOW DATA THIS PAGE
100336 Power 4-Stage Counter Shift Register
Physical Dimensions inches (millimeters) (Continued)
114913
24-Lead Quad Cerpak Package Number W24B
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