July 1992 100331 Power Triple Flip-Flop 100331 contains thre
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100331 Power Triple Flip-Flop
July 1992
100331 Power Triple Flip-Flop
100331 contains three D-type edge-triggered master slave flip-flops with true complement outputs Common Clock (CPC) Master (MS) Master Reset (MR) inputs Each flip-flop individual Clock (CPn) Direct (SDn) Direct Clear (CDn) inputs Data enters master when both transfers slave when both) HIGH Master Master Reset individual inputs override Clock inputs inputs have pull-down resistors
Features
power reduction 100131 2000V protection function compatible with 100131 Voltage compensated operating range Available industrial grade temperature range Available MIL-STD-883
Logic Symbol
Names -CP2 -CD2 Q0-Q2
10262
Description Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Inputs Master Reset Input Master Input Data Outputs Complementary Data Outputs
Connection Diagrams
24-Pin SOIC 28-Pin 24-Pin Quad Cerpak
10262
10262-2
10262
C1995 National Semiconductor Corporation
10262
RRD-B30M105 Printed
Logic Diagram
10262
Truth Tables (Each Flip-Flop)
Synchronous Operation Inputs Outputs Qn(t Qn(t) Qn(t) Qn(t) Asynchronous Operation Inputs Outputs Qn(t
HIGH Voltage Level Voltage Level Don't Care Undefined Time before Positive Transition Time after Positive Transition HIGH Transition
Absolute Maximum Ratings
Above which useful life impaired (Note Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Potential Ground (VEE) Input Voltage (DC) Output Current Output HIGH) (Note
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE)
2000V
Note Absolute maximum ratings those values beyond which device damaged have useful life impaired Functional operation under these conditions implied Note testing conforms MIL-STD-883 Method 3015
Commercial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1165 1830
1025 1830 1035
1705
1620
Units
Conditions (Max) (Min) (Min) (Max) Loading with Loading with
1610 1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Commercial Version (Continued) Electrical Characteristics
VCCA (Continued) Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Transition Time Setup Time (Release Time) (Release Time) Hold Time Pulse Width HIGH Propagation Delay Output Parameter Toggle Frequency Propagation Delay Output Propagation Delay Output Propagation Delay Output Units Conditions
Figures Figures
Figures
Figures Figure
Figure
tpw(H)
Figure Figures
SOIC Cerpak Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Output Parameter Toggle Frequency Propagation Delay Output Propagation Delay Output Propagation Delay Output Units Conditions
Figures Figures
Figures
Commercial Version (Continued) SOIC Cerpak Electrical Characteristics
VCCA (Continued) Symbol tTLH tTHL Parameter Transition Time Setup Time (Release Time) (Release Time) Hold Time Pulse Width HIGH Propagation Delay Output Propagation Delay Output Propagation Delay Output Propagation Delay Output Maximum Skew Common Edge Output-to-Output Variation Common Clock Output Path Maximum Skew Common Edge Output-to-Output Variation Output Path Maximum Skew Common Edge Output-to-Output Variation Common Clock Output Path Maximum Skew Common Edge Output-to-Output Variation Output Path Maximum Skew Opposite Edge Output-to-Output Variation Common Clock Output Path Maximum Skew Opposite Edge Output-to-Output Variation Output Path Maximum Skew (Signal) Transition Variation Common Clock Output Path Maximum Skew (Signal) Transition Variation Output Path Units Conditions
Figures Figure
Figure
tpw(H)
Figure Figures
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tOSHL
Figures Only
Only Only Only Only Only (Note Only (Note Only (Note Only (Note Only (Note Only (Note Only (Note Only (Note
Figures
tOSHL
tOSLH
tOSLH
tOST
tOST
Note Output-to-Output Skew defined absolute value difference between actual propagation delay outputs within same packaged device specifications apply outputs switching same direction either HIGH (tOSHL) HIGH (tOSLH) opposite directions both (tOST) Parameters tOST guaranteed design
Industrial Version Electrical Characteristics
VCCA (Note) Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1170 1830
1085 1830 1095 1565 1480
1025 1830 1035 1610 1165 1830
Units
Conditions (Max) (Min) (Min) (Max) Loading with Loading with
1575
1620
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
1475
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Transition Time Setup Time (Release Time) (Release Time) Hold Time Pulse Width HIGH Propagation Delay Output Parameter Toggle Frequency Propagation Delay Output Propagation Delay Output Propagation Delay Output Units Conditions
Figures
Figures
Figures
Figures Figure
Figure
tpw(H)
Figure Figures
Military Version Electrical Characteristics
VCCA Symbol Parameter Output HIGH Voltage
1025 1085
1620 1555
Units
Conditions
Notes
Output Voltage
1830 1830
(Max) (Min)
Loading with
VOHC
Output HIGH Voltage
1035 1085
VOLC
Output Voltage
1610 1555
(Min) (Max)
Loading with
Input HIGH Voltage Input Voltage Input Current Input HIGH Current
1165 1830
1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Power Supply Current
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately without allowing junction temperature stabilize heat dissipation after power-up This provides ``cold start'' specs which considered worst case condition cold temperatures Note Screen tested 100% each device Subgroups Note Sampled tested (Method 5005 Table each manufactured Subgroups Note Guaranteed applying specified input condition testing
Military Version (Continued) Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL Transition Time Setup Time (Release Time) (Release Time) Hold Time Pulse Width HIGH Propagation Delay Output Parameter Toggle Frequency Propagation Delay Output Propagation Delay Output Propagation Delay Output Figures Units Conditions Notes
Figures
Figures
Figures Figure
Figure
tpw(H)
Figure Figures
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately without allowing junction temperature stabilize heat dissipation after power-up This provides ``cold start'' specs which considered worst case condition cold temperatures Note Screen tested 100% each device Temperature only Subgroup Note Sample tested (Method 5005 Table each Subgroup Temp Subgroups Note tested Temperature (design characterization data)
Test Circuits
10262
FIGURE Test Circuit
10262
FIGURE Toggle Frequency Test Circuit
Notes VCCA Equal length impedance lines terminator internal scope Decoupling from unused outputs loaded with Fixture stray capacitance
Switching Waveforms
10262
FIGURE Propagation Delay (Clock) Transition Times
10262
FIGURE Propagation Delay (Resets)
10262
FIGURE Data Setup Hold Time
Note minimum time before transition clock that information must present data input Note minimum time after transition clock that information must remain unchanged data input
Ordering Information
device number used form part simplified purchasing code where package type temperature range defined follows 100331 Device Type (Basic) Package Code Ceramic Quad Cerpak Plastic Leaded Chip Carrier (PCC) Plastic Small Outline (SOIC) Special Variation Military grade device with environmental burn-in processing Temperature Range Commercial Industrial (b40 (PCC Only) Military (b55
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package Wide) Package Number J24E
24-Lead Molded Package Wide) Package Number M24B
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package Package Number N24E
28-Lead Plastic Chip Carrier Package Number V28A
100331 Power Triple Flip-Flop
Physical Dimensions inches (millimeters) (Continued)
114912
24-Lead Quad Cerpak Package Number W24B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications
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