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100351 Low Power Hex D Flip-Flop

July 1992

100351 Low Power Hex D Flip-Flop
July 1992
100351 Low Power Hex D Flip-Flop
General Description
The 100351 contains six D-type edge-triggered master slave flip-flops with true and complement outputs a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH The MR input overrides all other inputs and makes the Q outputs LOW All inputs have 50 kX pulldown resistors
Features
Logic Symbol
Pin Names D0 -D5 CPa CPb MR Q0 -Q5 Q0 -Q5
Description Data Inputs Common Clock Inputs Asynchronous Master Reset Input Data Outputs Complementary Data Outputs
Connection Diagrams
24-Pin DIP SOIC 28-Pin PCC 24-Pin Quad Cerpak
TL F 9885-1
C1995 National Semiconductor Corporation
TL F 9885
RRD-B30M115 Printed in U S A
Logic Diagram
Truth Tables (Each Flip-flop)
Synchronous Operation Inputs Dn L H L H X X X CPa L L L L H L L CPb L L L L L H L MR L L L L L L L Outputs Qn(t a 1) L H L H Qn(t) Qn(t) Qn(t) Dn X CPa X Asynchronous Operation Inputs CPb X MR H Outputs Qn(t a 1) L
Absolute Maximum Ratings
Above which the useful life may be impaired (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2)
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE) 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C
Note 1 Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 ESD testing conforms to MIL-STD-883 Method 3015
Commercial Version DC Electrical Characteristics
VEE e b4 2V to b5 7V VCC e VCCA e GND TC e 0 C to a 85 C (Note 3) Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current MR D 0 - D5 CPa CPb Power Supply Current
b 129 b 1165 b 1830
b 1025 b 1830 b 1035
b 955 b 1705
b 870 b 1620
Units mV mV
Conditions VIN e VIH (Max) or VIL (Min) VIN e VIH (Min) or VIL (Max) Loading with 50X to b2 0V Loading with 50X to b2 0V
b 1610 b 870 b 1475
Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN e VIL (Min)
VIN e VIH (Max) Inputs Open
DIP AC Electrical Characteristics
Figures 2 and 3 Figures 1 and 3 Figures 1 and 4 Figures 1 and 3
Commercial Version (Continued) DIP AC Electrical Characteristics (Continued)
VEE e b4 2V to b5 7V VCC e VCCA e GND Symbol tS Parameter Setup Time D0 - D5 MR (Release Time) Hold Time D0 - D5 Pulse Width HIGH CPa CPb MR TC e 0 C Min 0 40 1 60 0 80 2 00 Max TC e a 25 C Min 0 40 1 60 0 80 2 00 Max TC e a 85 C Min 0 40 1 60 0 80 2 00 Max Units Conditions
Figure 5
Figure 4
Figure 5 Figures 3 and 4
tpw(H)
SOIC PCC and Cerpak AC Electrical Characteristics
Figures 2 and 3 Figures 1 and 3 Figures 1 and 4 Figures 1 and 3 Figure 5
Figure 4
Figure 5 Figures 3 and 4
PCC only (Note 1) PCC only (Note 1) PCC only (Note 1) PCC only (Note 1)
tpw(H) tOSHL
tOSLH
Note 1 Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both HL and LH (tOST) Parameters tOST and tPS guaranteed by design
Industrial Version PCC DC Electrical Characteristics
VEE e b4 2V to b5 7V VCC e VCCA e GND TC e 0 C to a 85 C (Note 1) Symbol VOH VOL VOHC VOLC VIH VIL IIL IIH Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current MR D0 - D5 CPa CPb Power Supply Current
b 129 b 1170 b 1830
b 1085 b 1830 b 1095 b 1565 b 870 b 1480
b 1025 b 1830 b 1035 b 1610 b 1165 b 1830 b 870 b 1475
Units
Conditions VIN e VIH (Max) or VIL (Min) VIN e VIH (Min) or VIL (Max) Loading with 50X to b2 0V Loading with 50X to b2 0V
b 870 b 1575
b 870 b 1620
Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN e VIL (Min)
VIN e VIH (Max) Inputs Open
PCC AC Electrical Characteristics
Figures 2 and 3 Figures 1 and 3 Figures 1 and 4 Figures 1 and 3 Figure 5
Figure 4
Figure 5 Figures 3 and 4
tpw(H)
Military Version
Preliminary
DC Electrical Characteristics
VEE e b4 2V to b5 7V VCC e VCCA e GND TC e b55 C to a 125 C Symbol VOH Parameter Output HIGH Voltage Min
b 1025 b 1085
b 870 b 870 b 1620 b 1555
Units mV mV mV mV mV mV
Conditions
Notes
Output LOW Voltage
b 1830 b 1830
VIN e VIH (Max) or VIL (Min)
Loading with 50X to b2 0V
Output HIGH Voltage
b 1035 b 1085
Output LOW Voltage
b 1610 b 1555
VIN e VIH (Min) or VIL (Max)
Loading with 50X to b2 0V
VIH VIL IIL IIH
Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current CP MR D 0 - D5 CP MR D0 - D5
b 1165 b 1830
b 870 b 1475
Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VEE e b4 2V VIN e VIL (Min)
VEE e b5 7V VIN e VIH (Max)
Power Supply Current
Inputs Open
Military Version Preliminary (Continued) AC Electrical Characteristics
Figures 2 and 3 Figures 1 and 3
Figures 1 and 4 Figures 1 and 3 Figure 5
Figure 4 Figure 5 Figures 3 and 4
tpw(H)
Test Circuitry
Notes VCC VCCA e a 2V VEE e b 2 5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0 1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF
FIGURE 1 AC Test Circuit
Notes VCC VCCA e a 2V VEE e b 2 5V L1 and L2 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0 1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Jig and stray capacitance s 3 pF
FIGURE 2 Toggle Frequency Test Circuit
Switching Waveforms
FIGURE 3 Propagation Delay (Clock) and Transition Times
FIGURE 4 Propagation Delay (Reset)
Notes ts is the minimum time before the transition of the clock that information must be present at the data input th is the minimum time after the transition of the clock that information must remain unchanged at the data input
FIGURE 5 Setup and Hold Time
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows 100351 Device Type (Basic) Package Code D e Ceramic DIP F e Flatpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) S e Small Outline (SOIC) D C QB Special Variation QB e Military grade device with environmental processing shipped in tubes Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC only) M e Military (b55 C to a 125 C)
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (0 400 Wide) (D) NS Package Number J24E
24-Lead Molded Package (0 300 Wide) (S) NS Package Number M24B
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E
NS Package Number V28A
28-Lead Plastic Chip Carrier (Q) 11
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100351 Low Power Hex D Flip-Flop
Physical Dimensions inches (millimeters) (Continued)
24-Lead Quad Cerpak (F) NS Package Number W24B
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018
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