July 1992 100353 Power 8-Bit Register 100353 contains eight

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July 1992 100353 Power 8-Bit Register 100353 contains eight

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100353 Power 8-Bit Register
July 1992
100353 Power 8-Bit Register
100353 contains eight D-type edge triggered master slave flip-flops with individual inputs (Dn) true outputs (Qn) clock input (CP) common clock enable (CEN) Data enters master when transfers slave when goes HIGH When input goes HIGH overrides other inputs disables clock outputs maintain last state 100353 output drivers designed drive termination inputs have pull-down resistors
Features
power operation 2000V protection Voltage compensated operating range Available industrial grade temperature range
Logic Symbol
Names
9882
Description Data Inputs Clock Enable Input Clock Input (Active Rising Edge) Data Outputs Connect
Connection Diagrams
24-Pin 28-Pin 24-Pin Quad Cerpak
9882
9882
9882-1
C1995 National Semiconductor Corporation
9882
RRD-B30M115 Printed
Logic Diagram
9882
Truth Table
Inputs Outputs
HIGH Voltage Level Voltage Level Don't Care Change HIGH Transition
Absolute Maximum Ratings
Above which useful life impared (Note Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Potential Ground Input Voltage (DC) Output Current Output HIGH) (Note
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE)
2000V
Note Absolute maximum ratings those values beyond which device damaged have useful life impaired Functional operation under these conditions implied Note testing conforms MIL-STD-883 Method 3015
Commercial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1165 1830
1025 1830 1035
1705
1620
Units
Conditions (Max) (Min) (Min) (Max) Loading with Loading with
1610 1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) VIH(Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Electrical Characteristics
Symbol fmax tPLH tPHL tTLH tTHL Parameter Toggle Frequency Propagation Delay Output Transition Time Setup Time (Disable Time) (Release Time) Hold Time Pulse Width HIGH
VCCA Units Conditions
Figures Figures (Note Figures
Figures
tpw(H)
Figures Figures
Note propagation delay specified single output switching Delays vary with multiple outputs switching
Commercial Version (Continued) Cerpack Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Toggle Frequency Propagation Delay Output Transition Time Setup Time (Disable Time) (Release Time) Hold Time Pulse Width HIGH Units Conditions
Figures Figures (Note Figures
Figures Figures Figures
Only (Note Only (Note Only (Note Only (Note
tpw(H) tOSHL
Maximum Skew Common Edge Output-to-Output Variation Data Output Path Maximum Skew Common Edge Output-to-Output Variation Data Output Path Maximum Skew Opposite Edge Output-to-Output Variation Data Output Path Maximum Skew (Signal) Transition Variation Data Output Path
tOSLH
tOST
Note Output-to-Output Skew defined absolute value difference between actual propagation delay outputs within same packaged device specifications apply outputs switching same direction either HIGH (tOSHL) HIGH (tOSLH) opposite directions both (tOST) Parameters tOST guaranteed design Note propagation delay specified single output switching Delays vary with multiple outputs switching
Industrial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1170 1830
1085 1830 1095 1565 1480
1025 1830 1035 1610 1165 1830 1475
Units
Conditions (Max) (Min) (Min) (Max) Loading with Loading with
1575
1620
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Toggle Frequency Propagation Delay Output Transition Time Setup Time (Disable Time) (Release Time) Hold Time Pulse Width HIGH Units Conditions
Figures Figures (Note Figures
Figures Figures Figures
tpw(H)
Note propagation delay specified single output switching Delays vary with multiple outputs switching
Military Version
Preliminary
Electrical Characteristics
VCCA Symbol Parameter Output HIGH Voltage
1025 1085
1620 1555
Units
Conditions
Notes
Output Voltage
1830 1830
(Max) (Min)
Loading with
VOHC
Output HIGH Voltage
1035 1085
VOLC
Output Voltage
1610 1555
(Min) (Max)
Loading with
Input HIGH Voltage Input Voltage Input Current Input HIGH Current
1165 1830
1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Power Supply Current
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately without allowing junction temperature stabilize heat dissipation after power-up This provides ``cold start'' specs which considered worst case condition cold temperatures Note Screen tested 100% each device Subgroups Note Sample tested (Method 5005 Table each manufactured Subgroups Note Guaranteed applying specified input condition testing
Military Version
Preliminary (Continued)
Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Toggle Frequency Propagation Delay Output Transition Time Setup Time (Disable Time) (Release Time) Hold Time Pulse Width HIGH Units Conditions Notes
Figures
Figures
Figures Figures Figures
tpw(H)
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately after power-up This provides ``cold start'' specs which considered worst case condition cold temperatures Note Screen tested 100% each device temperature only Subgroup Note Sample tested (Method 5005 Table each manufactured Subgroup temperatures Subgroups Note tested temperature (design characterization data) Note propagation delay specified single output switching Delays vary with multiple outputs switching
Test Circuitry
9882
Notes VCCA equal length impedance lines terminator internal scope Decoupling from unused outputs loaded with Fixture stray capacitance
FIGURE Toggle Frequency Test Circuit
Switching Waveforms
9882
FIGURE Propagation Delay (Clock) Transition Times
Switching Waveforms (Continued)
9882
FIGURE Setup Pulse Width Times
9882
FIGURE Data Setup Hold Time
Note minimum time before transition clock that information must present data input Note minimum time after transition clock that information must remain unchanged data input
Ordering Information
device number used form part simplified purchasing code where package type temperature range defined follows 100353 Device Type (Basic) Package Code Ceramic Quad Cerpak Plastic Leaded Chip Carrier (PCC) Plastic Special Variations Military grade device with environmental burn-in processing Temperature Range Commercial Industrial (b40 (PCC only) Military (b55
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package Wide) Package Number J24E
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package Package Number N24E
Package Number V28A
28-Lead Plastic Chip Carrier
OVERFLOW DATA THIS PAGE
100353 Power 8-Bit Register
Physical Dimensions inches (millimeters) (Continued)
114921
Lead Quad Cerpak Package Number W24B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

July 1992 100353 Power 8-Bit Register 100353 contains eight

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