July 1992 100341 Power 8-Bit Shift Register 100341 contains

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July 1992 100341 Power 8-Bit Shift Register 100341 contains

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100341 Power 8-Bit Shift Register
July 1992
100341 Power 8-Bit Shift Register
100341 contains eight edge-triggered D-type flip-flops with individual inputs (Pn) outputs (Qn) parallel operation with serial inputs (Dn) steering logic bidirectional shifting flip-flops accept input data setup time before positive-going transition clock pulse their outputs respond propagation delay after this rising clock edge circuit operating mode determined Select inputs which internally decoded select either ``parallel entry'' ``hold'' ``shift left'' ``shift right'' described Truth Table inputs have pull-down resistors
Features
power reduction 100141 2000V protection function compatible with 100141 Voltage compensated operating range Available industrial grade temperature range
Logic Symbol
Names
9880
Description Clock Input Select Inputs Serial Inputs Parallel Inputs Data Outputs
Connection Diagrams
24-Pin SOIC 28-Pin 24-Pin Quad Cerpak
9880
9880
9880-2
C1995 National Semiconductor Corporation
9880
RRD-B30M115 Printed
Logic Diagram
9880
Truth Table
Function Load Register Shift Left Shift Left Shift Right Shift Right Hold Hold Hold
HIGH Voltage Level Voltage Level Don't Care LOW-to-HIGH Transition
Inputs
Outputs
Change
Absolute Maximum Ratings
Above which useful life impaired (Note Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic Potential Ground Input Voltage (DC) Output Current Output HIGH) (Note
Recommended Operating Conditions
Case Temperature (TC) Commercial Industrial Military Supply Voltage (VEE)
2000V
Note Absolute maximum ratings those values beyond which device damaged have useful life impaired Functional operation under these conditions implied Note testing conforms MIL-STD-883 Method 3015
Commercial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1165 1830
1025 1830 1035
1705
1620
Units
Conditions (Max) (Min) (Min) (Max) Loading with Loading with
1610 1475
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Commercial Version (Continued) Electrical Characteristics
Symbol fmax tPLH tPHL tTLH tTHL Parameter Clock Frequency Propagation Delay Output Transition Time Setup Time Hold tpw(H) Pulse Width HIGH VCCA Units Conditions
Figures Figures (Note Figures
Figure
Figure
Note propagation delay specified switching single output Delays vary multiple outputs switching simultaneously
SOIC Cerpak Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Clock Frequency Propagation Delay Output Transition Time Setup Time Hold Time tpw(H) tOSHL Pulse Width HIGH Units Conditions
Figures Figures (Note Figures
Figure
Figure
Only (Note Only (Note Only (Note Only (Note
Maximum Skew Common Edge Output-to-Output Variation Clock Output Path Maximum Skew Common Edge Output-to-Output Variation Clock Output Path Maximum Skew Opposite Edge Output-to-Output Variation Clock Output Path Maximum Skew (Signal) Transition Variation Clock Output Path
tOSLH
tOST
Note Output-to-Output Skew defined absolute value difference between actual propagation delay outputs within same packaged device specifications apply outputs switching same direction either HIGH (tOSHL) HIGH (tOSLH) opposite directions both (tOST) Parameters tOST guaranteed design Note propagation delay specified switching single output Delays vary multiple outputs switching simultaneously
Industrial Version Electrical Characteristics
VCCA (Note Symbol VOHC VOLC Parameter Output HIGH Voltage Output Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Current Input HIGH Current Power Supply Current
1170 1830
1085 1830 1095 1565 1480
1025 1830 1035 1610 1165 1830 1475
Units
Conditions VIH(Max) (Min) (Min) (Max) Loading with Loading with
1575
1620
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
Note specified limits represent ``worst case'' value parameter Since these values normally occur temperature extremes additional noise immunity guardbanding achieved decreasing allowable system operating ranges Conditions testing shown tables chosen guarantee operation under ``worst case'' conditions
Industrial Version (Continued) Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Clock Frequency Propagation Delay Output Transition Time Setup Time Hold Time tpw(H) Pulse Width HIGH Units Conditions
Figures Figures (Note Figures
Figure
Figure
Note propagation delay specified switching single output Delays vary multiple outputs switching simultaneously
Military Version Electrical Characteristics
VCCA Symbol Parameter Output HIGH Voltage
1025 1085
Units
Conditions
Notes
Output Voltage
1830 1620 1830 1555
(Max) (Min)
Loading with
VOHC
Output HIGH Voltage
1035 1085
VOLC
Output Voltage
1610 1555
(Min) (Max)
Loading with
Input HIGH Voltage Input Current Input Current Input High Current
1165
Guaranteed HIGH Signal Inputs Guaranteed Signal Inputs (Min) (Max) Inputs Open
1830 1475
Power Supply Current
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately without allowing junction temperature stabilize heat dissipation after power-up This provides ``cold start'' specifications which considered worst case condition cold temperatures Note Screen tested 100% each device Subgroups Note Sample tested (Method 5005 Table each manufactured Subgroups Note Guaranteed applying specified input condition testing
Military Version (Continued) Electrical Characteristics
VCCA Symbol fmax tPLH tPHL tTLH tTHL Parameter Clock Frequency Propagation Delay Output Transition Time Setup Time Hold Time tpw(H) Pulse Width HIGH Units Conditions Notes
Figures
Figures
Figure
Figure
Note F100K Series cold temperature testing performed temperature soaking guarantee junction temperature equals then testing immediately after power-up This provides ``cold start'' specifications which considered worst case condition cold temperatures Note Screen tested 100% each device temperature only Subgroup Note Sample tested (Method 5005 Table each manufactured Subgroup temperatures Subgroups Note tested temperature (design characterization data) Note propagation delay specified switching single output Delays vary multiple outputs switching simultaneously
Test Circuitry
Notes VCCA equal length impedance lines terminator internal scope Decoupling from unused outputs loaded with Fixture stray capacitance numbers shown Flatpak logic symbol
9880
FIGURE Test Circuit
Notes shift right mode pulse generator connected moved Pulse generator connected frequency duty cycle which allows occasional parallel load feedback path from output input should short possible
9880
FIGURE Shift Frequency Test Circuit (Shift Left)
Switching Waveforms
9880
FIGURE Propagation Delay Transition Times
Notes minimum time before transition clock that information must present data input minimum time after transition clock that information must remain unchanged data input
9880
FIGURE Setup Hold Times
Ordering Information
device number used form part simplified purchasing code where package type temperature range defined follows 100341 Device Type (Basic) Package Code Ceramic Quad Cerpak Plastic Plastic Leaded Chip Carrier (PCC) Small Outline (SOIC) Special Variation Military grade device with environmental burn-in processing Temperature Range Commercial Industrial (b40 (PCC only) Military (b55
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package Wide) Package Number J24E
24-Lead Molded Package Wide) Package Number M24B
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package Package Number N24E
Package Number V28A
28-Lead Plastic Chip Carrier
OVERFLOW DATA THIS PAGE
100341 Power 8-Bit Shift Register
Physical Dimensions inches (millimeters) (Continued)
114915
24-Lead Quad Cerpak Package Number W24B
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

July 1992 100341 Power 8-Bit Shift Register 100341 contains

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