August 1989 DP8417 NS32817 8418 32818 8419 32819 8419X 32819X 256
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DP8417 NS32817 8418 32818 8419 32819 8419X 32819X 256k Dynamic Controller Drivers
August 1989
DP8417 NS32817 8418 32818 8419 32819 8419X 32819X 256k Dynamic Controller Drivers
General Description
DP8417 8418 8419 8419X represent family 256k DRAM Controller Drivers which designed provide ``No-Waitstate'' interface Dynamic arrays Mbytes larger Each device offers slight functional variations DP8419 design which tailored different system requirements family members fabricated using National's oxide isolated Advanced power Schottky (ALS) process design techniques which enable them significantly out-perform other discrete alternatives speed level integration power consumption Each device integrates following critical 256k DRAM controller functions single monolithic device ultra precise delay line 9-bit refresh counter fall-through column bank select input latches Column address muxing logic on-board high capacitive-load Write Enable Address output drivers precise control signal timing above There four device options basic DP8419 Controller DP8417 function compatible with DP8419 except that outputs TRI-STATE DP8418 changes specifically designed offer optimum interface microprocessors DP8419X functionally identical DP8419 available 52-pin package which upward compatible with National's DP8429D Mbit DRAM Controller Driver Each device available plastic Ceramic Plastic Chip Carrier (PCC) packaging (Continued)
TRI-STATE registered trademark National Semiconductor Corp registered trademark used under license with Monolithic Memories
Operational Features
Makes DRAM Interface refresh tasks appear virtually transparent making DRAMs easy static RAMs Specifically designed eliminate wait states beyond Eliminates components significant board real estate reduction system power savings elimination chip-to-chip skewing On-board ultra precise delay line On-board high capacitive address drivers (specified driving DRAMs directly) specified directly addressing Megabytes power high speed bipolar oxide isolated process Upward function compatible with DP8428 DP8429 Mbit DRAM controller drivers Downward function compatible with DP8408A DP8409A 256k DRAM controller drivers user selectable modes operation Access Refresh automatic external)
Contents
System Device Block Diagrams Recommended Companion Components Device Connection Diagrams Definitions Family Device Differences (DP8419 DP8409A 8417 8418 8419X) Mode Operation (Descriptions Timing Diagrams) Application Description Diagrams Electrical Specifications Timing Diagrams Test Conditions
System Diagram
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C1995 National Semiconductor Corporation
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RRD-B30M105 Printed
General Description (Continued)
order specify each device ``true'' worst case operating conditions timing parameters guaranteed while chip driving capacitive load DRAMs including trace capacitance chip's delay timing logic makes patented delay line technique which keeps skew over full range temperature range DP8417 DP8418 DP8419 DP8419X guarantee maximum RASIN CASOUT delay even while driving Mbyte memory array with error correction check bits included Speed selected options these devices shown switching characteristics section this document With four independent outputs nine multiplexed address outputs DP8419 support four banks 256k DRAMs bank select pins decoded activate signals during access leaving three non-selected banks standby mode (less than tenth operating power) with data outputs TRI-STATE DP8419 mode-select pins allowing refresh modes access modes Refresh access timing controlled either externally automatically automatic modes require minimum input control signals refresh counter on-chip multiplexed with column inputs contents appear address outputs DP8419 during refresh incremented completion refresh Column bank address latches also on-chip However address inputs DP8419 valid throughout duration access these latches operated fallthrough mode
System Companion Components Device DP84300 DP84412 DP84512 DP84322 DP84422 DP84522 DP84432 DP84532 DP8400-2 DP8400-4 DP8402A Function Programmable Refresh Timer DP84xx DRAM Controller NS32008 DP8409A Interface NS32332 DP8417 Interface 68000 DP8409A Interface MHz) 68000 DP8409A Interface MHz) 68020 DP8417 Interface 8086 DP8409A Interface 80286 DP8409A Interface 16-bit Expandable Error Checker Corrector 16-bit Expandable Error Checker Corrector 32-bit Error Detector Corrector (EDAC)
Block Diagrams
DP8417 8419 8419X
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DP8418
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Connection Diagrams (Dual-In-Line Package)
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Order Number DP8417D-70 DP8417D-80 DP8417N-70 DP8417N-80 DP8418D-70 DP8418D-80 DP8418N-70 DP8418N-80 DP8419D-70 DP8419D-80 DP8419N-70 DP8419N-80 DP8419XD-70 DP8419XD-80 Package Number D48A D52A N48A
Connection Diagrams (Continued)
Plastic Chip Carrier Package
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Plastic Chip Carrier Package
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Order Number DP8417V-70 DP8417V-80 DP8418V-70 DP8418V-80 DP8419V-70 DP8419V-80 Package Number V68A
Family Device Differences
DP8417 DP8419 DP8417 identical DP8419 with exception that (Multiplexed Address) outputs TRI-STATE when (Chip Select) high chip refresh mode This feature allows access same DRAM array through multiple DRAM Controller Driver DP8417s specifications same DP8419 except tCSRLO which DP8417 versus DP8419 Separate delay specifications TRISTATE timing paths provided tables this data sheet DP8418 DP8419 DP8418 DYNAMIC CONTROLLER DRIVER identical DP8419 with exception functional differences incorporated improve performance with 32-bit microprocessors (B1) used enable disable pair outputs DP8419) connect When RAS0 RAS1 enabled such that they both during access When high RAS2 RAS3 enabled This feature useful when driving words bits more since each would driving only half word distributing load each line this DP8418 will meet same specifications driving banks DRAMs each DP8419 does driving banks bits each hidden refresh function available DP8419 been disabled order reduce amount setup time necessary from going RASIN going during access DRAM This parameter called tCSRL1 DP8418 whereas DP8419 hidden refresh function only allows very small increase system performance best microprocessor frequencies above DP8419 DP8409A DP8419 High Speed DRAM Controller Driver combines most popular memory control features DP8408A DRAM Controller Driver with high speed bipolar oxide isolation processing DP8419 retains high capacitive-load drive capability DP8408A well most frequently used access refresh modes allowing directly replace DP8408A applications using only modes Thus DP8419 will allow most DP8408A users directly upgrade their system replacing their controller chip with DP8419 highest priority DP8419 speed peforming DRAM address multiplexing control signal timing high-capacitive drive capability single chip propagation delay skews minimized Emphasis been placed reducing delay variation over specified supply temperature ranges Except following DP8419 will operate essentially same DP8409A DP8419 significantly faster performance DP8419 replace DP8409A applications which modes Modes DP8409A available DP8419 DP8419 RAHS instead DP8409A allows choices tRAH mode does function end-of-count signal Mode DP8419 does DP8409A DP8419 address control outputs TRI-STATE when high DP8409A DP8419 control outputs active high when high (unless refreshing)
Definitions
three supply pins have been assigned center package reduce voltage drops both There ground pins reduce level noise second ground located pins from that decoupling capacitors inserted directly next these pins important adequately decouple this device high switching currents that will occur when address bits change same direction simultaneously recommended solution would multilayer ceramic capacitor parallel with low-voltage tantalum capacitor both connected close possible reduce lead inductance Figure below
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Capacitor values should chosen depending particular application
Address Inputs Column Address Inputs Multiplexed Address Outputs This address selected from Address Input Latch Column Address Input Latch Refresh Counter RASIN Address Strobe Input RASIN directly controls selected output when access mode outputs during hidden external refresh (RFCK) auto-modes this external refresh clock input refresh cycle should performed each clock period external access mode Column Select Input which enables either column address input latch onto output CASIN (RGCK) auto-modes this Generator Clock input external access mode Column Address Strobe input which controls directly once columns enabled address outputs Address (Latch) Strobe Input Address Column Address Bank Select Latches fall-through with high latching occurs high-to-low transition Chip Select Input When high disables accesses Refreshing however both modes affected this (RFSH) Mode Control Inputs These pins select four available operational modes DP8419 (see Table III) Refresh Input Output auto-modes this Refresh Request Output goes following RFCK
Definitions (Continued)
indicating that hidden refresh performed while RFCK high When this external gate on-chip refresh counter reset zeroes Write Enable Input Write Enable Output follows unconditionally RAHS Address Hold Time Select Selects tRAH generated DP8419 delay line allow with fast slow DRAMs Column Address Strobe Output mode mode with CASIN before goes goes automatically after column address valid address outputs mode follows CASIN directly after goes allowing nibble accessing always high during refresh Address Strobe Outputs enabled output (see Table follows RASIN directly during access During refresh outputs enabled Bank Select Inputs These pins decoded enable four outputs during access (see Table Table TABLE DP8417 DP8419 DP8419X Memory Bank Decode Bank Select (Strobed ADS) RAS0 RAS1 RAS2 RAS3 Enabled RASn Because distributed trace capacitance inductance DRAM input capacitance current spikes created causing overshoots undershoots DRAM inputs that change contents DRAMs even destroy them reduce these spikes damping resistor (low inductance carbon) should inserted between DP8419 outputs DRAMs close possible DP8419 damping resistor values differ depending heavily output loaded These resistors should determined first prototypes (not wirewrapped larger distributed capacitance inductance) Resistors should chosen such that transition control outputs critically damped Typical values will from 100X with lower values being used with larger memory arrays Note that parameters specified with damping resistors more information AN-305 ``Precautions Take When Driving Memories'' DP8419 DRIVING 256k DRAMs DP8419 drive 256k DRAMs DRAMs basically same configuration including 5V-only version Hence most applications different manufacturers' DRAMs interchangeable (for same supply-rail chips) DP8419 drive them (see Figure There three basic configurations 5V-only DRAMs 128-row 512-column array with on-RAM refresh counter 128-row 512-column array with onRAM refresh counter 256-row 256-column array with on-RAM refresh counter DP8419 drive three configurations allows them interchangeable shown Figures providing maximum flexibility choice DRAMs Since 9-bit on-chip refresh counter used 7-bit refresh counter 128-row configuration 8-bit refresh counter 256-row configuration on-RAM refresh counter present never used 256k DRAMs require DP8419's address inputs select memory location within DRAM RAS-only refreshing with nine-bit refresh-counter DP8419 makes before refreshing available 256k DRAMs unnecessary READ WRITE READ-MODIFY-WRITE CYCLES output signal determines what type memory access cycle memory will perform kept high while goes read cycle occurs goes before goes write cycle occurs data (DRAM input data) written into DRAM goes goes later than tCWD after goes first read occurs (DRAM output data) becomes valid then data written into same address DRAM goes this read-modify-write case cannot linked together always follows directly determine type access performed POWER-UP INITIALIZE When first applied DP8419 initialize pulse clears refresh counter internal control flip-flops
TABLE DP8418 Memory Bank Decode Bank Select (Strobed ADS) RAS0 RAS1 RAS2 RAS3 Enabled RASn
Conditions Modes
INPUT ADDRESSING address block consists row-address latch column-address latch resettable refresh counter address latches fall-through when high latch when goes address contains valid addresses until after goes memory cycle permanently high Otherwise must while addresses still valid DRIVE CAPABILITY DP8419 timing parameters that specified driving typical capacitance (including traces) 5V-only DRAMs Since there outputs each specified driving one-fourth total memory address outputs specified driving DRAMs graph Figure used determine slight variations timing parameters loading conditions other than DRAMs
Mode Features Summary
modes operation access refresh Automatic external control selected user Auto access mode provides column change then automatically Choice between different values tRAH auto-access mode controlled independently external control mode allowing nibble mode accessing Automatic refreshing make refreshes transparent system inhibited during refresh cycles
DP8419 Mode Descriptions
MODE EXTERNALLY CONTROLLED REFRESH Figure shows Externally Controlled Refresh timing this mode refresh counter contents multiplexed address outputs outputs enabled follow RASIN that address indicated refresh counter refreshed DRAM banks when RASIN goes refresh counter increments when RASIN goes high RFSH should held least until RASIN goes high (they high simultaneously) that refresh address remains valid outputs remain enabled throughout refresh
burst refresh performed holding RFSH toggling RASIN until rows refreshed useful this case reset refresh counter just prior beginning refresh refresh counter resets zeroes when pulled external gate refresh counter always counts before rolling over zero there rows being refreshed then respectively going high used end-of-burst indicator order that refresh address valid address outputs prior lines going RFSH must before RASIN setup time required given tRFLRL Switching Characteristics This parameter adjusted using Figure loading conditions other than those specified TABLE DP8419 Mode Select Options Mode (RFSH) Mode Operation Externally Controlled Refresh Auto Refresh Forced Externally Controlled Access Auto Access (Hidden Refresh)
DP8419 Mode Descriptions (Continued)
DP8419 Interface Between System DRAM Banks
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FIGURE DP8419 with DRAMS
Only Bits Refresh Counter used Addresses used toggle
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FIGURE DP8419 with Column DRAM
Bits Refresh Counter Used
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FIGURE DP8419 with Column DRAM
Bits Refresh Counter Used
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FIGURE DP8419 with 256k DRAMs
DP8419 Mode Descriptions (Continued)
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Indicates Dynamic Parameters
FIGURE External Control Refresh Cycle (Mode
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FIGURE Burst Refresh Mode
DP8419 Mode Descriptions (Continued)
MODE -AUTOMATIC FORCED REFRESH Mode (RFCK) becomes RFCK (refresh cycle clock) CASIN (RGCK) becomes RGCK (RAS generator clock) RFCK high Mode entered then chip operates MODE (externally controlled refresh) with outputs following RASIN This feature Mode useful those want Mode (automatic access) with externally controlled refresh holding RFCK permanently high need only toggle (RFSH) switch from Mode external refresh with Mode pulled external gate reset refresh counter When using Mode automatic refresh RFCK must input clock signal refresh should occur each period RFCK refresh performed while RFCK high then when RFCK goes immediately goes indicate that refresh requested (RFI still used reset refresh counter even though also used refresh request however open-collector gate should used reset counter this case since forced internally request) After receiving refresh request system must allow forced refresh take place while RFCK External logic monitor RFRQ (RFI that when RFRQ goes this logic will wait access currently progress completed before pulling (RFSH) DP8419 mode access taking place when RFRQ occurs then immediately Once refresh counter contents appear address outputs generated perform refresh external clock RGCK required derive refresh signals second falling edge RGCK after lines They remain until more falling edges RGCK Thus remains high periods RGCK after goes stays periods order obtain minimum delay from going going should tRFSRG before falling edge RGCK
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RFCK goes RFRQ goes hidden refresh
Forced refresh starts after
tRP)
Forced refresh ends RFRQ removes refresh acknowledge
occurred while RFCK high
Next RASIN starts next access acknowledges refresh request
FIGURE DP8419 Performing Forced Refresh (Mode with Various Microprocessors
DP8419 Mode Descriptions (Continued)
Refresh Request terminated goes This signal used refresh earlier than normally would described above pulled high while lines then RASs high tRFRH later designer must careful however violate minimum time DRAMs must also guarantee that minimum precharge time violated during transition from mode mode when access desired immediately following refresh processor tries access memory while DP8419 mode WAIT states should inserted into processor cycles until DP8419 back mode desired access been accomplished (see Figure Instead using WAIT states delay accesses when refreshing HOLD states could used follows RFRQ could connected HOLD Request input system When convenient system acknowledges HOLD Request pulling Using this scheme HOLD will lines (RFI goes high) Thus there must sufficient delay from time HOLD goes high DP8419 returning mode that time DRAMs isn't violated described earlier (see Figure mode refresh with Hold states) perform forced refresh system will inactive about four periods RGCK frequency this refresh rows every average about refresh required With RFCK period RGCK period DRAM accesses delayed refresh only time using Hidden Refresh available mode (refreshing with RFCK high) this percentage will even lower MODE EXTERNALLY CONTROLLED ACCESS this mode control signal outputs controlled directly corresponding control input enabled output follows RASIN follows CASIN (with low) follows determines whether column inputs enabled address outputs (see Figure With high address latch contents enabled onto address going strobes address into DRAMs After waiting allow sufficient row-address hold time (tRAH) after goes enable column address latch contents onto address When column address valid going will strobe into DRAMs determines whether cycle read write read-modify-write access Refer Figures typical Read Write timing using mode
Resistors required DRAM load
depends
DRAMs Maybe 256k Banks drive data bits
Check Bits
Banks drive data bits
Check Bits
Bank drive data bits
Check Bits
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FIGURE Typical Application DP8419 Using External Control Access Refresh Modes
DP8419 Mode Descriptions (Continued)
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FIGURE Read Cycle Timing (Mode
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FIGURE Write Cycle Timing (Mode
DP8419 Mode Descriptions (Continued)
Page Nibble mode performed toggling CASIN once initial access been completed case page mode column address must changed before CASIN goes access memory location (see Figure Parameter tCPdif been specified order that users easily determine minimum pulse widths when CASIN toggling AUTOMATIC GENERATION held high when high even CASIN CASIN when goes goes automatically tASC after column address valid This feature eliminates need externally derived CASIN signal control when performing simple access (Figure demonstrates Auto-CAS generation mode Page nibble accessing performed shown Figure even generated automatically initial access FASTEST MEMORY ACCESS fastest mode access achieved using automatic feature external delay line generate required delay between RASIN amount delay required depends minimum tRAH DRAMs being used DP8419 parameter tDIF1 been specified order that delay between RASIN minimized tDIF1 MAXIMUM (tRPDL tRHA) where tRPDL RASIN delay tRHA address held from going delay between RASIN that guarantees specified DRAM tRAH given MINIMUM RASIN tDIF1 tRAH Example application using DRAMs that require minimum tRAH following demonstrates maximum RASIN time determined With tDIF1 (from Switching Characteristics) RASIN delay delay line will sufficient With Auto-CAS generation maximum delay from (loaded with Thus maximum RASIN time under given conditions With maximum RASIN time (tRPDL) maximum time about Most DRAMs with minimum tRAH have maximum tRCD about Thus memory accesses likely limited instead limited other words memory access time limited DRAM performance controller performance REFRESHING CONJUNCTION WITH MODE using mode access memory mode (externally controlled refresh) must used refreshing MODE AUTOMATIC ACCESS WITH HIDDEN REFRESHING CAPABILITY Automatic-Access advantages over externally controlled access (mode First column change derived internally from input signal RASIN Thus need external delay line (see mode eliminated Secondly since CASIN needed generate column change these pins used automatic refreshing function AUTOMATIC ACCESS CONTROL Mode DP8419 makes accessing Dynamic nearly easy accessing static Once column addresses valid (latched DP8419 necessary) RASIN going that required perform memory access
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FIGURE Page Nibble Access Mode
DP8419 Mode Descriptions (Continued)
Indicates Dynamic Parameters
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FIGURE Mode Timing (Refer Figure mode selected follows RASIN immediately mode strobe address into DRAMs address remains valid DP8419 address outputs long enough meet tRAH requirement DRAMs (pin RAHS DP8419 allows user choices tRAH) Next column address replaces address address outputs goes strobe columns into DRAMs determines whether read write read-modify-write done diagram below illustrates mode automatic control signal generation combination mode (hidden refresh) mode (auto-refresh) combination mode mode Externally Controlled Refreshing Mode Mode refreshing accomplished using external refreshes either mode mode with (RFCK) tied high (see mode mode descriptions) this desired system determines when refresh will performed puts DP8419 appropriate mode controls signals directly with RASIN on-chip refresh counter enabled address outputs DP8419 when refresh mode entered increments when RASIN goes high completion refresh Mode Refreshing (hidden) with Mode refreshing (auto) (Refer Figure RFCK tied clock (see mode description) becomes refresh request output goes following RFCK going refresh occurred while RFCK high Refreshes performed mode when DP8419 selected access high) RFCK high these conditions exist refresh counter contents appear DP8419 address outputs lines follow RASIN that RASIN goes access other than through DP8419 occurs) lines perform refresh DP8419 allows only refresh this type each period RFCK since RFCK should fast enough such that refresh period sufficient meet DRAM refresh requirement
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REFRESHING CONJUNCTION WITH MODE When using mode perform memory accesses refreshing accomplished externally mode mode
DP8419 Mode Descriptions (Continued)
Once started hidden refresh will continue even RFCK goes However must high throughout refresh (until RASIN goes high) These hidden refreshes valuable that they delay accesses When determining duty cycle RFCK high time should maximized order maximize probability hidden refreshes hidden refresh doesn't happen then refresh request will occur when RFCK goes After receiving request system must perform refresh while RFCK This done going mode allowing automatic refresh (see mode description) This refresh must completed while RFCK thus RFCK time determined worst-case time required system respond refresh request Mode Refresh (Hidden Refresh) with mode Refresh (External Refresh) This refresh scheme identical that except that after receiving refresh request mode entered refresh (see mode description) refresh request terminated (RFI goes high) soon mode entered This method requires more control than using mode (auto-refresh) however desirable mode refresh time considered excessive Example System Characteristics DRAM used tRAH requirement tASR DRAM address valid from time memory cycle four banks twenty-two 256K memory chips each being driven Using DP8419 (see Figure (RAHS) high guarantee minimum tRAH which sufficient DRAMs being used Generate RASIN earlier than time tASRL (see switching characteristics) that address valid DRAM address inputs before occurs high since latching DRAM address DP8419 necessary Connect first system address bits R0-R8 C0-C8 bits Connect each output DP8419 inputs DRAMs bank memory array connect Q0-Q8 DP8419 A0-A8 DRAMs connect DP8419 DRAMs Figure illustrates similar example using DP8418 drive 32-bit banks
Figure demonstrates system designer would DP8419 mode based certain characteristics system
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FIGURE Hidden Refreshing (Mode Forced Refreshing (Mode Timing
DP8419 Mode Descriptions (Continued)
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FIGURE Typical Application DP8419 Using Modes
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FIGURE Typical Application DP8418 Using Modes
Applications
desires memory interface containing DP8419 that minimizes number external components required modes should used These modes provide Automatic access memory mode only signal RASIN required order access memory) Hidden refresh capability (refreshes performed automatically while mode when non-local accesses taking place determined Refresh request capability hidden refresh took place while RFCK high refresh request generated when RFCK goes high) Automatic forced refresh refresh request generated while mode described above external logic should switch DP8419 into mode automatic forced refresh other external control signals need issued WAIT states inserted into processor machine cycles system tries access memory while DP8419 mode doing forced refresh) Some items considered when integrating DP8419 into system design system designer should ensure that DRAM access progress when refresh mode entered Similarly should attempt start access while refresh progress parameter tRFHRL specifies minimum time from RFSH high RASIN going initiate access should always guarantee that DP8419 enabled access prior initiating access (see tCSRL1) should bring RASIN even during non-local access cycles when mode order maximize chance hidden refresh occurring lower frequencies (under Mhz) becomes increasingly important differentiate between READ WRITE cycles RASIN generation during READ cycles take place soon knows that processor READ access cycle started WRITE cycles other hand cannot start until knows that data written DRAM inputs will valid setup time before (column address strobe) goes true DRAM inputs Therefore general READ cycles initiated earlier than WRITE cycles Many times possible only WAIT states during READ cycles have WAIT states during WRITE cycles This because generally takes less time write data into memory than read data from memory DP84XX2 family inexpensive preprogrammed medium Programmable Array Logic devices (PALs) have been developed provide easy interface between various microprocessors DP84XX family DRAM controller drivers These PALs interface necessary control signals particular processor DP8419 controls operation DP8419 modes while meeting critical timing considerations discussed above refresh clock RFCK divided down from processor clock using counter such DM74LS393 DP84300 programmable refresh timer DP84300 provide RFCK periods ranging from based input clock Figure shows general block diagram system using DP8419 modes Figure shows possible timing diagrams such system (using WAIT prohibit access when refreshing) Although DP84XX2 PALs offered standard peripheral devices DP84XX DRAM controller drivers programming equations these devices provided user make minor modification unique system requirements ADVANTAGES DP8419 OVER DISCRETE DYNAMIC CONTROLLER DP8419 system solution takes much less board space because everything chip (latches refresh counter control logic multiplexers drivers internal delay lines) Less effort needed design memory system DP8419 automatic modes which require minimum external control logic Also programmable array logic devices (PALs) have been designed which allow easy interface most popular microprocessors (Motorola 68000 family National Semiconductor 32032 family Intel 8086 family Zilog Z8000 family) Less skew memory timing parameters because critical components chip (many discrete drivers specify minimum on-chip skew under worst-case conditions this cannot used more then driver needed such would case driving large dynamic array) switching characteristics give designer critical timing specifications based output levels (low high specified load capacitance timing parameters specified DP8419 driving DRAM's over temperature range degrees centigrade extra drivers needed) under worst-case driving conditions with outputs switching simultaneously (most discrete drivers market specify worst-case conditions with only output switching time this true worst-case condition
Applications (Continued)
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FIGURE Connecting DP8419 Between 16-bit Microprocessor Memory
microprocessor's clock period
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FIGURE DP8419 Auto Refresh Access with WAIT States
Switching Characteristics
parameters specified with equivalent load capacitances including traces DRAMs organized banks DRAMs each Maximums based worstcase conditions including outputs switching simultaneously This many cases results values shown DP84XX DRAM controller data sheet being much looser than true worst case (maximum) delays system designer should estimate DP8419 load application modify appropriate parameters using graph Figure example calculations provided below additional fact that line driving less (switching faster) than load which spec applies address will remain valid about same time irregardless address loading since considered valid beginning transition
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FIGURE Output Load Circuit
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FIGURE Change Propagation Delay Relative ``True'' (Application) Load Minus Specified Data Sheet Load Examples mode user driving 16-bit banks DRAM following approximate ``true'' loading conditions Q0-Q8 tRPDL (since loading same that which spec'ed) tCPDL tCCAS tRCC tRHA significantly effected since does involve output transition Other parameters adjusted similar manner mode user driving 16-bit bank DRAM following approximate ``true'' loading conditions Q0-Q8 parameters should adjusted follows with RAHS ``1'' tRICL tRCDL (the lighter loading lighter loading) tRAH
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FIGURE DP8417 TRI-STATE Waveforms
Absolute Maximum Ratings (Note Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications Supply voltage
Storage Temperature Range Input Voltage Output Current Lead Temp (Soldering seconds)
Operating Conditions
Supply Voltage Ambient Temperature
Units
Electrical Characteristics
Symbol IIL1 IIL2 VOL1 VOL2 VOH1 VOH2
Except Except RASIN
unless otherwise noted (Note
Parameter Input Clamp Voltage Input High Current Inputs Output Load Current Input Current Inputs RASIN Input Threshold Input High Threshold Output Voltage Output Voltage Output High Voltage Output High Voltage Output High Drive Current Output Drive Current Supply Current
Conditions Output high
Units
VOUT (Note VOUT (Note
Switching Characteristics DP8417 DP8418 DP8419 DP8419X
unless otherwise noted (Notes output load capacitance typical banks DRAMs each DRAMs including trace capacitance These values Q0-Q8 RAS0- RAS3 500X unless otherwise noted Figure test load open unless otherwise noted Maximum propagation delays specified with outputs switching Preliminary Symbol ACCESS tRICL0 tRICL0 tRICL1 tRICL1 tRICH tRCDL0 tRCDL0 tRCDL1 tRCDL1 tRCDH tRAH0 tRAH1 tASC RASIN Delay (RAHS RASIN Delay (RAHS RASIN Delay (RAHS RASIN Delay (RAHS RASIN High Delay Delay (RAHS Delay (RAHS Delay (RAHS Delay (RAHS High Delay Address Hold Time (RAHS Mode Address Hold Time (RAHS Mode Column Address Set-up Time (Mode Parameter Condition Units
Figure DP8417 19-80 Figure DP8417 19-70 Figure DP8417 19-80 Figure DP8417 19-70 Figure Figure DP8417 19-80 Figure DP8417 19-70 Figure DP8417 19-80 Figure DP8417 19-70 Figure Figure Figure Figure
Switching Characteristics DP8417 DP8418 DP8419 DP8419X (Continued) unless otherwise noted (Notes output load capacitance typical banks DRAMs each DRAMs including trace capacitance These values Q0-Q8 RAS0-RAS3 500X unless otherwise noted Figure test load open unless otherwise specified Maximum propagation delays specified with outputs switching Preliminary
Symbol ACCESS (Continued) tRCV0 tRCV0 tRCV1 tRCV1 tRPDL tRPDH tASRL tAPD tSPD tASA tAHA tADS tWPD tCPDL tCPDH tCPdif tRCC tRCR tRHA tCCAS tDIF1 tDIF2 REFRESH tRASINL tRFPDL0 Refresh Cycle Period Pulse Width RASIN during Refresh RASIN Delay during Refresh (Mode RASIN Column Address Valid (RAHS Mode RASIN Column Address Valid (RAHS Mode RASIN Column Address Valid (RAHS Mode RASIN Column Address Valid (RAHS Mode RASIN Delay RASIN High Delay Address Set-up RASIN Address Input Output Delay Address Strobe High Address Output Valid Address Set-up Time Address Hold Time from Address Strobe Pulse Width Output Delay CASIN Delay Mode CASIN High Delay Mode tCPDL tCPDH Column Select Column Address Valid Select Address Valid Address Held from Column Select Delay (CASIN Mode Delay (CASIN Mode Maximum (tRPDL tRHA) Maximum (tRCC tCPDL) Parameter Condition Units
Figure DP8417 19-80 Figure DP8417 19-70 Figure DP8417 19-80 Figure DP8417 19-70 Figures Figures Figures Figures Figures Figures Figures Figures Figure Figure Figure
Mode Description
Figure Figures Figure Figure DP8417 19-80 Figure DP8417 19-70
Mode Description
Figure Figure Figure
Switching Characteristics DP8417 DP8418 DP8419 DP8419X (Continued) unless otherwise noted (Notes output load capacitance typical banks DRAMs each DRAMs including trace capacitance These values Q0-Q8 RAS0- RAS3 500X unless otherwise noted Figure test load open unless otherwise specified Maximum propagation delays specified with outputs switching
Symbol REFRESH (Continued) tRFPDL5 tRFPDH0 tRFPDH5 tRFLCT tRFLRL RASIN Delay during Hidden Refresh RASIN High Delay during Refresh (Mode RASIN High Delay during Hidden Refresh RFSH Counter Address Valid RFSH Set-up RASIN (Mode Minimum tASR RFSH High Setup Access RASIN RFSH High Address Valid High Count Valid Counter Reset Pulse Width Counter Outputs Minimum Pulse Width RFCK Period Generator Clock Minimum Pulse Width RGCK Minimum Pulse Width High RGCK RFCK Forced RFRQ (RFI RGCK Forced RFRQ High RGCK RGCK High Parameter Condition Units
Figure Figure Figure Figures Figure
tRFHRL tRFHRV tROHNC tRST tCTL tRFCKL tRGCKL tRGCKH tFRQL
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
tFRQH
tRGRL tRGRH
Switching Characteristics DP8417 DP8418 DP8419 DP8419X (Continued) unless otherwise noted (Notes output load capacitance typical banks DRAMs each DRAMs including trace capacitance These values Q0-Q8 RAS0 -RAS3 500X unless otherwise noted Figure test load open unless otherwise specified Maximum propagation delays specified with outputs switching
Symbol Parameter Condition REFRESH (Continued) tRQHRF tRFRH RFSH Hold Time from RGCK RFSH High High (Ending Forced Refresh early) RFSH Set-up RGCK (Mode High RASIN Hidden Refresh RFCK High RASIN hidden Refresh Access RASIN (Using Mode with Auto Refresh Mode) Access RASIN (Using Modes with externally controlled Refresh) Access RASIN (Using Mode with Auto Refresh Mode) Access RASIN (Using Modes with externally controlled Refresh) PRELIMINARY Access RASIN (Using Mode with Auto Refresh Mode) Access RASIN (Using Modes with externally controlled Refresh) Output High from Hi-Z High Output Hi-Z from High High Output Hi-Z from High Output from Hi-Z High Output Hi-Z from Units
Figure
(See Mode Description) (See Mode Description) Figure
tRFSRG
tCSHR tRKRL
Figure
DP8419 DP8419X ONLY tCSRL1
Figure
(See Mode Description)
tCSRL0
DP8418 ONLY tCSRL1
Figure
(See Mode Description)
tCSRL0
DP8417 ONLY tCSRL1
Figure
(See Mode Description)
tCSRL0
TRI-STATE (DP8417 ONLY) Open Figure Open Figure Open RAS0-3 CAS0-3 Figure Closed Figure Closed Figure
Input Capacitance (Note
Symbol Parameter Input Capacitance RASIN Input Capacitance Other Inputs Condition Units
Note ``Absolute Maximum Ratings'' values beyond which safety device cannot guaranteed They meant imply that device should operated these limits table ``Electrical Characteristics'' provides conditions actual device operation Note typical values Note This test provided monitor Driver output source sink current capability Caution should exercised testing this parameter testing these parameters resistor should placed series with each output under test output should tested time test time should exceed second Note Input pulse Input reference point measurements Output reference points High Note load capacitance should exceed
Physical Dimensions inches (millimeters)
Hermetic Dual-in-Line Package Order Number DP8417D-70 DP8417D-80 DP8418D-70 DP8418D-80 DP8419D-70 DP8419D-80 Package Number D48A
Hermetic Dual-in-Line Package Order Number DP8419XD-80 DP8419XD-70 Package Number D52A
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-in-Line Package Order Number DP8417N-70 DP8417N-80 DP8418N-70 DP8418N-80 DP8419N-70 DP8419N-80 Package Number N48A
DP8417 NS32817 8418 32818 8419 32819 8419X 32819X 256k Dynamic Controller Drivers
Physical Dimensions inches (millimeters) (Continued)
103070
Plastic Chip Carrier Order Number DP8417V-70 DP8417V-80 DP8418V-70 DP8418V-80 DP8419V-70 DP8419V-80 Package Number V68A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications
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