High-performance 32-bit RISC Architecture High-density 16-bit Instruct

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High-performance 32-bit RISC Architecture High-density 16-bit Instruct

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Utilizes ARM7TDMIARM® Thumb® Processor Core
High-performance 32-bit RISC Architecture High-density 16-bit Instruction Embedded (In-circuit Emulation) Kbytes Internal Fully Programmable External Interface (EBI) Maximum External Address Space Mbytes Four Chip Selects Software Programmable 8-/16-bit External Data 16-channel Correlator Accuracy: Time First Fix: 8-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller Three External Interrupts Programmable Lines Three USARTs Dedicated Peripheral Data Controller (PDC) Channels USART Master/Slave Interface Dedicated Peripheral Data Controller (PDC) Channels 16-bit Programmable Data Length Four External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) Peripherals Deactivated Individually Clock Manager (CLM) Geared Master Clock Reduce Power Consumption Sleep State with Disabled Master Clock Controller Signals Real Time Clock (RTC) Time Format 15-bit Fractional Part Second Programmable Interrupt Timer with 8-bit Fractional Part Second Parallel Load Supply Voltage Includes Power Supervisor Battery Backup Memory 100-pin Package
Baseband Processor ATR0620 Preliminary
Description
baseband processor ATR0620 includes 16-channel correlator based ARM7TDMI processor core. This processor high-performance 32-bit RISC architecture with high-density 16-bit instruction very power consumption. addition, large number internally banked registers result very fast exception handling, making device ideal real-time control applications. ATR0620 direct connection off-chip memory, including flash, through External Interface (EBI). ATR0620 manufactured using Atmel's high-density CMOS technology. combining ARM7TDMI microcontroller core with on-chip SRAM, 16-channel correlator wide range peripheral functions monolithic chip, ATR0620 provides highly flexible cost-effective solution applications.
Rev. 4574B-GPS-12/02
Figure Block Diagram
Accelerator
nSLEEP CLK32768
RF_ON
Power Management Controller
SRAM
nSHDN
GPSMODE10 GPSMODE7 GPSMODE5 GPSMODE3 GPSMODE2 GPSMODE4 TIMEPULSE GPSMODE9 GPSMODE1 GPSMODE0 GPSMODE11 GPSMODE8 GPSMODE6
Correlators
PIO2
SIGLO SIGHI
Generator
Clock Manager (CLM)
CLK23
PIO2 Controller
USART2
Special Function
TXD2 RXD2
PIO2
PIO2
Advanced Interrupt Controller
EXTINT2 EXTINT0
USART1
TXD1 RXD1
Watchdog
Interface Off-Chip Memory (EBI)
EM_A19 EM_A1 EM_DA15 EM_DA0
ARM7TDMI
Embedded
Power Supply Manager
DBG_EN TEST_MODE nTRST
JTAG
SRAM 128K
288K
PDC2
NWD_OVF BOOT_MODE0 EM_A20 EM_A0/NLB PDSR8 NUB/NWR1 NOE/NRD NWE/NWR0 nCS0 nCS1 BOOT_MODE1
USART0
TXD0 RXD0
VBAT18_O VBAT VBAT18_I LDOBAT_IN LDO_OUT LDO_IN LDO_EN
nRESET
ATR0620
4574B-GPS-12/02
Reset Controller
ATR0620
Configuration
Serial Number CPGA Name EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 SIGHI SIGLO XT_IN XT_OUT nSLEEP CLK23 nTRST TEST_MODE DBG_EN RF_ON nRESET nSHDN EM_A1 EM_A2 EM_A3 EM_A4 Firmware Label
Bank
Bank
TXD0 RXD0 GPSMODE4 TXD1 RXD1 GPSMODE5
TXD0
MSOUT
RXD0 SCK0
SCK0 TXD1
GPS_MON5 NUB/NWR1
RXD1 SCK1
SCK1
GPS_MON6
BOOT_MODE0 BOOT_MODE1
NWD_OVF 1PPS
GPS_MON0 GPS_MON1
Note:
selection option PIO.
4574B-GPS-12/02
Configuration (Continued)
Serial Number CPGA Name EM_A5 EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 EM_A16 EM_A17 EM_A18 EM_A19 VDD18_R VDD18_B VDD18_L2 VDD18_L1 VBAT GND_R GND_B GND_T GND_L GND_BAT LDO_EN LDO_OUT (OH) (OH) (OH) (OH) LDO_IN (OH) (OH) LDOBAT_IN
Firmware Label
Bank
Bank
GPSMODE8 GPSMODE9 GPSMODE7 GPSMODE10 GPSMODE1
MOSI MISO EXTINT0
MOSI MISO NPCS0
GPS_MON2 GPS_MON3 MCLK_OUT GPS_MON4 EM_A0/NLB
nCS1 nCS0 NWE/NWR0 NOE/NRD
nCS1 nCS0 NWE/NWR0 NOE/NRD
AGCOUT0
NUB/NWR1 EM_A0/NLB EM_A21 (RFU) NWD_OVF GPSMODE6 GPSMODE0
NUB/NWR1 EM_A0/NLB
MCLK_OUT EM_A21 GPS_MON10 NWD_OVF EM_A20 GPS_MON7
EXTINT2
AGCOUT0
SIGHI2 SIGLO2
AGCOUT1
Note:
selection option PIO.
ATR0620
4574B-GPS-12/02
ATR0620
Configuration (Continued)
Serial Number
CPGA
Name VBAT18_O VBAT18_I TOUT1 EM_DA16 EM_DA17 EM_DA18 EM_DA19 EM_DA20 EM_DA21 EM_DA22 EM_DA23 EM_DA24 EM_DA25 EM_DA26 EM_DA27 EM_DA28 EM_DA29 EM_DA30 EM_DA31 TMON0 TMON1 TMON2 TMON3 TMON4 TMON5 TMON6 TMON7 TMON8 TMON9 TMON10 TMON11 TMON12 TMON13 TMON14 TMON15 TMON16 TMON17
Firmware Label TXD2 RXD2 1PPS GPSMODE11 EM_A20 GPSMODE12 GPSMODE2 GPSMODE3
Bank
Bank TXD2
EM_A22 EM_A23 1PPS GPS_MON11 EM_A20 MSOUT GPS_MON8 GPS_MON9
RXD2 SCK2
SCK2 NPCS1 NPCS2 NPCS3 nCS2 nCS3
EXTINT1
APB_SELECT
Note:
selection option PIO.
4574B-GPS-12/02
Configuration (Continued)
Serial Number
CPGA
Name TMON18 TMON19 TMON20 TMON21 TMON22 TMON23 TMON24 TMON25 TMON26 POR_VEXT
Firmware Label
Bank
Bank
Note:
selection option PIO.
Description
Module Name EM_A0 EM_DA0 NCS0 NCS3 NWR0 NWR1 NWAIT BOOT_MODE0 BOOT_MODE1 TXD0-2 USART RXD0-2 SCK0-2 EXTINT0-2 AGCOUT0-1 RF_ON nSleep nSHDN XT_IN XT_OUT MOSI MISO NPCS0-3 NWD_OVF
Function
Type Output Output Output Output Input Output
Active Level High/Low
Comment valid after reset Used byte write option Used byte write option Used byte write option Used byte select option Used byte select option Used byte select option Used byte write option PIO-controlled after reset, pull PIO-controlled after reset, pull down PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset ATR0600 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset
Address Data Chip select Lower byte write signal Lower byte write signal Read signal Write enable Output enable Upper byte select (16-bit SRAM Lower byte select (16-bit SRAM Wait signal Boot mode input Boot mode input Transmit data output Receive data input External serial clock External interrupt request Automatic gain control Clear sleep output (AF-LDO) Clear sleep output (1.8LDO) Oscillator input Oscillator output clock Master slave Master slave Slave select Watchdog timer overflow
ATR0620
4574B-GPS-12/02
ATR0620
Description (Continued)
Module Name PDSR0-31 GPSMODE0-12 SIGHI SIGLO SIGHI2 SIGLO2 1PPS MSOUT GPS_MON0-11 JTAG/ NTRST DBG_EN CLOCK RESET CLK23 MCLK_OUT nReset VDD18 POWER VBAT18_I LDOBAT_IN LDOBAT VBAT VBAT18_O LDO_IN LDO_OUT LDO_EN TEST_MODE TEST POR_VEXT TMON0-26
Function
Type Input Input Input Input Output Output Input Input Output Input Input Input Input Output Input Power Power Power Power Power Power Power Input Input Input Output Output
Active Level
Comment Input after reset PIO-controlled after reset Pull down Pull down Pull down Pull down Pull down Schmitt trigger Backup power Backup power Production test POR18 test Debug package
Programmable port mode monitor Test mode select Test data Test data Test clock Test reset input Debug enable Clock input Master clock output Reset input enable Test mode select Test input Test monitor output
TOUT1/APB_Select Test output
4574B-GPS-12/02
Architecture Overview
ATR0620 architecture consists main buses, Advanced System (ASB) Advanced Peripheral (APB). designed maximum performance. interfaces processor with on-chip 32-bit memories external memories devices means External Interface (EBI). designed accesses on-chip peripherals optimized power consumption. AMBA bridge provides interface between APB. on-chip Peripheral Data Controller (PDC2) transfers data between on-chip USARTs/SPI off-chip memories without processor intervention. Most importantly, PDC2 removes processor interrupt handling overhead significantly reduces number clock cycles required data transfer. transfer continuous bytes without reprogramming starting address. result, performance microcontroller increased power consumption reduced. ATR0620 peripherals designed easily programmable with minimum number instructions. Each peripheral 16-Kbyte address space allocated upper bytes 4-Gbyte address space. Except interrupt controller, peripheral base address lowest address memory space. peripheral register composed control, mode, data, status interrupt registers. maximize efficiency manipulation, frequently-written registers mapped into three memory locations. first address used individual register bits, second resets bits third address reads value stored register. reset writing corresponding position appropriate address. Writing zero effect. Individual bits thus modified without having costly read-modify-write complex bit-manipulation instructions. external signals on-chip peripherals under control parallel controller. PIO2 controller programmed insert input filter each generate interrupt signal change. After reset, user must carefully program PIO2 controller order define which peripheral signals connected with off-chip logic. ARM7TDMI processor operates little-endian mode ATR0620 baseband. processor's internal architecture Thumb instruction sets described ARM7TDMI data sheet. memory on-chip peripherals described detail ATR0620 data sheet. electrical mechanical characteristics also documented ATR0620 data sheet. standard In-Circuit Emulation (ICE) debug interface supported port ATR0620.
PDC2
ATR0620 8-channel PDC2 dedicated three on-chip USARTs SPI. PDC2 channel connected receiving channel transmitting channel each peripheral. user interface PDC2 channel integrated memory space each USART channel memory space SPI. contains 32-bit address pointer register 16-bit count register. When programmed data transferred, end-of-transfer interrupt generated corresponding peripheral. USART section section more details PDC2 operation programming.
ATR0620
4574B-GPS-12/02
ATR0620
EBI: External Interface
generates signals that control access external memory peripheral devices. fully programmable address bytes. four chip selects 20-bit address bus. 16-bit data configured interface with 16-bit external devices. Separate read write control signals allow direct memory peripheral interfacing. supports different access protocols, allowing single clock cycle memory accesses. main features are: External memory mapping active chip select lines 16-bit data Byte write byte select lines User interface remap function boot memory different read protocols Programmable wait state generation Programmable data float time Programmable write protection each memory bank
AIC: Advanced Interrupt Controller
ATR0620 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces software real time overhead handling internal external interrupts. interrupt controller connected NFIQ (fast interrupt request) NIRQ (standard interrupt request) inputs ARM7TDMI processor. processor's NFIQ line only asserted external fast interrupt request input: FIQ. NIRQ line asserted interrupts generated on-chip peripherals external interrupt request lines: IRQ0 IRQ3. 8-level priority encoder allows customer define priority between different NIRQ interrupt sources. Internal sources programmed level sensitive edge triggered. External sources programmed positive negative edge triggered high- low-level sensitive.
PIO2: Parallel Controller
ATR0620 features programmable lines. lines multiplexed with on-chip peripheral signals order optimize available package pins. PIO2 controller provides internal interrupt signal Advanced Interrupt Controller (AIC).
4574B-GPS-12/02
USART2: Universal Synchronous/ Asynchronous Receiver/Transmitter
ATR0620 provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface connected peripheral data controller. main features are: Programmable baud rate generator Parity, framing overrun error detection Line break generation detection Automatic echo, local loopback remote loopback channel modes Multi-drop mode: address detection generation Interrupt generation dedicated peripheral data controller channels 9-bit character length Protocol 7816
SPI: Serial Peripheral Interface
ATR0620 features SPI, which provides communication with external devices master slave mode. four external chip selects that connected devices. data length programmable from 16-bit. used move data directly between memory without intervention maximum real-time processing throughput. ATR0620 features internal watchdog timer, which used guard against system lock-up software becomes trapped deadlock. watchdog timer programmed generate interrupt internal reset. power management controller allows optimization power consumption. enables/disables clock inputs most peripherals well processor. When clock disabled, current instruction processed before clock stopped. clock re-enabled enabled interrupt hardware reset. When peripheral clock disabled, clock immediately stopped. When clock re-enabled peripheral resumes action where left off. static nature design, contents on-chip registers which clocks disabled remain unchanged.
Watchdog Timer
PMC: Power Manager Controller
CLM: Clock Manager
addition Power Management Controller (PMC) Clock Manager (CLM) another possibility reduce power consumption. clock manager provides fixed divided clocks USARTs, watchdog timer generates master clock which divided. master clock programmable frequencies between 23.1 MHz. ATR0620 provides registers that implement following special functions: Chip identification RESET status
Special Function
ATR0620
4574B-GPS-12/02
ATR0620
includes channels. They programmed seperately. possible generate output voltage range from (255/256) VDD18. provides time format. structure system time: zero point midnight Universal Time (UT) January 1980. From zero point weeks, time week 15-bit fractional part second counted. Each week 604800 seconds (GPS system time does count leap seconds. Therefore, compared time shifted some seconds). Additional provides programmable interrupt (maximum period: week).
Correlator
correlator incorporates channels provides functionality required sampling, down-converting correlating signals. correlator processes signal data acquire satellite signals using model satellite codes multiply/accumulate circuits (correlators) spread signal bandwidth enough detect above thermal noise.
Accelerator
ATR0620 features accelerator which reduces time identify correct signal.
4574B-GPS-12/02
Ordering Information
Extended Type Number ATR0620-100 ATR0620-144 Package CTBGA100 Remarks 0.80 pitch Debug package
Package Outline CTBGA100
VIEW SIDE VIEW
1.10 0.10 9.00 0.05 0.30 0.05 0.40 Dia.
9.00 0.05
0.60 0.05
BOTTOM VIEW
0.80 0.05
BALL CORNER
0.90 0.05
0.90 0.05
0.80 0.05
ATR0620
4574B-GPS-12/02
ATR0620
Package CPGA144
VIEW
1.575 0.16
SIDE VIEW
0.090 0.009
0.018 0.002 1.575 0.16
BOTTOM VIEW
1.400 0.012 0.100
4574B-GPS-12/02
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Atmel Corporation 2002. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems.
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4574B-GPS-12/02

High-performance 32-bit RISC Architecture High-density 16-bit Instruct

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