Dual Digitally Programmable Potentiometer (DPPTM) with Taps Interface

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Dual Digitally Programmable Potentiometer (DPPTM) with Taps Interface

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CAT5261
Dual Digitally Programmable Potentiometer (DPPTM) with Taps Interface
linear-taper digitally programmable
E
Automatic recall saved wiper settings
potentiometers
resistor taps potentiometer resistance 100k Potentiometer control memory access
power
volt operation Standby current less than 1,000,000 nonvolatile WRITE cycles year nonvolatile memory data retention 24-lead SOIC 24-lead TSSOP Industrial temperature range
interface
wiper resistance, typically Nonvolatile memory storage four wiper
settings each potentiometer
DESCRIPTION
CAT5261 Digitally Programmable Potentiometers (DPPsTM) integrated with control logic bytes NVRAM memory. Each consists series resistive elements connected between externally accessible points. points between each resistive element connected wiper outputs with CMOS switches. separate 8-bit control register (WCR) independently controls wiper switches each DPP. Associated with each wiper control register four 8-bit non-volatile memory data registers (DR) used storing four wiper settings. Writing wiper control register non-volatile data registers serial bus. power-up, contents first data register (DR0) each potentiometers automatically loaded into respective wiper control register. CAT5261 used potentiometer terminal, variable resistor. intended circuit level system level adjustments wide variety applications. available -40°C 85°C industrial operating temperature range offered 24-lead SOIC TSSOP package.
CONFIGURATION
SOIC/TSSOP Package W/U,
5261 HOLD
FUNCTIONAL DIAGRAM
INTERFACE
WIPER CONTROL REGISTERS
HOLD CONTROL LOGIC NONVOLATILE DATA REGISTERS
2004 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Document 2122, Rev.
CAT5261
DESCRIPTION
(SOIC/TSSOP)
DESCRIPTIONS
Function
Serial Data Output Device Address, Connect Connect Connect Connect Supply Voltage Reference Terminal Potentiometer High Reference Terminal Potentiometer Wiper Terminal Potentiometer Chip Select Write Protection Serial Input Device Address Reference Terminal Potentiometer High Reference Terminal Potentiometer Wiper Terminal Potentiometer Ground Connect Connect Connect Connect Serial Clock Hold
Name
HOLD
Serial Input serial data input pin. This used input opcodes, byte addresses data written CAT5261. Input data latched rising edge serial clock. Serial Output serial data output pin. This used transfer data CAT5261. During read cycle, data shifted falling edge serial clock. SCK: Serial Clock serial clock pin. This used synchronize communication between microcontroller CAT5261. Opcodes, byte addresses data present latched rising edge SCK. Data updated falling edge SCK. Device Address Inputs These inputs device address when addressing multiple devices. total four devices addressed single bus. match slave address must made with address input order initiate communication with CAT5261. Resistor Points pins equivalent terminal connections mechanical potentiometer. Wiper pins equivalent wiper terminal mechanical potentiometer. Chip Select
Chip select pin. enables CAT5261 high disables CAT5261. high takes output high impedance forces devices into Standby mode (unless internal write operation underway). CAT5261 draws ZERO current Standby mode. high transition required prior sequence being initiated. high transition after valid write sequence what initiates internal write cycle. Write Protect Write Protect pin. Write Protect will allow normal read/write operations when held high. When tied low, non-volatile write operations Data registers inhibited (change wiper control register allowed). going while still will interrupt write registers. internal write cycle already been initiated, going will have effect write operation. HOLD: HOLD Hold HOLD used pause transmission CAT5261 while middle serial sequence without having retransmit entire sequence later time. pause, HOLD must brought while low. high impedance state during time part paused, transitions pins will ignored. resume communication, HOLD brought high, while low. (HOLD should held high time this function being used.) HOLD tied high directly tied through resistor.
Document 2122, Rev.
CAT5261
SERIAL PROTOCOL
CAT5261 supports data transmission protocol. synchronous Serial Peripheral Interface (SPI) helps CAT5261 interface directly with many today's popular microcontrollers. CAT5261 contains 8-bit instruction register .The instruction operation codes detailed instruction table page After device selected with going first byte will received. part accessed pin, with data being clocked rising edge SCK. first byte contains op-codes that define operation performed.
DEVICE OPERATION
CAT5261 resistor arrays integrated with serial interface logic, 8-bit wiper control registers eight 8-bit, non-volatile memory data registers. Each resistor array contains separate resistive elements connected series. physical ends each array equivalent fixed terminals mechanical potentiometer RL). symmetrical interchanged. positions between ends series resistors connected output wiper terminals (RW) CMOS transistor switch. Only point each potentiometer connected wiper terminal time determined value wiper control register. Data read written wiper control registers non-volatile memory data registers bus. Additional instructions allows data transferred between wiper control registers each respective potentiometer's non-volatile data registers. Also, device instructed operate "increment/decrement" mode.
Document 2122, Rev.
CAT5261
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect VSS(1)(2) -2.0V +VCC +2.0V with Respect Ground -2.0V +7.0V Package Power Dissipation Capability 25°C) 1.0W Lead Soldering Temperature secs) 300°C Wiper Current +6mA
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
Recommended Operating Conditions: +2.5V +6.0V Temperature Industrial -40°C 85°C
Notes: minimum input voltage -0.5V. During transitions, inputs undershoot -2.0V periods less than Maximum voltage output pins +0.5V, which overshoot +2.0V periods less than Latch-up protection provided stresses address data pins from +1V.
POTENTIOMETER CHARACTERISTICS Over recommended operating conditions unless otherwise stated.
Symbol RPOT RPOT Parameter Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance Tolerance RPOT Matching Power Rating VTERM Wiper Current Wiper Resistance Wiper Resistance Voltage Noise Resolution Absolute Linearity
Test Conditions
Units
25°C, each +3mA +3mA Rw(n)(actual)-R(n)(expected)(5) Rw(n+1)-[Rw(n)+LSB](5) RPOT 50k(1) 10/10/25 +300 +0.2
ppm/°C ppm/°C
Relative Linearity TCRPOT TCRATIO CH/CL/CW Temperature Coefficient RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response
Note: This parameter tested initially after design process change that affects parameter. Absolute linearity utilitzed determine actual wiper voltage versus expected voltage determined wiper position when used potentiometer. Relative linearity utilized determine actual change voltage between successive positions when used potentiometer. measure error step size. RTOT 255, single
Document 2122, Rev.
CAT5261
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol ICC1 ICC2 VOL1 VOH1
Parameter Power Supply Current Power Supply Current Non-Volatile WRITE Standby Current (VCC 5.0V) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage (VCC 3.0V) Output High Voltage
Test Conditions fSCK 2.5MHz, Open Inputs fsck 2.5MHz, Open Inputs VCC; Open VOUT
Units
-1.6mA VCC-0.8
CAPACITANCE
Applicable over recommended operating range from 25°C, MHz, 5.0V (unless otherwise noted).
Symbol COUT
Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, HOLD,
Units
Conditions VOUT=0V VIN=0V
Note: This parameter tested initially after design process change that affects parameter.
Document 2122, Rev.
CAT5261
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Test SYMBOL fSCK tRI(1) tFI(1) tDIS tCSS tCSH PARAMETER Data Setup Time Data Hold Time High Time Time Clock Frequency HOLD Output Input Rise Time Input Fall Time HOLD Setup Time HOLD Hold Time Output Valid from Clock Output Hold Time Output Disable Time HOLD Output High High Time Setup Time Hold Time UNITS 50pF Conditions
NOTE: This parameter tested initially after design process change that affects parameter.
POWER TIMING (1)(2)
Over recommended operating conditions unless otherwise stated.
Symbol tPUR tPUW
Parameter Power-up Read Operation Power-up Write Operation
Units
Note: This parameter tested initially after design process change that affects parameter. tPUR tPUW delays required from time stable until specified operation initiated.
XDCP TIMING Symbol Parameter tWRPO tWRL Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued
Units
Document 2122, Rev.
CAT5261
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter Write Cycle Time
Units
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol NEND(1)
Parameter Endurance Data Retention Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard
1,000,000 2000
Units Cycles/Byte Years Volts
VZAP(1) ILTH(1)
Note: This parameter tested initially after design process change that affects parameter.
Figure Sychronous Data Timing
tCSS tCSH
VALID
tDIS HI-Z
HI-Z
Note: Dashed Line= mode
Figure HOLD Timing
HOLD
HIGH IMPEDANCE
Document 2122, Rev.
CAT5261
INSTRUCTION REGISTER DESCRIPTION
DEVICE TYPE ADDRESS BYTE first byte sent CAT5261 from master/ processor called Device Address Byte. most significant four bits Device Type address device type identifier. These bits CAT5261 fixed 0101[B] (refer Table least significant bits slave address byte, internal slave address must match physical device address which defined state input pins CAT5261 successfully continue command sequence. Only device which slave address matches incoming device address sent master executes instruction. inputs actively driven CMOS input signals tied VSS. remaining bits device address byte must Table Identification Byte Format
Device Type Identifier
INSTRUCTION BYTE next byte sent CAT5261 contains instruction register pointer information. four most significant bits used provide instruction opcode bits point four data registers each associated potentiometer. least significant bits point Wiper Control Registers. format shown Table Data Register Selection Data Register Selected
Slave Address
(MSB)
(LSB)
Table Instruction Byte Format
Instruction Opcode Data Register Selection
WCR/Pot Selection
(MSB)
(LSB)
Document 2122, Rev.
CAT5261
WIPER CONTROL DATA REGISTERS
Wiper Control Register (WCR) CAT5261 contains 8-bit Wiper Control Registers, each potentiometer. Wiper Control Register output decoded select switches along resistor array. contents altered four ways: written host Write Wiper Control Register instruction; written transferring contents four associated Data Registers Data Register instruction; modified step time Increment/decrement instruction (see Instruction section more details). Finally, loaded with content data register zero (DR0) upon power-up. Wiper Control Register volatile register that loses contents when CAT5261 powered-down. Although register automatically loaded with value upon power-up, this different from value present power-down. Data Registers (DR) Each potentiometer four 8-bit non-volatile Data Registers. These read written directly host. Data also transferred between Table Instruction
Instruction Instruction Read Wiper Control Register Write Wiper Control Register
Read Data Register Write Data Register Data Register Wiper Control Register Wiper Control Register Data Register Global Data Registers Wiper Control Registers Global Wiper Control Registers Data Register Increment/Decrement Wiper Control Register
Read Status (WIP bit)
Note: data zero
four Data Registers associated Wiper Control Register. data changes Data Registers non-volatile operation will take maximum 5ms. application does require storage multiple settings potentiometer, Data Registers used standard memory locations system parameters user preference data. Write Process contents Data Registers saved nonvolatile memory when input goes HIGH after write sequence received. status internal write cycle monitored issuing Read Status command read Write Process (WIP) bit.
INSTRUCTIONS
Five instructions three bytes length. These instructions are: Read Wiper Control Register read current wiper position selected potentiometer Write Wiper Control Register change current wiper position selected potentiometer Read Data Register read contents selected Data Register
WCR1/
WCR0/
Operation
Read contents Wiper Control Register pointed P1-P0 Write value Wiper Control Register pointed P1-P0 Read contents Data Register pointed P1-P0 R1-R0 Write value Data Register pointed P1-P0 R1-R0 Transfer contents Data Register pointed P1-P0 R1-R0 associated Wiper Control Register Transfer contents Wiper Control Register pointed P1-P0 Data Register pointed R1-R0 Transfer contents Data Registers pointed R1-R0 four pots their respective Wiper Control Registers Transfer contents both Wiper Control Registers their respective data Registers pointed R1-R0 four pots Enable Increment/decrement Control Latch pointed P1-P0 Read check internal write cycle status
Document 2122, Rev.
CAT5261
Write Data Register write value selected Data Register Read Status Read status which when signifies write cycle progress. basic sequence three byte instructions illustrated Figure These three-byte instructions exchange data between Data Registers. controls position wiper. response wiper this action will delayed tWRL. transfer from (current wiper position), Data Register write non-volatile memory takes minimum complete. transfer occur between potentiometers associated registers; transfer occur between both potentiometers associated register. Four instructions require two-byte sequence complete, illustrated Figure These instructions transfer data between host/processor CAT5261; either between host data registers directly between host Wiper Control Register. These instructions are: Data Register Wiper Control Register This transfers contents specified Data Register associated Wiper Control Register. Wiper Control Register Data Register This transfers contents specified Wiper Figure Two-Byte Instruction Sequence
Control Register specified associated Data Register. Global Data Register Wiper Control Register This transfers contents specified Data Registers associated Wiper Control Registers. Global Wiper Counter Register Data Register This transfers contents Wiper Control Registers specified associated Data Registers. INCREMENT/DECREMENT COMMAND final command Increment/Decrement (Figure 10). Increment/Decrement command different from other commands. Once command issued master clock selected wiper and/ down segment steps; thereby providing fine tuning capability host. each clock pulse (tHIGH) while HIGH, selected wiper will move resistor segment towards terminal. Similarly, each clock pulse while LOW, selected wiper will move resistor segment towards terminal. Instructions format more detail.
Device Internal Address
Register Address Pot/WCR Address
Instruction Opcode
Figure Three-Byte Instruction Sequence
Data Pot/WCR Register Address Address WCR[7:0] Data Register D[7:0]
Device
Internal Address
Instruction Opcode
Figure Increment/Decrement Instruction Sequence
Internal Address Pot/WCR Data Register Address Address
Device
Instruction Opcode
Document 2122, Rev.
CAT5261
Figure Increment/Decrement Timing Limits
INC/DEC Command Issued
tWRL
Voltage
INSTRUCTION FORMAT
Read Wiper Control Register (WCR) DEVICE ADDRESSES INSTRUCTION DATA
Write Wiper Control Register (WCR) DEVICE ADDRESSES Read Data Register (DR) DEVICE ADDRESSES Write Data Register (DR) DEVICE ADDRESSES Read (WIP) Status DEVICE ADDRESSES INSTRUCTION DATA
Document 2122, Rev.
INSTRUCTION
DATA
INSTRUCTION
DATA High Voltage Write Cycle
INSTRUCTION
DATA
CAT5261
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) Wiper Control Register (WCR) DEVICE ADDRESSES INSTRUCTION
Global Transfer Wiper Control Register (WCR) Data Register (DR) DEVICE ADDRESSES INSTRUCTION
High Voltage Write Cycle
Transfer Wiper Control Register (WCR) Data Register (DR) DEVICE ADDRESSES INSTRUCTION
High Voltage Write Cycle
Transfer Data Register (DR) Wiper Control Register (WCR) DEVICE ADDRESSES INSTRUCTION
Increment (I)/Decrement Wiper Control Register (WCR) DEVICE ADDRESSES INSTRUCTION DATA
Notes: write transfer Non-volatile Data Registers followed high voltage cycle after STOP been issued.
Document 2122, Rev.
CAT5261
ORDERING INFORMATION
Prefix Device 5261 Suffix -TE13
Optional Company
Product Number
Package SOIC TSSOP SOIC (Lead free, Halogen free) TSSOP (Lead free, Halogen free)
Tape Reel TE13: 2000/Reel
Resistance -50: 50kohm -00: 100kohm
Notes: device used above example CAT5261JI-50-TE13 (SOIC, Industrial Temperature, 50kohm, Tape Reel)
PACKAGING INFORMATION 24-LEAD WIDE SOIC
0.2914 (7.40) 0.2992 (7.60)
0.394 (10.00) 0.419 (10.65)
0.5985 (15.20) 0.6141 (15.60) 0.0926 (2.35) 0.1043 (2.65) 0.050 (1.27) 0.013 (0.33) 0.020 (0.51)
0.0040 (0.10) 0.0118 (0.30)
0.010 (0.25) 0.029 (0.75) 0.0091 (0.23) 0.0125 (0.32) 0.016 (0.40) 0.050 (1.27)
Dimensions inches (mm).
Document 2122, Rev.
CAT5261
PACKAGING INFORMATION CON'T Lead TSSOP
7.72
-B(1.78 TYP)
4.16
0.42 0.65
INDENT.
LEAD TIPS
LAND PATTERN RECOMMENDATION
LEAD TIPS (0.9)
-C0.10 0.05 0.65 0.19 0.30 DETAIL
GAGE PLANE
0.09 0.20
0.25
0.6+0.1
SEATING PLANE DETAIL
Dimensions
Document 2122, Rev.
REVISION HISTORY
Date 11/18/2003 5/6/2004 Rev. Reason Initial Issue Updated wiper resistance from Updated Functional Diagram Updated Description Updated notes Absolute Ratings Eliminated Commercial temp range areas Updated Potentiometer Characteristics table Updated Characteristics table Updated Capacitance table Updated Characteristics table Added XDCP Timing Table page Corrected Sychronous Data Timing (Figure drawing
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Publication Revison: Issue date:
2122 5/6/04

Dual Digitally Programmable Potentiometer (DPPTM) with Taps Interface

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