Mbit CMOS 3.3Volt-only Firmware Flash Memory Preliminary Document

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Mbit CMOS 3.3Volt-only Firmware Flash Memory Preliminary Document

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A49LF004
Mbit CMOS 3.3Volt-only Firmware Flash Memory Preliminary
Document Title Mbit CMOS Volt-only Firmware Flash Memory Revision History
History
Initial issue
Issue Date
November 2003
Remark
Preliminary
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Mbit CMOS 3.3Volt-only Firmware Flash Memory Preliminary
FEATURES
Single Power Supply Operation voltage range: Read Write Operations Standard Intel Firmware Interface Read compatible Intel® 82802 Firmware devices Memory Configuration 512K Mbit) Block Architecture 4Mbit: eight uniform 64KByte blocks Supports full chip erase Address/Address Multiplexed (A/A Mux) mode Automatic Erase Program Operation Embedded Byte Program Block/Chip Erase algorithms Typical µs/byte programming time Typical block erase time Operational Modes Firmware Interface (FWH) Mode in-system operation Address/Address Multiplexed (A/A Mux) Interface Mode programming equipment Firmware (FWH) Mode synchronous operation with 5-signal communication interface in-system read write operations Standard Command Data# Polling (I/O7) Toggle (I/O6) features Block Locking Register blocks pins multi-chip selection pins General Purpose Input Register TBL# hardware write protection Boot Block hardware write protection whole memory array except Boot Block
Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address 8-pin data interface Supports fast programming EPROM programmers Standard Command Data# Polling (I/O7) Toggle (I/O6) features Lower Power Consumption Typical 12mA active read current Typical 24mA program/erase current High Product Endurance Guarantee 100,000 program/erase cycles each block Minimum years data retention Compatible Pin-out Packaging 32-pin TSOP (TYPE 32-pin PLCC
GENERAL DESCRIPTION
A49LF004 flash memory device designed readcompatible with Intel 82802 Firmware (FWH) device PC-BIOS application. This device designed single voltage, range from Volt Volt power supply perform in-system off-system read write operations. provides protection storage update code data addition adding system design flexibility through five general-purpose inputs. interface modes supported A49LF004: Firmware (FWH) Interface mode In-System programming Address/Address Multiplexed (A/A Mux) mode fast factory programming PC-BIOS applications. memory divided into eight uniform 64Kbyte blocks that erased independently without affecting data other blocks. Blocks also protected individually prevent accidental Program Erase commands from modifying memory. Program Erase operations executed issuing Program/Erase commands into command interface which activating internal control logic automatically process Program/Erase procedures. device programmed byte-bybyte basis after performing Erase operation. addition Block Erase operation, Chip Erase feature provided mode that allows whole memory erased single Erase operation. A49LF004 provides status detection such Data# Polling Toggle Functions both modes. process completion Program Erase operations detected reading status bits. A49LF004 offered 32-lead TSOP 32-lead PLCC packages. Figures assignments Table descriptions.
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
CONFIGURATIONS
RST# (RST#)
(FGPI3)
(FGPI1) (FGPI0) (WP#) (TBL#) (ID3) (ID2) (ID1) (ID0) I/O0 (FWH0)
(FGPI4)
R/C# (CLK)
(VDD)
(FGPI2)
(IC) (VSS) (VDD) (INIT#) (FWH4) (RES) I/O7 (RES)
32-lead PLCC View
(FWH1)
(FWH2)
(FWH3)
(VSS)
(RES)
(RES)
Designates Mode
FIGURE Assignments 32-Lead PLCC
(RES)
(VSS) (IC) (FGPI4) R/C# (CLK) (VDD) RST# (RST#) (FGPI3) (FGPI2) (FGPI1) (FGPI0) (WP#) (TBL#)
Designates Mode
32-lead TSOP (8MM 14MM) View
(INIT#) (FWH4) (VDD) I/O7 (RES) I/O6 (RES) I/O5 (RES) I/O4 (RES) I/O3 (FWH3) (VSS) I/O2 (FWH2) I/O1 (FWH1) I/O0 (FWH0) (ID0) (ID1) (ID2) (ID3)
FIGURE Assignments 32-Lead TSOP
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
BLOCK DIAGRAM
FWH[3:0] FWH4 ID[3:0] FGPI[4:0] A[10:0] I/O7 I/O0 R/C# RST# Y-Decoder
Address Latch
Mode Interface
Control Logic
Input/Output Buffers
Mode Interface High Voltage Generator Data Latch
Y-Gating
X-decoder
Cell Matrix
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Table Description
Interface Symbol Name Type Descriptions Inputs addresses during Read Write operations mode. column addresses latched R/C# pin. output data during Read cycle receive input data during Write cycle mode. outputs tri-state when high. control data output buffers. control Write operations. determine which interface operational. When held high, mode enabled when held low, mode enabled. This must setup power-up before return from reset change during device operation. This internally pulled down with resistor between 20-100 This second reset in-system use. INIT# RST# pins internally combined initialize device reset when driven low. These four pins part mechanism that allows multiple devices attached same bus. identify component, correct strapping these pins must set. boot device must have ID[3:0]=0000 recommended that subsequent devices should sequential up-count strapping. These pins internally pulled down with resistor between 20-100 These individual inputs used additional board flexibility. state these pins read immediately boot, through internal registers. These inputs should their desired state before start clock cycle during which read attempted, should remain place until Read cycle. Unused FGPI pins must floated. prevent write operations Boot Block when driven low, regardless state block lock registers. When TBL# high disables hardware write protection Boot Block. This cannot left unconnected. Communications mode. provide clock input device. This same that clock adheres specifications. Input communication mode. reset operation device When low, prevents write operations highest addressable block. When high disables hardware write protection these blocks. This cannot left unconnected. This determines whether address pins pointing addresses column addresses mode. determine device busy write operations. Valid only mode. Reserved. These pins must left unconnected. provide power supply (3.0-3.6Volt). Circuit ground. pins must grounded. Unconnected pins.
A10-A0 I/O7-I/O0
Address Data Output Enable Write Enable Interface Configuration
INIT#
Initialize
ID[3:0]
Identification Inputs
FGPI[4:0]
General Purpose Inputs
TBL# FWH[3:0] FWH4 RST# R/C#
Block Lock I/Os Clock Input Reset Write Protect Row/Column Select Ready/Busy# Reserved Power Supply Ground Connection
IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C 125°C Storage Temperature -65°C 125°C D.C. Voltage Pins with Respect Ground -0.5V 0.5V Package Power Dissipation Capability (Ta=25°C) -0.5V 0.5V Output Short Circuit Current 50mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections these specifications implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Operating Ranges
Commercial Devices Ambient Temperature (TA) +85°C Supply Voltages devices +3.0V +3.6V Operating ranges define those limits between which functionally device guaranteed. when FWH4 high internal operation progress. device ready mode when FWH4 activity bus.
Notes:
Minimum voltage input pins -0.5V. During voltage transitions, input pins undershoot 2.0V periods 20ns. Maximum voltage input pins 0.5V. During voltage transitions, input pins overshoot 2.0V periods 20ns. more than output shorted time. Duration short circuit should greater than second.
MODE SELECTION
A49LF004 flash memory devices operate distinct interface modes: Firmware Interface (FWH) mode Address/Address Multiplexed (A/A Mux) mode. (Interface Configuration pin) used interface mode selection. logic High, device mode; while Low, device mode. selection must configured prior device operation. internally pulled down connected. mode, device configured interface with host using Intel's Firmware proprietary protocol. Communication between Host A49LF004 occurs 4-bit communication signals, [3:0] FWH4. mode, device programmed 11-bit address A10-A0 8-bit data I/O7-I/O0 parallel signals. address inputs multiplexed column selected control signal R/C# pin. column addresses mapped higher internal addresses, addresses mapped lower internal addresses. Device Memory Maps Figure address assignment.
Read Operation
Read operations read from memory cells specific registers device. valid Read operation starts when FWH4 rises START value "1101b" FWH[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Read operations. Refer Table Read Cycle Definition.
Write Operation
Write operations write Interface registers. valid Write operation starts when FWH4 rises START value "1110b" FWH[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Write operations. Refer Table write Cycle Definition.
Abort Operation
FWH4 driven more clock cycles during cycle, cycle will terminated device will wait ABORT command. host drive FWH[3:0] with `1111b' (ABORT command) return device Ready mode. abort occurs during Write operation, data incorrectly altered.
MODE OPERATION
interface consists four data signals (FWH[3:0]), control signal (FWH4) clock (CLK). data signals, control signal clock comply with specifications. Operations such Memory Read Memory Write Intel propriety protocol. JEDEC Standard (Software Data Protection) Byte-Program Block-Erase command sequences incorporated into memory cycles. Chip-Erase command only available mode. addresses data transferred through FWH[3:0] synchronized with input clock during memory cycle. pulse FWH4 inserted least clock period indicate start memory cycle. address data FWH[3:0] latched rising edge CLK. device enters standby mode
Response Invalid Fields
During operations, will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows: Address range: address sequence fields long bits), only last five address fields bits) will decoded A49LF004. Address special function directing reads writes flash memory (A22=1) register space (A22=0).
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Table Read Cycle
Clock Cycle Field FWH[3:0] MEMORY Descriptions FWH4 must active (low) part respond. Only last start field (before FWH4 transitioning high) should recognized. START field contents indicate read cycle. Indicates which device should respond. IDSEL select) field matches value ID[3:0], then that particular device will respond subsequent commands. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. field this size indicates many bytes will transferred during multibyte operations. this clock cycle, master (Intel ICH) driven then floats bus, prior next clock cycle. This first part "turnaround cycle." takes control during this cycle. During next clock cycle, will driven "sync data." During this clock cycle, will generate "ready-sync" (RSYNC) indicating that least-significant nibble leastsignificant byte will available during next clock cycle. YYYY least-significant nibble data byte. YYYY most-significant nibble data byte. this clock cycle, A49LF004 driven then floats prior next clock cycle. This first part "turnaround cycle." master (Intel ICH) resumes control during this cycle.
START
1101
IDSEL
0000 1111
IMADDR IMSIZE TAR0 TAR1 RSYNC DATA DATA TAR0 TAR1
YYYY 0000 byte) 1111 1111 (float) 0000 (READY) YYYY YYYY 1111 1111 (float)
then float Float then then float Float then
Single-Byte Read Waveforms
FWH4
FWH[3:0]
START
IDSEL
IMADDR
IMSIZE
TAR0
TAR1
RSYNC
DATA
TAR0
TAR1
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Table Write Cycle
Clock Cycle Field FWH[3:0] MEMORY Descriptions FWH4 must active (low) part respond. Only last start field (before FWH4 transitioning high) should recognized. START field contents indicate write cycle. Indicates which device should respond. IDSEL select) field matches value ID[3:0], then that particular device will respond subsequent commands. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. field this size indicates many bytes will transferred during multibyte operations. This field least-significant nibble data byte. This data either data programmed into flash memory valid flash command. This field most-significant nibble data byte. this clock cycle, master (Intel ICH) driven then floats bus, prior next clock cycle. This first part "turnaround cycle." A49LF004 takes control during this cycle. During next clock cycle will driving "sync" data. A49LF004 outputs values 0000, indicating that received data flash command. this clock cycle, A49LF004 driven ones then floats prior next clock cycle. This first part "turnaround cycle." master (Intel ICH) resumes control during this cycle.
START
1110
IDSEL
0000 1111
IMADDR IMSIZE DATA DATA TAR0 TAR1 RSYNC TAR0 TAR1
YYYY 0000 byte) YYYY YYYY 1111 1111 (float) 0000 1111 1111 (float)
then float Float then then float Float then
Write Waveforms
FWH4
FWH[3:0]
START
IDSEL
IMADDR
IMSIZE
DATA
TAR0
TAR1
RSYNC
TAR0
TAR1
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Invalid IMSIZE field: receives invalid size field during Read Write operation, device will reset operation will attempted. A49LF004 will generate kind response this situation. Invalid size fields Read/Write cycle anything 0000b. detection includes status bits: Data# Polling (I/O7) Toggle (I/O6). End-of-Write detection mode incorporated into Read cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (I/O7) When A49LF004 device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Proper status will given using Data# Polling address invalid range. Toggle (I/O6) During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop.
Device Memory Hardware Write Protection
Boot Lock (TBL#) Write Protect (WP#) pins provided hardware write protection device memory A49LF004. TBL# used write protect boot block Kbytes) highest flash memory address range A49LF004. write protects remaining blocks flash memory. active signal TBL# prevents Program Erase operations boot block. When TBL# held high, write protection boot block then determined Boot Block Locking register. serves same function remaining blocks device memory. TBL# pins write protection functions operate independently another. Both TBL# pins must their required protection states prior starting Program Erase operation. logic level change occurring TBL# during Program Erase operation could cause unpredictable results. TBL# pins cannot left unconnected. TBL# internally ORed with Boot Block Locking register. When TBL# low, Boot Block hardware write protected regardless state Write-Lock Boot Block Locking register. Clearing Write-Lock register when TBL# will have functional effect, even though register indicate that block longer locked. internally ORed with Block Locking register. When low, blocks hardware write protected regardless state Write-Lock corresponding Block Locking registers. Clearing WriteLock register when will have functional effect, even though register indicate that block longer locked.
Multiple Device Selection
four pins, ID[3:0], allow multiple devices attached same using different strapping system. When A49LF004 used boot device, ID[3:0] must strapped 0000, subsequent devices should sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). A49LF004 will compare strapping values, there mismatch, device will ignore remainder cycle into standby mode. further information regarding device mapping paging, please refer Intel 82801(ICH) Controller documentation. Since there support mode, program multiple devices stand-alone PROM programmer recommended.
Reset
INIT# RST# initiates device reset. INIT# RST# pins have same function internally. required drive INIT# RST# pins during system reset ensure proper initialization. During Read operation, driving INIT# RST# pins deselects device places output drivers, FWH[3:0], highimpedance state. reset signal must held minimal duration time TRSTP. reset latency will occur reset procedure performed during Program Erase operation. Table Reset Timing Parameters more information. device reset during active Program Erase will abort operation memory contents become invalid data being altered corrupted from incomplete Erase Program operation. this case, device take TRSTE abort Program Erase operation.
REGISTERS
There three types registers available A49LF004, General Purpose Inputs Register, Block Locking Registers, JEDEC Registers. These registers appear their respective address location GByte system memory map. Unused register locations will read 00H. attempt read write register during internal Write operation will ignored. Refer Table register memory map.
Write Operation Status Detection
A49LF004 device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software PRELIMINARY (November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
Table Register Memory
Memory Address FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFBC0100h FFBC0000h FFBC0001h FFBC0003h Mnemonic T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK FGPI_REG MANUF_REG DEV_REG CONT_REG Register Name Block Lock Register (Block Block [-1] Lock Register (Block Block [-2] Lock Register (Block Block [-3] Lock Register (Block Block [-4] Lock Register (Block Block [-5] Lock Register (Block Block [-6] Lock Register (Block Block [-7] Lock Register (Block General Purpose Input Register Manufacturer Register Device Register Continuation Register Default Type
General Purpose Inputs Register GPI_REG (General Purpose Inputs Register) passes state FGPI[4:0] pins power-up A49LF004. recommended that FGPI[4:0] pins desired state before FWH4 brought beginning cycle, remain that state until cycle. There default value since this pass-through register. register boot device appears FFBC0100H GByte system memory map, will appear elsewhere device boot device. Register available read when device Erase/Program operation. Table GPI_REG bits function.
Table General Purpose Inputs Register
Name FGPI[4] FGPI[3] FGPI[2] FGPI[1] FGPI[0] Function Reserved GPI_REG GPI_REG GPI_REG GPI_REG GPI_REG Number 32-PLCC 32-TSOP
Write-Lock. Write-Lock determines whether contents Block modified (using Program Erase Command). When Write-Lock `1', block write protected; operations that attempt change data block will fail Status Register will report error. When Write-Lock reset `0', block write protected through Locking Register modified unless write protected through some other means. Block Lock, TBL#, Low, VIL, then Block (Block write protected cannot modified. Similarly, Write Protect, WP#, Low, VIL, then Main Blocks (Blocks write protected cannot modified. After power-up reset Write-Lock always (write protected). Read-Lock. Read-Lock determines whether contents Block read (from Read mode). When Read-Lock `1', block read protected; operation that attempts read contents block will read instead. When Read-Lock reset `0', read operations Block return data programmed into block expected. After power-up reset Read-Lock always reset (not read protected). Lock-Down. Lock-Down provides mechanism protecting software data from simple hacking malicious attack. When Lock-Down `1', further modification Write-Lock, Read-Lock Lock-Down Bits cannot performed. reset power-up required before changes these bits made. When LockDown reset `0', Write-Lock, Read-Lock Lock-Down Bits changed.
Block Locking Registers A49LF004 provides software controlled lock protection through Block Locking registers. Block Locking Registers read/write registers accessible through standard addressable memory locations specified Table Unused register locations will read 00H.
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A49LF004
Table Lock Register Definition
Data Reserved 00000 00000 00000 00000 00000 00000 00000 00000 Read-Lock Lock-Down Write-Lock Full Access. Write locked. Default state power-up. Locked open (full access locked down). Write-locked down. Read locked. Read Write locked. Read-locked down Read- Write-locked down Function
Data Reserved Read-Lock Prevents read operations block where
Function
Normal operation reads block where clear. This default state. Lock-Down Prevents further clear operations Write-Lock Read-Lock bits. Lock-Down only clear. block will remain lock-down until reset (with RST# INIT# being Low), until device power-on reset. Normal operation Write-Lock Read-Lock altering block where clear. This default state. Write-Lock Prevents program erase operations block where set. This default state. Normal operation programming erase block where clear.
ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE
Device Operation
Commands used initiate memory operation functions device. data portion software command sequence latched rising edge WE#. During software command sequence address latched falling edge R/C# column address latched rising edge R/C#. Refer Table Table operation modes command sequence.
Byte-Program Operation
A49LF004 device programmed byte-by-byte basis. Before programming, must ensure that block, which byte which being programmed exists, fully erased. Byte-Program operation initiated executing four-byte command load sequence Software Data Protection with address data last byte sequence. During Byte-Program operation, address (A10A0) latched falling edge R/C# column Address (A21-A11) latched rising edge R/C#. data latched rising edge WE#. Figure Program operation timing diagram, Figure timing waveforms, Figure flowchart. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Read
Read operation A49LF004 device controlled OE#. output control used gate data from output pins. Refer Read cycle timing diagram, Figure further details.
Reset
RST# initiates device reset.
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A49LF004
Table Mode Operation Selection
Mode Read Write Standby Output Disable Reset Product Identification RST# Address VIL, VIL, VIH, DOUT High High High Manufacturer Device Continuation
Block-Erase Operation
Block-Erase Operation allows system erase device KByte uniform block size A49LF004. Block-Erase operation initiated executing six-byte command load sequence Software Data Protection with Block-Erase command (30H 50H) block address. internal Block-Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Block- Erase operation will ignored.
Chip-Erase
A49LF004 device provides Chip-Erase operation only mode, which allows user erase entire memory array `1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing six-byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth WE#. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored.
When A49LF004 device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Data# Polling valid after rising edge fourth pulse Program operation. Block- ChipErase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram. Proper status will given using Data# Polling address invalid range.
Data# Polling (I/O7)
Toggle (I/O6)
Write Operation Status Detection
A49LF004 device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (I/O7) Toggle (I/O6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. PRELIMINARY (November, 2003, Version 0.0)
During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth pulse Program operation. Block- Chip-Erase, Toggle valid after rising edge sixth pulse. Figure Toggle timing diagram.
Data Protection
A49LF004 device provides both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high will inhibit Write operation. This prevents inadvertent writes during powerup power-down.
AMIC Technology, Corp.
A49LF004
Software Data Protection (SDP)
A49LF004 provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequences. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. A49LF004 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC.
Electrical Specifications
specifications Interface signals (FWH[3:0], CLK, FWH4, RST#) defined Section 4.2.2 Local Specification, Rev. 2.1. Refer Table voltage current specifications. Refer specifications Table Table Clock, Read/Write, Reset operations.
Product Identification
product identification mode identifies Manufacturer Continuation Device A49LF004. Table detail information.
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A49LF004
Figure System Memory Device Memory A49LF004
System Memory (Top Bytes) FFFFFFFFh
A49LF004 Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes)
Device Memory 07FFFF TBL# 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
Block
FFF80000h
Range Additional Devices
FFC0000h
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A49LF004
Table Software Data Protection Command Definition
Command Cycles Cycle Addr
Cycle Data
Cycle Addr 5555H 5555H 5555H 5555H Data
Cycle Addr 5555H 5555H
Cycle Addr 2AAAH 2AAAH Data
Cycle Addr
Data
Addr 2AAAH 2AAAH 2AAAH 2AAAH
Data
Data 30H/50H
Block Erase Chip Erase
5555H 5555H 5555H 5555H XXXX 5555H
5555H
Byte Program Product Entry Product Exit Product Exit
2AAAH
5555H
Notes: Mode uses consecutive Write cycles complete command sequence; Mode uses consecutive cycles complete command sequence. Addresses used command decoding; other value command sequence Mode. Chip erase available Mode only. Block Erase Address. Either acceptable Block Erase. Program Byte Address; Byte data programmed. Both Product Exit commands equivalent.
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A49LF004
Operating Range Conditions Test Input Rise/Fall Time Output Load 30pF
Range Commercial
Ambient Temperature +85°C
3.0-3.6V
Table Operating Characteristics (All Interfaces)
Limits Symbol Parameter Active Current: Read Active Current: Write
Test Conditions -0.5 0.5VDD -0.5 VDD+0.5 VDD+0.5 0.3VDD 0.1VDD 0.9VDD Units Address Input=VIL/VIH, F=1/TRCMin, VDD=VDDMax(A/A Mode) OE#=VIH, WE#=VIH FWH4=0.9VDD,f=33MHz,VDD=VDDMax, other inputs 0.9VDD 0.1VDD FWH4=VIL,f=33MHz,VDD=VDDMax, other inputs 0.9VDD 0.1VDD VIN=GND VDD, VDD=VDDMax VIN=GND VDD, VDD=VDDMax VOUT=GND VDD, VDD=VDDMax VDD=VDDMax VDD=VDDMin VDD=VDDMax VDD=VDDMin IOL=1500µA, VDD=VDDMin IOH=-500µA, VDD=VDDMin
Standby Current (FWH Mode) Ready Mode Current (FWH Mode) Input Current ID[3:0] Pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Voltage Input High Voltage Input Voltage Output Voltage Output High Voltage
VIHI VILI
Notes: active while Erase Program progress. device Ready Mode when activity bus. violate processor chipset specification regarding INIT# voltage.
Table Recommended System Power-Up Timings
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Write Operation
Units
PU-WRITE
Notes: This parameter measured only initial qualification after design process change that could affect this parameter.
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A49LF004
Table Impedance (VDD=3.3V, Ta=25°C, f=1MHz, other pins open)
Parameter CI/O LPIN
Description Capacitance Input Capacitance Inductance
Test Condition VI/O
12pF 12pF 20nH
Notes: This parameter measured only initial qualification after design process change that could affect this parameter. Refer specifications.
Table Clock Timing Parameters
Symbol TCYC THIGH TLOW Parameter Cycle Time High Time Time Slew Rate (peak-to-peak) Units V/ns
Figure Waveform
TCYC THIGH Peak-to-Peak (Min) TLOW
Table Mode Read/Write Cycle Timing Parameters, VDD=3.0-3.6V
Symbol TVAL TOFF Parameter Input Time Rising Rising Data Hold Time Rising Data Valid Rising Active (Float Active Delay) Rising Inactive (Active Float Delay) Units
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A49LF004
Table Mode Interface Measurement Condition Parameters
Symbol VTEST VMAX Input Signal Edge Rate Value 1V/ns Units
Figure Input Timing Parameters
VTEST FWH[3:0] (Valid Input Data) Valid Inputs VMAX
Figure Output Timing Parameters
VTEST TVAL FWH[3:0] (Valid Output Data)
FWH[3:0] (Float Output Data) TOFF
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A49LF004
Table Mode Interface Input/Output Characteristics
Symbol Parameter Test Conditions VOUT 0.3VDD (AC) Switching Current High 0.3VDD VOUT 0.9VDD 0.7VDD VOUT (Test Point) VOUT 0.7VDD VOUT 0.6VDD (AC) Switching Current 0.6VDD VOUT 0.1VDD 0.18VDD VOUT (Test Point) slewr slewf Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT=0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 16VDD 26.7VOUT Equation 38VDD -17.1(VDD-VOUT) Equation Units V/ns V/ns
Notes: specification. specification output load used.
Table Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol TPRST TKRST TRSTP TRSTF TRST
Parameter Stable Reset Clock Stable Reset RST# Pulse Width RST# Output Float RST# High FWH4 RST# Reset During Erase Program RST# INIT# Slew Rate
Units
mV/ns
TRSTE
Notes: There will latency TRSTE reset procedure performed during Program Erase operation.
Figure Reset Timing Diagram
TKRST RST#/INIT# TRSTF FWH[3:0] TRSTE TRST
Program Erase Operation Aborted
TPRST
TRSTP
FWH4
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Figure Mode Input/Output Reference Waveforms
VIHT INPUT VILT test inputs driven VIHT (0.9VDD) logic HIGH VILT (0.1VDD) logic LOW. Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times (10% 90%) Note: VINPUT Test VOUTPUT Test IHT: VINPUT HIGH Test ILT: VINPUT Test Reference Points OUTPUT
Figure Mode Test Load Condition
TESTER
CL=30pF
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MODE CHARACTERISTICS Table Read Cycle Timing Parameters VDD=3.0-3.6V
Symbol TRST TOLZ TOHZ Parameter Read Cycle Time RST# High Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time Active Output High High-Z Output Output Hold from Address Change Units
Table Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V
Symbol TRST TCWH TOES TOEH TOEP TOET TWPH TIDA TSCE Parameter RST# High Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# Write Enable High Time High Setup Time High Hold Time Data# Polling Delay Toggle Delay Pulse Width Pulse Width High Data Setup Time Data Hold Time Product Access Exit Time Byte Programming Time Block Erase Time Chip Erase Time Units
Table Reset Timing Parameters, VDD=3.0-3.6V
Symbol TPRST TRSTP TRSTF TRST
Parameter Stable Reset RST# Pulse Width RST# Output Float RST# High FWH4 RST# Reset During Erase Program
Units
TRSTE
There will reset latency TRSTE reset procedure performed during Program Erase operation.
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A49LF004
Figure Mode Read Cycle Timing Diagram
TRSTP RST#
TRST
Address
Column Address Address Column Address
Address
R/C#
High-Z TOLZ
Data Valid
TOHZ High-Z
I/O7-I/O0
Figure Mode Write Cycle Timing Diagram
TRSTP RST#
TRST
Address Column Address
Address
R/C#
TCWH TOES
TOEH TWPH
I/O7-I/O0 High-Z
Data Valid
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A49LF004
Figure Mode Data# Polling Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
R/C#
TOEP High-Z
I/O7
Data
Data#
Data#
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
Figure Mode Toggle Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
R/C#
TOET High-Z
I/O6
Data
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
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A49LF004
Figure Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555
R/C#
TWPH
High-Z
I/O7-I/O0
Byte Program Command Input Byte Program Address Byte Program Data
Byte Program Operation Progress
Figure Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA
R/C#
TWPH
High-Z
30/50
I/O7-I/O0
Block Erase Command Input Block Address
Block Erase Operation Progress
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A49LF004
Figure Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555
R/C#
TWPH
TSCE
High-Z
I/O7-I/O0
Chip Erase Command Input
Chip Erase Operation Progress
Figure Mode Product Entry Read Timing Diagram
Three-Byte Product Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003
R/C#
TWPH
TIDA
High-Z
I/O7-I/O0
Figure Mode Product Exit Reset Timing Diagram
Three-Byte Product Exit Reset Command Sequence 5555 Address 2AAA 5555
R/C#
TWPH
High-Z
I/O7-I/O0
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A49LF004
Figure Automatic Byte Program Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: Data:
I/O7 Data I/O6 Stop Toggle?
Byte Program Completed
Byte Program Address Byte Program Data
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A49LF004
Figure Automatic Block Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: Data:
Block Erase Completed
Block Address
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A49LF004
Figure Automatic Chip Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: 5555H Data:
Chip Erase Completed
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A49LF004
Figure Product Command Flowchart
Start
Start
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: XXXXH Data:
Enter Product Mode
Exit Product Mode
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A49LF004
Ordering Information
A49LF004T
Temperature Range
Commercial (0°C +85°C)
Clock Frequency
33MHz
Package Type
PLCC TSOP (8mmX14mm)
Device Number
Mbit Flash Memory
Part
Clock Frequency (MHz)
Boot Block Location
Temperature Range
+85°C +85°C
Package Type
A49LF004TL-33
32-pin PLCC 32-pin TSOP (8mm
A49LF004TX-33
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A49LF004
Package Information PLCC Outline Dimension
unit: inches/mm
Dimensions inches
Dimensions 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075
Symbol
0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
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A49LF004
Package Information
TSOP TYPE 14mm) Outline Dimensions unit: inches/mm
Pin1
0.254 Gage Plane Detail
Detail
Dimensions inches Symbol 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003
Dimensions 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 1.00 0.22 8.00 0.50 14.00 12.40 0.60 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076
Notes: Dimension does include mold flash. Dimension does include interlead flash. Dimension does include dambar protrusion.
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Mbit CMOS 3.3Volt-only Firmware Flash Memory Preliminary Document

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