GMS81604/08 Revision History (Dec. 1998) Redraw package dime
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Semicon 8-bit Microcontrollers
GMS81604/08
Revision History (Dec. 1998)
Redraw package dimension page 5~6.
(Nov. 1998)
Operating Voltage, 2.7~5.5V extended with 2.4~5.5V. Operating Temperature, -20~80°C extended with -20~85°C. "Typical Characteristics" page unused port guidance page Revision information programming guidance, recommand using "Intelligent Mode" page chapter programming specification appendix.
(Nov. 1997)
First Edition
Second Edition Published Application Team
©1998 Semicon Co., Ltd. right reserved.
Additional information this manual served Semicon offices Korea Distributors Representatives listed address directory. Semicon reserves right make changes information here time without notice. information, diagrams other data this manual correct reliable; however, Semicon Co,. Ltd. responsible violations patents other rights third party generated this manual.
Table Contents
OVERVIEW BLOCK DIAGRAM ASSIGNMENT PACKAGES DESCRIPTIONS PORT STRUCTURES
ELECTRICAL CHARACTERISTICS MEMORY ORGANIZATION Registers Program Memory Data Memory PORTS BASIC INTERVAL TIMER TIMER/COUNTER 8-bit Timer/Counter Mode 16-bit Timer/Counter Mode 8-bit Capture Mode 16-bit Capture Mode ANALOG DIGITAL CONVERTER Converter
BUZZER FUNCTION INTERRUPTS External Interrupt
Interrupt Multiple Interrupt WATCHDOG TIMER
STOP MODE Release Stop Mode
Minimizing Current Consumption Stop Mode RESET POWER FAIL PROCESSOR OSCILLATOR CIRCUIT UNUSED PORTS GMS81608T (OTP) PROGRAMMING Using Universal programmer
Using general EPROM(27C256) programmer GMS81608T PROGRAMMING MANUAL
APPENDIX INSTRUCTION MASK ORDER SHEET
Semicon
GMS81604/08
GMS81604 GMS81608 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
OVERVIEW
Description
GMS81604/08 high-performance CMOS 8-bit microcontroller with bytes ROM. device GMS800 family. Semicon GMS81604/08 powerful microcontroller which provides highly flexible cost effective solution many embedded control applications. GMS81604/08 provides following standard features: bytes ROM, bytes RAM, lines(33 lines 40PDIP), 16-bit 8-bit timer/counter, precision analog digital converter, on-chip oscillator clock circuitry. addition, GMS81604/08 supports power saving modes reduce power consumption. Stop Mode saves contents freezes oscillator disabling other chip functions until next hardware reset external interrupt.
Features
On-chip Program Memory Bytes On-Chip Data Instruction execution time: 0.5us 8MHz 2.4V 5.5V Operating Range Operating frequency Basic Interval Timer Four 8-Bit Timer/ Counters (can used 16-bit) Four external interrupt ports Programmable Clock Buzzer Driving port Programmable I/O, Input pins, Twelve Interrupt Sources Direct Drive Output Ports 8-Channel 8-Bit On-Chip Analog Digital Converter Power Fail Processor (Noise immunity circuit) Power Down Mode (Stop Mode)
Memory Proliferation
Device Bytes Bytes
ages permit user program them once. addition program memory, configuration fuses must programmed.
GMS81604, GMS81608
In-Circuit Emulators devices CHOICE-Jr.
GMS81604 GMS81608 GMS81608T
EPROM
Development Tools
GMS800 family supported full-featured macro assembler, in-circuit emulators CHOICEJr. socket adapters device. availability devices especially useful customers expecting frequent code changes updates. devices, packaged plastic pack-
GMS81608T DIP) GMS81608T SDIP) GMS81608T PLCC) OA816A-40PD DIP) OA816A-42SD SDIP) OA816A-44PL PLCC) Macro Assembler
Socket Adapters Devices Assembler
GMS81604/08
Semicon
Device Selection Guide
size Package Ordering code
bytes
40DIP 42SDIP 44PLCC
GMS81604 GMS81604 GMS81604 GMS81608 GMS81608 GMS81608 GMS81608T GMS81608T GMS81608T
bytes
40DIP 42SDIP 44PLCC
bytes (OTP)
40DIP 42SDIP 44PLCC
Semicon
GMS81604/08
BLOCK DIAGRAM
Figure Block Diagram
GMS81604/08
Semicon
ASSIGNMENT
SDIP
PDIP
PLCC
Figure Connections
PACKAGES
Part Package Type
GMS8160X GMS8160X GMS8160X
40DIP 42SDIP 44PLCC
means 4(4K bytes) 8(8K bytes).
Semicon
GMS81604/08
PACKAGE
42SDIP
UNIT: INCH
1.470 1.450 0.190 max.
min. 0.015
0.600 0.550 0.530
0.140 0.120
0.020 0.016
0.045 0.035
0-15°
0.012 0.008
0.070
40DIP
UNIT: INCH
2.075 2.045 0.200 max.
min. 0.015
0.600 0.550 0.530
0.140 0.120
0.022 0.015
0.065 0.045
0.100
0-15°
0.012 0.008
GMS81604/08
Semicon
44PLCC UNIT: INCH
0.695 0.685 0.656 0.650 min. 0.020
0.695 0.685
0.656 0.650
0.032 0.026
0.050
0.012 0.0075
0.120 0.090 0.180 0.165
0.630 0.590
Semicon
GMS81604/08
DESCRIPTIONS
Supply voltage. Circuit Ground. TEST test purposes only. Connect RESET Reset MCU. Input inverting oscillator amplifier input internal clock operating circuit. Output from inverting oscillator amplifier. R00~R07 8-bit, CMOS, bidirectional port. output port each sink several inputs. pins that have written their Port Direction Mode Register, used outputs inputs. R10~R17 8-bit, CMOS, bidirectional port. output port each sink several inputs. pins that have written their Port Direction Mode Register, used outputs inputs. R40~R47 8-bit, CMOS, bidirectional port. output port each sink several inputs. pins that have written their Port Direction Mode Register, used outputs inputs.
addition, Port serves functions various following special features.
Port Alternate Function
R50, R51, 3-bit, CMOS, bidirectional port. output port each sink several inputs. pins that have written their Port Direction Mode Register, used outputs inputs. differs having internal pull-ups.
Port serves functions special features.
Port Alternate Function
(Square wave output Buzzer driving)
R60~R67 8-bit, CMOS, port. R60~R63 used only input, output, R64~R67 bidirectional port. output port each sink several inputs. R64~R67 pins that have written their Port Direction Mode Register, used outputs inputs.
serves functions following special features.
Port Alternate Function
(ADC (ADC (ADC (ADC (ADC (ADC (ADC (ADC
input input input input input input input input
Supply voltage ladder resistor circuit. enhance resolution analog digital converter, independent power source well possible, other than digital power source.
INT0 (External Interrupt INT1 (External Interrupt INT2 (External Interrupt INT3 (External Interrupt (External Count Input Timer/ Counter (External Count Input Timer/ Counter (Timer Clock-Out) (Timer Clock-Out)
GMS81604/08
Semicon
Port
Descriptions Primary Functions Secondary Functions
Pull-up/ Pull-down
RESET
STOP Mode
AVDD TEST RESET XOUT R00~R07 R10~R17 R40/INT0 R41/INT1 R42/INT2 R43/INT3 R44/EC0 R45/EC2 R46/T1O R47/T3O R55/BUZ R60/AN0 R61/AN1 R62/AN2 R63/AN3 R64/AN4 R65/AN5 R66/AN6 R67/AN7
Power supply Ground Power supply Test mode Reset Oscillation input Oscillation output General General General General General Input General
External interrupt External interrupt External interrupt External interrupt External count input External count input Timer output Timer output Buzzer driving output Analog Analog Analog Analog Analog Analog Analog Analog input input input input input input input input
Pull-up
Oscillation Oscillation Input Input
Last state High Last state Last state
Input
Last state
Pull-up Pull-up
Input
Last state
Input
Last state
NOTES: physically served package. When input mode selected, pull-up activated. output mode, pull-up de-activated. reset status, status R50,R51 weak high (Typ. impedance 50~100k Other impedance very high(High-Z).
Semicon
GMS81604/08
PORT STRUCTURES
R00~R07, R10~R17
DATA REG. DATA
PROTECT DIODE
DIRECTION REG. DATA PROTECT DIODE DATA
R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/EC0, R45/EC2
PMR4 DATA REG. DATA DIRECTION REG. DATA
DATA
ALTERNATE FUNCTION INT0
R46/T1O, R47/T3O, R55/BUZ
Selection (PMR4 PMR5) ALTERNATE FUNCTION DATA REG. DATA DATA DIRECTION REG. DATA
GMS81604/08
Semicon
R50,
PULL-UP RESISTOR
DATA REG. DATA
DIRECTION REG. DATA
DATA
INPUT MODE: PULL-UP RESISTOR ACTIVATED. OUTPUT MODE: PULL-UP RESISTOR DE-ACTIVATED.
R60/AN0, R61/AN1, R62/AN2, R63/AN3
DATA
Converter
Select
R64/AN4, R65/AN5, R66/AN6, R67/AN7
DATA REG. DATA DIRECTION REG. DATA
DATA Converter
Output Reset, Input, select
Select
Semicon
GMS81604/08
RESET
TEST
Pull-up Resister
OTP: P-Ch diode
STOP
GMS81604/08
Semicon
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Supply Voltage -0.3 +6.0 Storage Temperature +125 Voltage with respect Ground -0.3 +0.3 Notice: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Maximum current Maximum current into
Maximum current sunk Pin) Maximum output current sourced Pin) Maximum current Maximum current
Recommended Operating Conditions
Parameter Symbol Condition Specifications Min. Max. Unit
Supply Voltage Operating Frequency Operating Temperature
4.5~5.5V 2.4~5.5V
Semicon
GMS81604/08
Characteristics
5.0V Parameter Symbol Test Condition Specifications Min. Typ.* Max. Unit
Input High Voltage
RESET, R40~R45 R0,R1,R46,R47 R5,R6 RESET, R40~R45 R0,R1,R46,R47 R5,R6
STOP
-2mA 10mA =3~4V =4MHz =8MHz
0.8V 0.7V
-1.0
-0.4
0.2V 0.3V
Input Voltage
Output High Voltage Output Voltage Power Fail Detect Voltage Input Leakage Current Input Pull-up Current
R0,R1,R4,R5,R6 R0,R1,R4,R5,R6 RESET, RESET R50,
-5.0 -5.0 -180
-120
Power Current
Operating mode STOP mode
Hysteresis
RESET, R40~R45
Data "Typ" column unless otherwise stated. These parameters design guidance only tested.
Converter Characteristics
5.0V 5.0V, Parameter Symbol Min. Specifications Typ.* Max. Unit
Analog Input Range Non-linearity Error Differential Non-linearity Error Zero Offset Error Full Scale Error Accuracy Input Current Conversion Time Analog power supply Input Range
AVDD CONV AVDD
AVDD
Data "Typ" column unless otherwise stated. These parameters design guidance only tested.
GMS81604/08
Semicon
Characteristics
3.0V Parameter Symbol Test Condition Specifications Min. Typ.* Max. Unit
Input High Voltage
RESET, R40~R45 R0,R1,R46,R47 R5,R6 RESET, R40~R45 R0,R1,R46,R47 R5,R6
STOP
-1mA =4MHz
0.8V 0.7V
-0.5
-0.3
0.2V 0.3V -7.5
Input Voltage
Output High Voltage Output Voltage Power Fail Detect Voltage** Input Leakage Current Input Pull-up Current Power Current
R0,R1,R4,R5,R6 R0,R1,R4,R5,R6 RESET, RESET R50, Operating mode STOP mode
-3.0 -3.0
Hysteresis
RESET, R40~R45
Data "Typ" column unless otherwise stated. These parameters design guidance only tested. Power Fail Detection function available operation.
Converter Characteristics
3.0V 3.0V, Parameter Symbol Min. Specifications Typ.* Max. Unit
Analog Input Range Non-linearity Error Differential Non-linearity Error Zero Offset Error Full Scale Error Accuracy Input Current Conversion Time Analog power supply Input Range
AVDD CONV AVDD
AVDD
Data "Typ" column unless otherwise stated. These parameters design guidance only tested.
Semicon
GMS81604/08
Characteristics
2.7~5.5V, Parameter Symbol Min. Specifications Typ. Max. Unit
Main clock frequency Oscillation stabilization Time External Clock Pulse Width External Clock Transition Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width Event Counter Transition Time
INT0, INT1, INT2, INT3 RESET EC0, EC0,
Timing Chart
0.9V 0.1V
INT0, INT1 INT2, INT3
0.8V 0.2V
RESET
0.2V
EC0,
0.8V 0.2V
GMS81604/08
Semicon
TYPICAL CHARACTERISTICS
These parameters design guidance only tested.
(mA) 4MHz fXIN 8MHz ISTOP (uA)
STOP
(mA) =5.0V (mA)
=5.0V
Operating area
(MHz) -20~80
Semicon
GMS81604/08
=3.0V
(mA) =3.0V (mA)
=3.0V
GMS81604/08
Semicon index registers also have increment, decrement, compare data transfer functions they used simple accumulators.
MEMORY ORGANIZATION
GMS81604 separate address spaces Program Data Memory. Program memory only read, written GMS81608) bytes Program Memory. Data memory read written bytes including stack area.
Registers
This device registers that Program Counter (PC), Accumulator (A), Index registers (X,Y), Stack Pointer (SP) Program Status Word (PSW). Program Counter consists 16-bit register.
ACCUMULATOR REGISTER REGISTER STACK POINTER
Stack Pointer stack pointer 8-bit register used occurrence interrupts calling subroutines. stack located position within internal data memory. Data store restore sequence to(from) stack area shown Figure
Caution: stack pointer must initialized software because value undefined after reset. #03FH TXSP
Stack Address (100 ~13F
Hardware fixed. PROGRAM COUNTER PROGRAM STATUS WORD
Figure Stack Pointer
Figure Configuration Registers
Accumulator accumulator 8-bit general purpose register, used data operation such transfer, temporary saving conditional judgment, etc.
accumulator used 16-bit register with register shown below.
Program Counter: program counter 16-bit wide which consists 8-bit registers, PCH, PCL. This counter indicates address next instruction executed. reset state, program counter reset routine address (PCH: PCL: Program Status Word Program Status Word (PSW) contains several status bits that reflect current state CPU. shown Figure contains Negative flag, Overflow flag, Direct page flag, Break flag, Half Carry (for operations), Interrupt enable flag, Zero flag Carry bit.
[Carry flag This flag stores carry borrow from after arithmetic operation also changed Shift instruction rotate instruction. [Zero flag This flag when result arithmetic operation data transfer cleared other result. [Interrupt disable flag This flag enables/disables interrupts except interrupt caused Reset software
8-BIT REGISTERS "YA" 16-BIT REGISTER
Figure Configuration 16-bit register
register, register addressing modes which these index registers, register contents added specified address this becomes actual address. These modes extremely effective referencing subroutine tables memory tables.
Semicon
GMS81604/08
RESET VALUE: CARRY FLAG RECEIVES CARRY ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY FROM ADDITION OPERANDS
NEGATIVE FLAG
OVERFLOW FLAG FLAG SELECT DIRECT PAGE
FLAG
Figure (Program Status Word) Register instruction. interrupts disabled when cleared "0". This flag immediately becomes when interrupt served. instruction, cleared instruction. [Half carry flag After operation, when there carry from there borrow from ALU. This cleared except CLRV instruction, clearing with Overflow flag (V). [Break flag This flag software instruction distinguish from TCALL instruction which same vector address. [Direct page flag This flag assign direct page direct addressing mode. direct addressing mode, addressing area within zero page when this flag "0". "1", addressing area SETG instruction, cleared CLRG. [Overflow flag This flag when overflow occurs result arithmetic operation involving signs. overflow occurs when result addition subtraction exceeds +127(7F -128(80 CLRV instruction clears overflow flag. There instruction. When instruction executed, other than above, memory copy this flag. [Negative flag This flag match sign (bit status result data arithmetic operation. When instruction executed, memory copy this flag.
INTERRUPT
M(SP) (PCH)
RETI
CALL
M(SP) (PCH)
PUSH (X,Y,PSW)
M(SP) ACC.
(PSW) M(SP)
(PCL) M(SP)
M(SP) (PCL)
M(SP) (PCL)
(X,Y,PSW)
(PCL) M(SP) (PCH) M(SP)
M(SP) (PSW)
M(SP) (PCH)
(PCH) M(SP)
Figure Stack Operation
GMS81604/08
Semicon
Program Memory
16-bit program counter capable addressing bytes, this devices have bytes GMS81608) program memory space only physically implemented. Accessing location above FFFF will cause wrap-around 0000 Figure shows upper part Program Memory. After reset, begins execution from reset vector which stored address FFFE FFFF shown Figure each area assigned fixed location Program Memory. Program Memory area contains user program, Page Call (PCALL) area contains subroutine program, reduce program byte length because using bytes PCALL instead bytes CALL instruction. frequently called, more useful save program byte length.
E000H
Address
TCALL Name
FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFCCH FFCEH FFD0H FFD2H FFD4H FFD6H FFD8H FFDAH FFDCH FFDEH
TCALL15 TCALL14 TCALL13 TCALL12 TCALL11 TCALL10 TCALL9 TCALL8 TCALL7 TCALL6 TCALL5 TCALL4 TCALL3 TCALL2 TCALL1 TCALL0/
software interrupt using same address with TCALL0.
F000H
PROGRAM MEMORY
interrupt causes jump specific location, where commences execution service routine. External interrupt example, assigned location FFFA interrupt service locations spaced 2-byte interval FFF8 External Interrupt FFFA External Interrupt etc. area from FF00 FFFF going used, service location available general purpose Program Memory.
Address Vector Name
FEFFH FF00H FFBFH FFC0H FFDFH FFE0H
GMS81608
PCALL AREA TCALL AREA INTERRUPT VECTOR AREA
GMS81604
FFFFH
Figure Program Memory
Table Call (TCALL) causes jump each TCALL address, where commences execution service routine. Table Call service locations spaced 2-byte interval FFC0 TCALL15, FFC2 TCALL14, etc.
FFE0H FFE2H FFE4H FFE6H FFE8H FFEAH FFECH FFEEH FFF0H FFF2H FFF4H FFF6H FFF8H FFFAH FFFCH FFFEH
Basic Interval Timer Watch Timer Analog Digital Converter Timer/ Counter Timer/ Counter Timer/ Counter Timer/ Counter External Interrupt External Interrupt External Interrupt External Interrupt RESET
Semicon
GMS81604/08
Data Memory
Figure shows internal Data Memory space available. Data Memory divided into three groups, user RAM, control registers Stack.
Caution: Write only registers accessed manipulation instruction.
Address
DATA MEMORY (RAM)
Symbol
Power-on Reset Value
BYTES CONTROL REGISTERS STACK AREA
Figure Data Memory Internal Data Memory addresses always byte wide, which implies address space bytes including stack area. access above G-flag should before, because after reset, G-flag "0". stack pointer should initialized within software because implemented area internal data memory. control registers used Peripheral functions controlling desired operation device. Therefore these registers contain control status bits interrupt system, timer/ counters, analog digital converters, ports. control registers address Note that unoccupied addresses implemented chip. Read accesses these addresses will general return random data, write accesses will have indeterminate effect. More detail informations each register explained each peripheral sections.
R0DD R1DD R4DD R5DD R6DD PMR4 PMR5 BITR CKCTLR WDTR
Note Note Note Note
ADCM PFDR IENL IRQL IENH IRQH IEDS
00000000 00000000 00000000 -0-00 00000000 00000000 -0-00000000 -010111 -0111111 00000000 00000000 -000001 -100 000-000-00000000 00000000 00000000
Legend Unimplemented locations. Undefined value.
NOTES: write only registers accessed manipulation instruction. register BITR CKCTLR located same address. Address read BITR, written CKCTLR. Several names given same address. Refer below table.
When read Timer mode Capture Mode CDR0 CDR1 CDR2 CDR3 TDR0 TDR1 TDR2 TDR3
Address
When write
Only ADCM read.
GMS81604/08
Semicon
Control Registers GMS81604/08
Address Name
R0DD R1DD R4DD R5DD R6DD PMR4 PMR5 BITR CKCTLR WDTR TDR0/ CDR0 TDR1/ CDR1 TDR2/ CDR2 TDR3/ CDR3 ADCM PFDR IENL IRQL IENH IRQH IEDS
port data register port direction register port data register port direction register port data register port direction register port data register port direction register port data register port direction register EC2S BUZS EC0S INT3S INT2S INT1S INT0S
Basic Interval Timer data register CAP0 CAP2 WDTCL T1ST T3ST T1SL1 T3SL1 WDTON ENPCK BTCL BTS2 BTS1 BTS0
6-bit Watch Counter register T1SL0 T3SL0 T0ST T2ST T0CN T2CN T0SL1 T2SL1 T0SL0 T2SL0
Timer register/ Timer data register Capture data register Timer register/ Timer data register Capture data register Timer register/ Timer data register Capture data register Timer register/ Timer data register Capture data register ADEN ADS2 ADS1 ADS0 ADST ADSF
result data register BUCK1 INT0E INT0IF IED3H BUCK0 WDTE WDTIF INT1E INT1IF IED3L BITE BITIF INT2E INT2IF IED2H INT3E INT3IF IED2L T0IF IED1H T1IF IED1L T2IF IED0H T3IF IED0L
Legend Unimplemented locations.
NOTES: register BITR CKCTLR located same address. Address read BITR, written CKCTLR. register PFDR only implemented device, In-circuit Emulator.
Semicon
GMS81604/08
PORTS
GMS81604/08 have five ports, These ports pins multiplexed with alternate function peripheral features device. general, when initial reset state, ports used general purpose input port. pins have data direction registers which configure these pins output input. port direction register configures corresponding port output. Conversely, write corresponding specify input pin. example, even numbered output ports numbered bits input ports, write address direction register) during initial setting shown Figure
R1DD registers: 8-bit bidirectional port (address Each individually configurable input output through R1DD register (address
Port Data Register
ADDRESS: RESET VALUE: Undefined
Input/ Output data
Port Direction Register R1DD
ADDRESS: RESET VALUE: 00000000
WRITE PORT DIRECTION REGISTER
Direction select Input Output
DATA DIRECTION DATA DIRECTION
PORT
INPUT PORT OUTPUT PORT
R4DD registers: 8-bit bidirectional port (address Each individually configurable input output through R4DD register (address
addition, Port multiplexed with various special features. control register PMR4 (address controls select alternate function. After reset, this value "0", port used general ports. select alternate function such External interrupt External counter Timer clock out, write corresponding PMR4.
Port Alternate Function
Figure Example port assignment Reading data register reads status pins whereas writing will write port latch.
R0DD registers: 8-bit bidirectional port (address Each individually configurable input output through R0DD register (address
INT0 INT1 INT2 INT3
(External (External (External (External
Interrupt Interrupt Interrupt Interrupt
Port Data Register
ADDRESS: RESET VALUE: Undefined
(External Count Input Timer/ Counter (External Count Input Timer/ Counter (Timer Clock-Out) (Timer Clock-Out)
Input/ Output data ADDRESS: RESET VALUE: 00000000
Port Direction Register R0DD
Regardless direction register R4DD, PMR4 selected alternate functions, port used corresponding alternate features.
Direction select Input Output
GMS81604/08
Semicon
Port Data Register
ADDRESS: RESET VALUE: Undefined
Input/ Output data
R5DD registers: 3-bit bidirectional port (address R50, only physically implemented this device. R50, have internal pullups which activated input deactivated output. input, these pins that externally pull will source current characteristics) because internal pullups.
Caution: Pins R50, present 42SDIP, 44PLCC package only, 40DIP Refer assignment.
Port Direction Register R4DD
ADDRESS: RESET VALUE: 00000000
Direction select Input Output
Each individually configurable input output through R5DD register (address
Port Alternate Function
Port Mode Register PMR4
ADDRESS: RESET VALUE: 00000000
(Square-wave output Buzzer driving)
EC2S EC0S INT3S INT2S INT1S INT0S
INT3
INT0 INT1
control register PMR5 (address controls selection alternate function. After reset, this value "0", port used general ports. buzzer function, write PMR5.
Port Data Register
INT2
ADDRESS: RESET VALUE: Undefined
Input/ Output data
Edge Selection Register IEDS
INT3 INT2
ADDRESS: RESET VALUE: 00000000 INT1 INT0
Port Direction Register R5DD
ADDRESS: RESET VALUE: -0-00
External Interrupt Edge select Reserved Falling (1-to-0 transition) Rising (0-to-1 transition) Both (Rising Falling)
Direction select Input Output
Port Mode Register PMR5
BUZS
ADDRESS: RESET VALUE:
(Buzzer Port)
Semicon R6DD registers: 8-bit port (address CCH). Pins R64~R67 individually configurable input output through R6DD register (address CDH), pins R60~R63 input only.
Port Alternate Function (ADC input (ADC input (ADC input (ADC input (ADC input (ADC input (ADC input (ADC input
GMS81604/08
Port Data Register
ADDRESS: RESET VALUE: Undefined
Input/ Output data
Port Direction Register R6DD
ADDRESS: RESET VALUE: 0000-
R6DD (address CDH) controls direction pins, even when they being used analog inputs. user must make sure keep pins configured inputs when using them analog inputs.
initial RESET, used digital input port, because this port selected analog input port ADCM register. this port digital port, change value lower bits ADCM (address 0E8H). other hand, port, eight pins used digital port simultaneousely. least used analog input.
Fixed Input. write. Direction select Input Output
GMS81604/08 Basic interval timer.
Semicon
BASIC INTERVAL TIMER
GMS81604 8-bit Basic Interval Timer that free-run, stop. Block diagram shown Figure 8-bit Basic interval timer register (BITR) incremented every internal count pulse which divided prescaler. Since prescaler divided ratio 2048, count rate 1/16 1/2048 oscillator frequency. count overflows from this overflow causes generate Basic interval timer interrupt. BITR interrupt request flag
Caution: control bits Basic interval timer CKCTLR register which located same address BITR (address Address read BITR, written CKCTLR.
When write BTCL CKCTLR, data register cleared restart count-up. becomes after machine cycle hardware.
BTS[2:0]
BTCL CLEAR
÷128 ÷256 ÷512 ÷1024 ÷2048
PRESCALER
BITR BITS)
BITIF
BASIC INTERVAL TIMER INTERRUPT
Figure Block Diagram Basic Interval Timer
CKCTLR
ENPCK
BTCL
BTS2
BTS1
BTS0
ADDRESS: RESET VALUE: -010111
Symbol
WDTON ENPCK BTCL
Position
CKCTLR.5 CKCTLR.4 CKCTLR.3
Name Significance
WDTON=1, enables Watch Timer operation, WDTON=0, operates 6-bit timer Enable Peripheral clock. BTCL "1", BITR cleared. BTCL becomes automatically after machine cycle, starts counting.
BASIC INTERVAL TIMER CLOCK SELECTION BTS2 BTS1 BTS0 Prescale value 1024 2048
Figure CKCTLR: Control Clock Register
Semicon
GMS81604/08 "16-bit timer/counter", "8-bit capture", "16-bit capture" which selected Timer mode register shown right Table. operation Timer Timer their operations same with Timer Timer respectively.
TIMER TIMER CAP0
T1SL1 T1SL0
TIMER/COUNTER
GMS81604 four Timer/Counter registers. Each module generate interrupt indicate that event occurred (i.e. timer match). Timer Timer used either 8-bit Timer/Counter 16-bit Timer/Counter combine them. Also Timer Timer same. "timer" function, register incremented every internal clock input. Thus, think counting internal clock input. Since least clock consists most clock consists oscillator periods, count rate 1/64 oscillator frequency. "counter" function, register incremented response 1-to-0 (falling edge) transition corresponding external input pin, EC2. addition "capture" function, register incremented response external internal clock sources same with timer counter function. When external clock edge input, count register captured into Timer data register correspondingly. four operating modes: "8-bit timer/counter",
Timer
Timer
16-bit Timer/Counter 16-bit Capture 8-bit Timer 8-bit Capture 8-bit Timer 8-bit Timer
TIMER TIMER CAP2
T3SL1 T3SL0
Timer
Timer
16-bit Timer/Counter 16-bit Capture 8-bit Timer 8-bit Capture 8-bit Timer 8-bit Timer
T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 ADDRESS: RESET VALUE:
Figure
CAP0
TIMER T0ST
TIMER When set, Timer Count Register cleared start again. When cleared, stop counting. Start/Stop control Timer logic starts timer.
CAP0
Capture mode selection flag, When set, timer operate 16-bit capture timer combine 8-bit timers. When set, Timer count register cleared start again. When cleared, stop counting.
T1ST
T0CN
TIMER T1SL1 T1SL0 INPUT CLOCK 16-BIT TIMER MODE (NOTE 8-BIT TIMER, PRESCALER 8-BIT TIMER, 8-BIT TIMER,
TIMER T0SL1 T0SL0 INPUT CLOCK Timer Counter select PRESCALER
NOTE: this mode selected, Timer used 16-bit timer mode. Timer engaged Timer source clock selected bits T0SL1 T0SL0.
Figure TM0: Timer Timer Mode Register
GMS81604/08
Semicon
T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0 ADDRESS: RESET VALUE:
CAP2
TIMER CAP2 Capture mode selection flag, When set, timer operate 16-bit timer combine 8-bit timers. Figure Figure When set, Timer count register cleared start again. When cleared, stop counting. T2ST
TIMER When set, Timer count register cleared start again. When cleared, stop counting. Start/Stop control Timer logic starts timer.
T3ST
T2CN
TIMER T3SL1 T3SL0 INPUT CLOCK 16-BIT TIMER MODE (NOTE 8-BIT TIMER, PRESCALER 8-BIT TIMER, 8-BIT TIMER,
TIMER T2SL1 T2SL0 INPUT CLOCK Timer Counter select PRESCALER
NOTE: this mode selected, Timer Timer used 16-bit timer mode. Timer engaged Timer source clock selected bits T2SL1 T2SL0.
Figure TM2: Timer Timer Mode Register
ADDRESS: RESET VALUE: ADDRESS: RESET VALUE: ADDRESS: RESET VALUE: ADDRESS: RESET VALUE:
TDR0 TDR1 TDR2 TDR3
Figure TDRx Timer Data Register
Semicon
GMS81604/08 until matches TDR0 then reset match output Timer generates Timer interrupt (latched T0IF bit) TDRx register same address, when reading written TDRx.
Caution: contents Timer data register TDRx should initialized except because undefined after reset.
8-bit Timer/Counter Mode
GMS81604 four 8-bit Timer/Counters, Timer Timer Timer Timer Timer Timer only shown Figure because other timer/counters same with Timer Timer "timer" "counter" function selected control registers TM0, shown Figure Figure 8-bit timer/counter mode, CAP0 cleared bits T1SL1, T1SL0 bits T3SL1, T3SL0 should zero (Figure 16). These timers have each 8-bit count register data register. count register incremented every internal external clock input. internal clock prescaler divide ratio option (selected control bits TxSL1, TxSL0 register TMx). Timer timer register increments from
counter function, counter incremented every 1-to (falling edge) transition pin. order counter function, EC0S, EC2S Port mode register PMR4 "1". Timer used counter input, Timer not. Similarly, Timer used input Timer not.
CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 ADDRESS: T0SL0 RESET VALUE:
T0SL[1:0] EDGE DETECTOR
T0ST Stop Clear Start (8-BITS) CLEAR
PRESCALER
T0CN T0IF COMPARATOR TIMER INTERRUPT
TIMER
TDR0 (8-BITS)
T1SL[1:0]
T1ST Stop Clear Start
(8-BITS)
CLEAR
T1IF
TIMER
COMPARATOR TDR1 (8-BITS)
TIMER INTERRUPT
Figure 8-bit Timer/Counter Mode
GMS81604/08 pulse out, timer match goes port shown Figure Thus, pulse generated timer match. These operation implemented pin, T3O. output from Timer from Timer Operation omitted this document, still presents same architecture with T1O.
Semicon
rFrequency
Prescaler
EC2S EC0S INT3S INT2S INT1S INT0S ADDRESS: RESET VALUE:
PMR4
EC2S
(TIMER OUTPUT) (TIMER OUTPUT) TIMER TIMER
INT3S INT2S INT1S
INT3 (EXTERNAL INTERRUPT INT2 (EXTERNAL INTERRUPT INT1 (EXTERNAL INTERRUPT INT0 (EXTERNAL INTERRUPT
EC0S
INT0S
Figure PMR4: Port Mode Register
When TM0: 00110111 (PRESCALER= TDR0: OSCILLATOR FREQ.= 4MHz INTERRUPT PERIOD
(249
COUNT PULSE PERIOD
MATCH (TDR0 TDR0
CLEAR CLEAR CLEAR TIME
TIMER INTERRUPT
OCCUR INTERRUPT INTERRUPT PERIOD
OCCUR INTERRUPT
OCCUR INTERRUPT
Figure Timer Count Example
Semicon
GMS81604/08 Even Timer (including Timer used 16-bit timer, Timer Timer still used either 8-bit timer 16-bit timer setting TM2. Reversely, even Timer (including Timer used 16-bit timer, Timer Timer still used 8-bit timer independently.
16-bit Timer/Counter Mode
Timer register being with bits. 16-bit timer/counter register incremented from 0000 until matches TDR0, TDR1 then resets 0000 match output generates Timer interrupt. clock source Timer selected either internal external clock T0SL1, T0SL0.
T1ST T1SL1 T1SL0 T0ST T0CN T0ST Stop Clear Start (8-BITS) (8-BITS) CLEAR T0SL1 T0SL0 ADDRESS: RESET VALUE:
CAP0 T0SL[1:0]
CARE
EDGE DETECTOR
PRESCALER
T0CN
T0IF
TIMER INTERRUPT
TIMER
THIS FIGURE EXAMPLE TIMER TIMER TIMER EACH REGISTERS FLAGS CHANGED CORRESPONDINGLY.
(+TIMER1) TDR1 (8-BITS) HIGHER TDR0 (8-BITS) LOWER
COMPARATOR
(NOT TIMER INTERRUPT)
Figure 16-bit Timer/Counter Mode
TDR0
MATCH Restart Stop Clear Start
MATCH
Stop
Count
CLEAR CLEAR CLEAR TIME
TIMER INTERRUPT
OCCUR INTERRUPT
OCCUR INTERRUPT
HIGH TxST HIGH TxCN
Figure Timer Count Operation
GMS81604/08
Semicon input INTx causes current value Timer register (T0,T2), captured into registers CDRx (CDR0, CDR2), respectively. After captured, Timer register cleared restarts hardware.
Caution: CDRx TDRx same address. capture mode, reading operation read CDRx, TDRx because path opened CDRx.
8-bit Capture Mode
Timer capture mode CAP0 timer mode register (bit CAP2 timer mode register Timer shown Figure this mode, Timer still operates 8-bit timer/counter. mentioned above, only Timer Timer also used capture mode. 8-bit capture mode, Timer Timer used capture mode. Timer/Counter register incremented response internal external input. This counting function same with normal timer mode, Timer interrupt generated. Timer/Counter still does above, with added feature that edge transition external
three transition modes: "falling edge", "rising edge", "both edge" which selected interrupt edge selection register IEDS (Refer External interrupt section). addition, transition INTx generate interrupt.
CAP0 T1ST T1SL1 T1SL0 T0ST T0ST Stop Clear Start T0CN T0SL1 ADDRESS: T0SL0 RESET VALUE:
T0SL[1:0]
EDGE DETECTOR
(8-BITS) T0CN CAPTURE CDR0 (8-BITS) THIS FIGURE EXAMPLE TIMER TIMER EACH REGISTERS FLAGS CHANGED CORRESPONDINGLY.
PRESCALER
IEDS[1:0]
INT0
INT0IF
INT0 INTERRUPT
Figure 8-bit Capture Mode
Semicon
GMS81604/08
16-bit Capture Mode
16-bit capture mode same 8-bit capture, except that Timer register being will bits.
CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 ADDRESS: T0SL0 RESET VALUE:
CARE T0SL[1:0] EDGE DETECTOR (8-BITS) (8-BITS) THIS FIGURE EXAMPLE USING TIMER TIMER TIMER TIMER EACH REGISTERS FLAGS CHANGED. CDR1 (8-BITS) HIGHER CDR0 (8-BITS) LOWER INT0IF INTERRUPT T0ST Stop Clear Start
PRESCALER
T0CN
IEDS[1:0]
TIMER TIMER
INT0
Figure 16-bit Capture Mode
GMS81604/08 direction register.
Semicon
ANALOG DIGITAL CONVERTER
analog-to-digital converter (A/D) allows conversion analog input signal corresponding 8-bit digital value. module eight analog inputs, which multiplexed into sample hold. output sample hold input into converter, which generates result successive approximation. analog supply voltage connected ladder resistance module. module registers which control register ADCM result register ADR. register ADCM, shown Figure controls operation converter module. port pins configured analog inputs digital I/O. analog inputs, selected input mode R6DD
Converter
processing conversion start when start ADST "1". After cycle, cleared hardware. register contains results conversion. When conversion completed, result loaded into ADR, conversion status ADSF "1", interrupt flag set. block diagram module shown Figure status ADSF automatically when conversion completed, cleared when conversion process. conversion time takes maximum MHz).
ADEN ADS[2:0] LADDER RESISTOR DECODER
R60/AN0 R61/AN1 R62/AN2 R63/AN3 R64/AN4 R65/AN5 R66/AN6 R67/AN7
SAMPLE HOLD
SUCCESSIVE APPROXIMATION CIRCUIT
INTERRUPT
ADDRESS: RESET VALUE: Undefined
RESULT REGISTER INPUT CHANNEL SELECTION
Figure Block Diagram
Semicon
GMS81604/08
ADS2 ADS1 ADS0 ADST
ADSF ADDRESS: RESET VALUE: -00001
ADCM
ADEN
status conversion process. conversion completed, process.
RESERVED
start Setting this starts conversion. After cycle, cleared "0". force zero. Analog channel select 000: channel (R60/AN0) 001: channel (R61/AN1) 010: channel (R62/AN2) 011: channel (R63/AN3) 100: channel (R64/AN4) 101: channel (R65/AN5) 110: channel (R66/AN6) 111: channel (R67/AN7) converter Enable converter module shut consumes operating current. Enable converter
Figure ADCM: Converter Control Register
GMS81604/08
Semicon
BUZZER FUNCTION
buzzer driver consists 6-bit binary counter, buzzer register clock selector. generates square-wave which very wide range frequency (250 Hz~125 MHz) user programmable counter. assigned output port Buzzer driver setting PMR5 (address "1". this time, must defined output mode (the R5DD=1) determines output frequency buzzer driving. Frequency calculation following below. fXIN Prescaler ratio value
COUNTER BIT)
PRESCALER
BUR[7:6] BUR[5:0] BIT) REGISTER
Figure Buzzer Driver
6-bit buzzer counter cleared start counting writing signal register BUR. increment from until matches 6-bit register BUR.
Caution: register contains undefined value after reset. must initialized none
Buzzer frequency oscillator frequency Prescaler: Prescaler divide ratio BUCK1, BUCK0 BUR:Lower 6-bit BUR. Buzzer period data value
bits BUCK1, BUCK0 selects source clock from prescaler output.
ADDRESS: RESET VALUE: Undefined
BUCK1 BUCK0
Buzzer Period Data
Buzzer Source Clock Selection
Figure BUR: Buzzer Period Data Register
BUZS ADDRESS: RESET VALUE:
PMR5
R55/ Port Selection
Figure PMR5: Port Mode Register
Semicon
GMS81604/08 External Interrupts INT0~INT3 each transition-activated, depending interrupt edge selection register. Timer 0~Timer Interrupts generated T0IF ~T3IF, which match their respective timer/counter register. converter Interrupt generated which finishing analog digital conversion. Watch timer Interrupt generated WDTIF which match Watch timer register. Basic Interval Timer Interrupt generated BITIF which overflow timer/counter register. interrupts controlled interrupt master enable flag I-flag (bit PSW), interrupt enable register (IENH, IENL) interrupt request flags IRQH, IRQL) except Power-on reset software interrupt. Interrupt enable registers shown Figure These registers composed interrupt enable flags each interrupt source, these flags determines
INTERRUPTS
GMS81604/08 interrupt circuits consist Interrupt enable register (IENH, IENL), Interrupt request flags IRQH, IRQL, priority circuit Master enable flag(I flag PSW). configuration interrupt circuit shown Figure interrupt sources provided including Reset.
Interrupt source Symbol Priority
Hardware RESET External Interrupt External Interrupt External Interrupt External Interrupt Timer/Counter Timer/Counter Timer/Counter Timer/Counter Converter Watch timer Basic interval timer
INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF WDTIF BITIF
*Vector addresses shown Program Memory section.
IRQH INT0 INT1 INT2 INT3 TIMER TIMER TIMER TIMER INT0IF INT1IF INT2IF INT3IF
IENH I-flag PSW, cleared "DI", "EI" instruction. When goes interrupt service, I-flag cleared hardware, thus other interrupt inhibited. When interrupt service completed "RETI" instruction, I-flag hardware.
(Software Interrupt) T0IF T1IF T2IF T3IF IRQL BASIC INTERVAL TIMER WDTIF BITIF IENL RELEASE STOP STOP MODE)
PRIORITY CONTROL
I-FLAG Master Enable Flag
RESET
Figure Block Diagram Interrupt Function
GMS81604/08
Semicon
INT1E INT2E INT3E ADDRESS: RESET VALUE:
IENH
INT0E
WDTE BITE ADDRESS: RESET VALUE: 000-
IENL
Enables disables interrupt individually. flag cleared, interrupt disabled. Disable Enable
Figure IENH, IENL: Interrupt Enable Registers whether interrupt will accepted not. When enable flag "0", corresponding interrupt source prohibited. Note that contains also master enable bit, I-flag, which disables interrupts once. When interrupt responded I-flag cleared disable further interrupt, return address pushed into stack vectored Once interrupt service routine source(s) interrupt determined polling interrupt flag bits. interrupt flag bit(s) must cleared software before reenabling interrupts avoid recursive interrupts. Interrupt Request flags able read write. port mode register PMR4. PMR4 IEDS registers shown Figure
EDGE DETECTOR IEDS[1:0] INT0 INT0IF INT0 INTERRUPT IEDS[3:2] INT1 INT1IF INT1 INTERRUPT
IEDS[5:4] INT2 INT2IF INT2 INTERRUPT IEDS[7:6] INT3 INT3IF INT3 INTERRUPT
External Interrupt
External interrupt INT0~INT3 pins edge triggered depending edge selection register IEDS. edge detection external interrupt three transition activated mode: rising edge, falling edge, both edge. INT0~INT3 multiplexed with general ports (R40~R43). external interrupt pin,
Figure External Interrupt
Semicon
GMS81604/08
MAX.
INTERRUPT ACTIVE INSTRUCTION EXECUTION (INTERRUPT HOLDING) INTERRUPT PROCESSING INTERRUPT ROUTINE
Figure Interrupt Timing
EC2S EC0S INT3S INT2S INT1S INT0S ADDRESS: RESET VALUE:
PMR4
Relation with Timer/Counter Function EC2S (TIMER/COUNTER OUTPUT) (TIMER/COUNTER OUTPUT) (EXTERNAL INPUT TIMER/COUNTER (EXTERNAL INPUT TIMER/COUNTER
Relation with External Interrupt function INT3S INT2S INT1S INT3 (EXTERNAL INTERRUPT INT2 (EXTERNAL INTERRUPT INT1 (EXTERNAL INTERRUPT INT0 (EXTERNAL INTERRUPT
EC0S
INT0S
IED3L IED2H IED2L IED1H IED1L IED0H IED0L ADDRESS: RESET VALUE:
IEDS
IED3H
INT3
INT2
INT1
INT0
Edge selection register Reserved Falling (1-to-0 transition) Rising (0-to-1 transition) Both (Rising Falling)
Figure PMR4 IEDS Registers
GMS81604/08
Semicon
Interrupt
Software interrupt invoked instruction, which lowest priority order. Interrupt vector address shared with vector TCALL0 (Refer Program Memory Section). When interrupt generated, B-flag distinguish from TCALL0. Each processing step determined B-flag shown below.
Multiple Interrupt
requests different priority levels received simultaneously, request higher priority level serviced. requests same priority level received simultaneously, internal polling sequence determines hardware which request serviced. Hardware interrupt priority shown Page37. However, multiple processing through software special features possible. Generally when interrupt accepted, I-flag cleared disable further interrupt. user I-flag interrupt routine, some further interrupt serviced even certain interrupt progress.
B-FLAG TCALL0
this example, INT0 interrupt serviced without pending, even TIMER progress. Because re-setting interrupt enable registers IENH, IENL master enable flag "EI" Timer/Counter routine. TCALL0 ROUTINE
MAIN ROUTINE TIMER ROUTINE ROUTINE
INTERRUPT ROUTINE
RETI
IENH,#80H IENL,#00H
Occur TIMER INTERRUPT
INT0 ROUTINE
Figure Execution BRK/ TCALL0
IENH,#FFH IENL,#FFH RETI
RETI
Figure Execution Multi-Interrupt
Semicon
GMS81604/08
WATCHDOG TIMER
purpose watchdog timer detect malfunction (runaway) program external noise other causes return operation normal condition. watchdog timer consists 6-bit binary counter, 6-bit comparator watchdog timer data register. When value 6-bit binary counter equal lower bits WDTR, match generated reset CPU. 6-bit binary counter cleared WDTCL=1.
WDTCL
Caution: Because watchdog timer counter enabled after clearing Basic Interval Timer After WDTON "1", maximum error timer depend prescaler ratio Basic Interval Timer.
This watchdog timer also used simple 6-bit timer interrupt WDTIF. interval watchdog timer interrupt decided Basic Interval Timer. Interval equation below. WDTR Interval
BASIC INTERVAL TIMER OVERFLOW COUNT SOURCE
WATCHDOG COUNTER (6-BITS)
CLEAR
NOTE: WDTON register CKCTLR. Figure
COMPARATOR WDTON WDTR[5:0] (6-BITS) WATCHDOG TIMER REGISTER RESET
WDTIF WATCH-DOG TIMER INTERRUPT
Figure Block Diagram Watch-dog Timer
WDTCL
WDTR
6-bit Watch-dog count register
ADDRESS: RESET VALUE: Undefined
Reserved
WDTCL Free-run Watch-dog Timer WDTCL "1", Counter cleared. WDTCL becomes automatically after machine cycle, Counter starts counting.
Figure WDTR: Watch-dog Timer Data Register
GMS81604/08
Semicon restored normal operating level, must held active long enough allow oscillator restart stabilize (minimum msec).
Caution: instruction have written more than next line STOP instruction. STOP
STOP MODE
applications where power consumption critical factor, device provides reduced power STOP. instruction that STOP causes that last instruction executed before going into Stop mode. Stop mode, on-chip oscillator stopped. With clock frozen, functions stopped, on-chip Control registers held. port pins values held their respective port data register port direction register RxDD. status peripherals during Stop mode shown below.
Peripheral Status
Release Stop Mode
Control registers Oscillation Retain Retain Retain Stop High
exit from Stop mode hardware reset external interrupt. Reset redefines Control registers does change on-chip RAM. External interrupts allow both on-chip Control registers retain their values. I-flag normal interrupt response takes place. I-flag chip will resume execution starting with instruction following STOP instruction. will vector interrupt service routine. When exit from Stop mode external interrupt from Stop mode, enough oscillation stabilization time required normal operation. Figure shows timing diagram. When release Stop mode,
Stop mode operation, reduced minimize power consumption. Care must taken, however, ensure that reduced before Stop mode invoked, that restored normal operating level, before Stop mode terminated. reset should activated before
OSCILLATOR
INTERNAL CLOCK
EXTERNAL INTERRUPT
BASIC INTERVAL TIMER COUNTER
STOP INSTRUCTION EXECUTION
CLEAR BASIC INTERVAL TIMER
NORMAL OPERATION
STOP MODE
STABILIZATION TIME
NORMAL OPERATION
Figure Timing Stop Release External Interrupt
Semicon
GMS81604/08
Wake-up Reset Function Table
Event Chip Status before event Chip function after event Oscillator Circuit
RESET STOP instruction External Interrupt External Interrupt Wake-up
care Normal operation Normal operation Stop, I-flag Stop, I-flag
Vector Vector Vector
Program Counter contents after event. Address STOP instruction.
Basic interval timer activated wake-up. incremented from until then count overflow start normal operation. Therefore, before STOP instruction, user must relevant prescaler divide ratio have long enough time (more than 20msec). This guarantees that crystal oscillator started stabilized. reset, exit from Stop mode shown Figure
inimizing Current Consumption Stop Mode
Stop mode designed reduce power consumption. minimize current drawn during Stop mode, user should turn-off output drivers that sourcing sinking current, practical. Weak pull-ups port pins should turned off, possible. inputs should either close rail possible). intermediate voltage input causes input buffer draw significant amount current.
STOP MODE
OSCILLATOR
INTERNAL CLOCK
RESET STABILIZATION TIME Time control software.
STOP INSTRUCTION EXECUTION
Figure Timing Stop Mode Release Reset
GMS81604/08
Semicon
RESET
reset input RESET pin, which input Schmitt Trigger. reset accomplished holding RESET least oscillator periods, while oscillator running. After reset, 64ms MHz) plus oscillator periods required start execution shown Figure Internal affected reset. When turned content indeterminate. Initial state each register follow. Therefore, this should initialized before reading testing
R0DD R1DD R4DD R5DD R6DD PMR4 PMR5
Register
Content
00000000 00000000 00000000 -0-00 00000000 00000000 -0-00H -010111 -0111111 -000001 -100 000-00H 000-00H
OPERATION RESET 10uF 7042 4.2V RESET
BITR CKCTLR WDTR TDR0/ TDR1/ TDR2/ TDR3/ ADCM PFDR IENH IENL IRQH IRQL IEDS
CDR0 CDR1 CDR2 CDR3
Figure Example Reset circuit
unimplemented unknown
OSCILLATOR
RESET
ADDRESS
FFFE
FFFF
Start
DATA
Code
STABILIZATION TIME
RESET PROCESS STEP
MAIN PROGRAM
Figure Timing Diagram after Reset
Semicon
GMS81604/08
POWER FAIL PROCESSOR
GMS81604/08 have on-chip power fail detection circuitry immunize against power noise. configuration register, PFDR, enable clear/programmed) disable set) Power-fail Detect circuitry. falls below 3.0~4.0V range longer than Power fail situation reset according PFDR.
Caution: Power fail processor function available operation, because this function will detect power fail time.
below PFDR register implemented in-circuit emulator, user experiment with Therefore, after final development user program, this function experimented.
Power Fail Status Normal operate This force when Power fail detected. Operation Mode Normal operation regardless power fail. will reset during power fail. Disable flag Power fail detection enable Power fail detection disable
PFDR
ADDRESS: RESET VALUE: -100
Reserved
Figure PFDR: Power Fail Detector Register
RESET VECTOR
CLEAR INITIALIZE DATA
INITIALIZE PORTS INITIALIZE REGISTERS
Skip initial routine.
FUNCTION EXECUTION
Figure Example Reset flow Power Fail
GMS81604/08
Semicon
MAX. MIN. Internal Reset
When Internal Reset MAX. MIN.
MAX. MIN.
Internal Reset
Figure Power Fail Processor Situations
Semicon
GMS81604/08
OSCILLATOR CIRCUIT
input output, respectively, inverting amplifier which configured on-chip oscillator, shown Figure
RESET
Recommend: C1,C2 Crystals.
Figure Layout Crystal Oscillation circuit designed used either with ceramic resonator crystal oscillator. Since each crystal ceramic resonator have their characteristics, user should consult crystal manufacturer appropriate values external components. addition, Figure layout crystal. cases, external clock operation available.
Figure Oscillator Connections drive device from external clock source, should left unconnected while driven shown Figure There requirements duty cycle external clock signal, since input internal clocking circuitry through divide-by-two flip-flop, minimum maximum high times specified data sheet must observed.
EXTERNAL OSCILLATOR SIGNAL
Figure External Clock Drive Configuration
GMS81604/08
Semicon voltage level applied input pin, there little current max. around flow. appropriate input mode, then output mode considering there current flow. Setting High decided considering relationship with external circuit. example, there external pull-up resistor then output mode, i.e. High, there external pull-down register, low.
UNUSED PORTS
unused ports should properly that current flow through port does exist. First conseider setting input mode. sure that there current flow after considering relationship with external circuit. input mode, impedance viewing from external very high that current does flow. input voltage level should careful that unspecified voltage, i.e. unfirmed
Semicon
GMS81604/08 these socket adapters, GMS81608T easy programming verifying using 27C256 EPROM mode general-purpose PROM programmer. assembler file type, files generated after compiling. "*.HEX", another "*.OTP". "*.HEX" file used emulation circuit emulator (CHOICE-Dr CHOICE-Jr "*.OTP" file used programming device.
GMS81608T (OTP) PROGRAMMING
GMS81608T one-time PROM (OTP) microcontroller with bytes electrically programmable read only memory GMS81604/08 system evaluation, first production fast mass production. programming device, user have way. using universal programmer which support microcontrollers, other using general EPROM programmer.
Programming Procedure
Select EPROM device manufacturer EPROM programmer (Intel 27C256). Select programming algorithm Intelligent mode (apply writing pulse), Quick pulse mode. Load file (*.OTP) programmer. programming address range below table.
Address Value
Using Universal programmer
Third party universal programmer support program GMS81608T microcontrollers lists shown below.
Manufacturer: site: http://www.aec.com.tw Programmer: LabTool-48 Manufacturer: site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08
Socket adapters supported third party programmer manufacturer.
Buffer start address Buffer address
6000 7FFF 6000
Using general EPROM(27C256) programmer
programming algorithm simmilar with standart EPROM 27C256. give some convience that user standard EPROM programmer. Make sure that programming pulse must used, generally called "Intelligent Mode". 100us programming pulse mode, "Quick Pulse Mode". When user general EPROM programmer, socket adaper essencially required. convert general 27C256 EPROM. Three type socket adapters provided according package variation below table.
Socket Adapter Package Type
Device start address
Mount socket adapter with GMS81608T PROM programmer. Start PROM programmer programming/ verifying.
OA816A-40SD OA816A-42SD OA816A-42PL
SDIP PLCC
GMS81608T PROGRAMMING MANUAL
Semicon
GMS81608T PROGRAMMING SPECIFICATION
GMS815045T PACKAGE
DEVICE NAME GMS81608T GMS81608T GMS81608T
PACKAGE 40DIP 42SDIP 44PLCC
CONFIGURATION
40DIP
GMS81608T PROGRAMMING SPECIFICATION
Semicon
42SDIP
44PLCC
Semicon
GMS81608T PROGRAMMING SPECIFICATION
40DIP Package GMS81608T
Mode Mode Mode Mode
NOTES:
TEST R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R47/T3O R46/T1O R45/EC2 R44/EC0 R43/INT3 R42/INT2 R41/INT1 R40/INT0 R55/BUZ
RESET XOUT
Pins must connected because these pins input ports during programming, program verify reading Pins must connected must opened during programming.
I/O: Input/Output Input Output
GMS81608T PROGRAMMING SPECIFICATION
Semicon
42SDIP Package GMS81608T
Mode Mode Mode Mode
NOTES:
TEST R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R47/T3O R46/T1O R45/EC2 R44/EC0 R43/INT3 R42/INT2 R41/INT1 R40/INT0 R55/BUZ
RESET XOUT
Pins must connected because these pins input ports during programming, program verify reading Pins must connected must opened during programming.
I/O: Input/Output Input Output
Semicon
GMS81608T PROGRAMMING SPECIFICATION
44PLCC Package GMS81608T
Mode Mode Mode Mode
NOTES:
N.C. TEST R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R47/T3O R46/T1O R45/EC2 R44/EC0 R43/INT3 N.C. R42/INT2 R41/INT1 R40/INT0 R55/BUZ
N.C. N.C.
RESET XOUT
Pins must connected because these pins input ports during programming, program verify reading Pins must connected must opened during programming.
I/O: Input/Output Input Output
GMS81608T PROGRAMMING SPECIFICATION
Semicon
FUNCTION (OTP Mode)
(Program Voltage) input program voltage programming EPROM. Chip Enable) input programming verifying internal EPROM. (Output Enable) input data output control signal verify. (Address Bus) address input pins internal EPROM. (EPROM Data Bus) These data internal EPROM.
PROGRAMMING
GMS81608T address pins. Therefore, programmer just program bytes data addresses 6000 7FFF into GMS81608T device. During programming addresses programmer must pulled logic high. When programmer write data from 6000 7FFF consequently, data actually will written into addresses E000 FFFF device.
Programming Flow
data format programmed made Motorola format. "Motorola format; S00B00005741544348363038DF S1057FF2941FD6 S1057FFEFF1F5F S9030000FC Down load above data into programmer from Programming data from address 6000 7FFF into MCU, data must turned over respectively, then record data into device. When read data, also must turned over. 00(00000000) FF(11111111), 76(01110110) 89(10001001), (11111111)00(00000000) etc. course, check result whole data from address 6000 7FFF file (not reverse data MCU). When GMS81608T shipped, blank data GMS81608T initially (not
Semicon
GMS81608T PROGRAMMING SPECIFICATION
Programming Flow
Buffer Start Address: 6000 Buffer Address: 7FFF Device Start Address: E000
GMS81608T
xxxxxxxx.OTP
Address E000 Program Verify Reading
Universal Programmer
Address 6000
Program area BYTES
Down Loading
File Type: Motorola S-format
FFFF
7FFF
Programming Example
GMS81608T device
Programmer Buffer
File xxxxxxxx.OTP
Data
Address E000 E001 E002 E003 E004 E005 E006 E007 FFF2 FFF3 FFFE FFFF
Data
Address 6000 6001 6002 6003 6004 6005 6006 6007 7FF2 7FF3 7FFE 7FFF
Data
Address 6000 6001 6002 6003 6004 6005 6006 6007 7FF2 7FF3 7FFE 7FFF
Program
Down Loading
Reading Verify
Loading
Checksum E1+FF+3B+FF+04+A1+3F+8F+ 94+1F+ +FF+1F
GMS81608T PROGRAMMING SPECIFICATION
Semicon
DEVICE OPERATION MODE
Mode A0~A15
Read Output Disable Programming Program Verify
NOTES: Either
5.0V 5.0V
DOUT Hi-Z DOUT
Characteristics Table voltages during programming.
CHARACTERISTICS
Symbol Item Unit Test condition
NOTES:
supply voltage supply voltage supply current supply current Input high voltage Input voltage Output high voltage Output voltage Input leakage current
12.0 5.75
13.0 6.25
CE=V
-1.0
-2.5
must applied simultaneously before removed simultaneously after maximum current value with outputs unloaded.
Semicon
GMS81608T PROGRAMMING SPECIFICATION
SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must steady
steady
change from change from care change permitted
changing from changing from Changing state unknown Center line high impedance "Off" state
Does apply
READING WAVEFORMS
Addresses
Address Valid
High-Z
Output
Valid Output
NOTES: input timing reference level 4.0V =5.0V read output data, transition requires from high after address setup time
GMS81608T PROGRAMMING SPECIFICATION
Semicon
PROGRAMMING ALGORITHM WAVEFORMS
Program
Program Verify
Addresses
Address Stable
Data Stable High-Z Data Valid
Data
12.5V
6.0V
5.0V
NOTES:
input timing reference level 4.0V =5.0V
Semicon
GMS81608T PROGRAMMING SPECIFICATION
READING CHARACTERISTICS
Symbol Item Unit Test condition
NOTES:
Address setup time Data output delay time Data hold time
must applied simultaneously before removed simultaneously after
PROGRAMMING CHARACTERISTICS
Characteristics Table voltages.)
Symbol Item Unit Condition* (Note
Address set-up time set-up time Data setup time Address hold time Data hold time Output disable delay time setup time setup time Program pulse width pulse width when over programming Data output delay time
0.95 2.85 1.05 78.75
(Note
CONDITIONS TEST Input Rise Fall Times (10% Input Pulse Levels Input Timing Reference Level Output Timing Reference Level NOTES:
90%)
0.45V 4.55V 1.0V 4.0V 1.0V 4.0V
must applied simultaneously before removed simultaneously after length overprogram pulse vary from 2.85 msec 78.75 msec function iteration counter value (Intelligent Programming Algorithm).Refer flow chart page
GMS81608T PROGRAMMING SPECIFICATION
Semicon
Intelligent Programming Algorithm
START
ADDRESS= FIRST LOCATION
6.0V 12.5V
PROGRAM PULSE
INCREMENT
FAIL VERIFY BYTE PASS VERIFY BYTE PASS
FAIL
PROGRAM PULSE msec DURATION
INCREMENT ADDRESS
LAST ADDRESS 5.0V
COMPARE BYTES ORIGINAL DATA PASS
FAIL
DEVICE PASSED
DEVICE FAILED
APPENDIX
GMS800 Series
INSTRUCTION
Terminology List
Terminology #imm !abs .bit A.bit dp.bit M.bit upage Accumulator register register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Position Position Accumulator Position Direct Page Memory Position Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
Position
Description
Upper Nibble Expression Opcode
Position
Upper Nibble Expression Opcode
Subtraction Multiplication Division Contents Expression Exclusive Assignment Transfer Shift Left Shift Right Exchange Equal Equal
GMS800 Series
Instruction
00000 HIGH
00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 SET1 dp.bit,re #imm dp.bit A.bit,rel #imm #imm #imm #imm #imm #imm dp,#im dp+X dp+X dp+X dp+X dp+X dp+X dp+X dp+X !abs !abs !abs !abs !abs !abs !abs !abs TCALL SETA1 .bit PUSH PUSH
CLRC
TCALL CLRA1 .bit TCALL NOT1 M.bit
CLRG
PUSH PCALL Upage PUSH TXSP
TCALL CMPX OR1B
CLRV
TCALL AND1 CMPY CBNE AND1B dp+X TCALL EOR1 DBNE EOR1B TCALL LDCB TCALL M.bit dp+X dp+Y dp+Y
SETC
TSPX
SETG
STOP
10000 HIGH
10001 10010 CLR1
dp.bit
10011
10100
10101
10110
10111
11000 !abs !abs !abs !abs !abs !abs !abs !abs
11001 dp+X dp+X dp+X dp+X dp+X dp+X dp+X dp+X
11010 TCALL
11011 !abs
11100 !abs TEST !abs
11101 ADDW SUBW
11110 #imm #imm
11111 [!abs] [dp] CALL [dp] RETI
A.bit,rel dp.bit,rel
!abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y !abs+Y [dp+X] [dp]+Y
TCALL CALL !abs TCALL
TCLR1 CMPW CMPX !abs #imm LDYA CMPY #imm
TCALL DBNE CMPX !abs TCALL TCALL TCALL TCALL {X}+ {X}+
CMPY INCW !abs !abs !abs DECW STYA CBNE
GMS800 Series
Instruction
Arithmetic Logic Operation
Mnemonic
#imm !abs !abs #imm !abs !abs !abs #imm !abs !abs CMPX #imm CMPX CMPX !abs CMPY #imm CMPY CMPY !abs
Code
Byte
Cycle
Arithmetic shift left
Operation
with carry. A(A)+(M)+C
Flag
NVGBHIZC
NV-H-ZC
Logical (A)(M) N-Z-
N-ZC
Compare accumulator contents with memory con- N-ZC tents -(M)
Compare contents with memory contents (X)-(M) Compare contents with memory contents (Y)-(M) Complement Decimal adjust addition Decimal adjust subtraction Decrement N-ZC N-ZN-ZC N-ZC N-ZC N-ZC
GMS800 Series
Mnemonic
!abs #imm !abs !abs !abs !abs #imm !abs !abs !abs !abs #imm
Code
Byte
Cycle
Logical shift right Increment (M)+1 (M)-1
Operation
Flag
NVGBHIZC N-ZN-ZN-ZN-ZN-Z-
Divide Exclusive (A)(M)
NV-H-Z-
N-Z-
N-ZC N-ZN-ZN-ZN-ZN-ZN-ZC
Multiply Logical (A)(M)
N-Z-
N-Z-
Rotate left through Carry
N-ZC
Rotate right through Carry
N-ZC
Subtract with Carry
GMS800 Series
Mnemonic
!abs !abs
Code
Byte
Cycle
Operation
Flag
NVGBHIZC
NV-HZC
Test memory contents negative zero, N-Z00H Exchange nibbles within accumulator A7~A4 A3~A0 N-Z-
GMS800 Series
Register Memory Operation
Mnemonic
#imm !abs !abs dp,#imm #imm !abs #imm !abs !abs !abs !abs !abs TSPX TXSP
Code
Byte
Cycle
Load Y-register Y(M) Load accumulator A(M)
Operation
Flag
NVGBHIZC
N-Z-
register auto-increment Load memory with immediate data Load X-register N-Z-
N-Z-
Store accumulator contents memory (M)A
register auto-increment Store X-register contents memory Store Y-register contents memory Transfer accumulator contents X-register Transfer accumulator contents Y-register Transfer X-register contents accumulator: Transfer X-register contents stack-pointer: Transfer Y-register contents accumulator: -N-ZN-ZN-ZN-ZN-Z-
Transfer stack-pointer contents X-register N-Z-
Exchange X-register contents with accumulator
GMS800 Series
dp+X
Exchange Y-register contents with accumulator Exchange memory contents with accumulator (M)A N-Z-
Exchange X-register contents with Y-register
16-BIT operation
Mnemonic
ADDW CMPW DECW INCW LDYA STYA SUBW
Code
Byte
Cycle
Operation
16-Bits without Carry Compare contents with memory pair contents (YA) (dp+1)(dp) Decrement memory pair dp+1)( dp+1) Increment memory pair dp+1) dp+1) Load Store 16-Bits subtract without carry
Flag
NVGBHIZC NV-H-ZC N-ZC N-ZN-ZN-Z-NV-H-ZC
Manipulation
Mnemonic
AND1 M.bit AND1B M.bit !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit M.bit LDCB M.bit NOT1 M.bit M.bit OR1B M.bit
Code
Byte
Cycle
Operation
C-flag .bit C-flag .bit test with memory Clear M.bit Clear A.bit Clear C-flag Clear G-flag Clear V-flag exclusive-OR C-flag .bit exclusive-OR C-flag .bit) Load C-flag .bit Load C-flag with .bit complement .bit .bit C-flag .bit C-flag .bit
Flag
NVGBHIZC MM-Z-
-0-0-0-C
GMS800 Series
SET1 dp.bit SETA1 A.bit SETC SETG M.bit TCLR1 !abs TSET1 !abs
M.bit A.bit C-flag G-flag Store C-flag .bit Test clear bits with Test bits with A-(M), (M)(A)
-1-N-ZN-Z-
viii
GMS800 Series
Branch Jump Operation
Mnemonic
A.bit,rel dp.bit,rel A.bit,rel dp.bit,rel CALL !abs
Code
Byte
Cycle
Branch clear
Operation
then Branch then Branch carry clear then Branch carry then Branch equal then Branch minus then Branch equal then Branch minus then Branch always Branch overflow clear then Branch overflow then Subroutine call
Flag
NVGBHIZC
CALL [dp]
sp)( spsp M(sp) (pcL), !abs, [dp], dp+1 Compare branch equal then rel. Decrement branch equal then rel. Unconditional jump jump address U-page call M(sp) M(sp) upage "0FFH" Table call (sp) M(sp) ),sp (Table vector (Table vector
CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel !abs [!abs] [dp] PCALL upage
TCALL
GMS800 Series
Control Operation Etc.
Mnemonic Code Byte Cycle Operation
Software interrupt "1", M(sp) (pcH), sp-1, M(s) (pcL), M(sp) (PSW), 0FFDEH 0FFDFH) Disable interrupts Enable interrupt operation Return from subroutine Return from interrupt Stop mode halt CPU, stop oscillator restored -restored
Flag
NVGBHIZC
-1-0-
PUSH PUSH PUSH PUSH
-0-1-
RETI STOP
MASK ORDER VERIFICATION SHEET
GMS81604-HC
Customer should write inside thick line box. Customer Information Company Name Application
YYYY
Device Information Package 40DIP 44PLCC Mask Data File Name: Hitel Check Sum:
0000H "FF" this area
42SDIP
Order Date Tel: Name Signature: Fax:
.OTP)
Chollian Internet
6FFFH 7000H
(4K)
Marking Specification S81604 KOREA
7FFFH
(Please check mark into
Customer's part
Delivery Schedule Date
YYYY
Quantity
Confirmation
Customer Sample
YYYY
Risk Order
Code Verification
YYYY
This written after "5.Verification".
YYYY
Verification ate:
Please confirm verification data.
Approval Date:
agree your verification data confirm set.
Check Sum: Tel: Name Signature: Fax:
Tel: Name Signature:
Fax:
Semicon
MASK ORDER VERIFICATION SHEET
GMS81608-HC
Customer should write inside thick line box. Customer Information Company Name Application
YYYY
Device Information Package 40DIP 44PLCC Mask Data File Name: Hitel Check Sum:
0000H "FF" this area
42SDIP
Order Date Tel: Name Signature: Fax:
.OTP)
Chollian Internet
5FFFH 6000H
(8K)
Marking Specification S81608 KOREA
7FFFH
(Please check mark into
Customer's part
Delivery Schedule Date
YYYY
Quantity
Confirmation
Customer Sample
YYYY
Risk Order
Code Verification
YYYY
This written after "5.Verification".
YYYY
Verification ate:
Please confirm verification data.
Approval Date:
agree your verification data confirm set.
Check Sum: Tel: Name Signature: Fax:
Tel: Name Signature:
Fax:
Semicon
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