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Intel® Advanced+ Boot Block Flash Memory C3

28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)

Intel® Advanced+ Boot Block Flash Memory (C3)
28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)
Datasheet
Product Features
Flexible SmartVoltage Technology - 2.7 V- 3.6 V read / program / erase - 12 V for fast production programming 1.65 V to 2.5 V or 2.7 V to 3.6 V I / O Option - Reduces overall system power High Performance - 2.7 V- 3.6 V: 70 ns max access time Optimized Architecture for Code Plus Data Storage - Eight 4 Kword blocks, top or bottom parameter boot - Up to 127 x 32 Kword blocks - Fast program suspend capability - Fast erase suspend capability Flexible Block Locking - Lock / unlock any block - Full protection on power-up - Write Protect(WP#) pin for hardware block protection Low Power Consumption - 9 mA typical read - 7 uA typical standby with Automatic Power Savings feature Extended Temperature Operation - -40 °C to +85 °C
128-bit Protection Register - 64 bit unique device identifier - 64 bit user programmable OTP cells Extended Cycling Capability - Minimum 100, 000 block erase cycles Software - Intel® Flash Data Integrator - Supports top or bottom boot storage, streaming data (for example, voice) - Intel Basic Command Set - Common Flash Interface Standard Surface Mount Packaging - 48-Ball µBGA / VFBGA - 64-Ball Easy BGA packages - 48-TSOP package ETOX VIII (0.13 µm) Flash Technology - 8, 16, 32 Mbit ETOX VII (0.18 µm) Flash Technology - 16, 32, 64 Mbit ETOX VI (0.25 µm) Flash Technology - 8, 16 and 32 Mbit
Order Number: 290645, Revision: 022 January 2005
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Contents
1.0 Introduction..................................................................7 1.1 1.2 2.0 2.1 2.2 2.3 3.0 3.1 3.2 3.3 4.0 4.1 4.2 4.3 5.0 5.1 5.2 6.0 6.1 6.2 7.0 7.1 7.2 7.3 7.4 7.5 8.0 8.1 8.2 8.3 8.4 8.5 Nomenclature ............................................................7 Conventions.............................................................7 Product Overview .........................................................8 Block Diagram ...........................................................9 Memory Map .............................................................9 mBGA and VF BGA Package..............................................12 TSOP Package ..........................................................13 Easy BGA Package ......................................................14 48-Lead TSOP Package ...................................................15 64-Ball Easy BGA Package ................................................18 Signal Descriptions .......................................................18 Absolute Maximum Ratings ................................................20 Operating Conditions .....................................................20 Current Characteristics ....................................................22 DC Voltage Characteristics.................................................24 AC Read Characteristics ..................................................25 AC Write Characteristics...................................................29 Erase and Program Timings ................................................33 AC I / O Test Conditions ....................................................33 Device Capacitance......................................................34 Active Power (Program / Erase / Read).........................................35 Automatic Power Savings (APS) ............................................35 Standby Power ..........................................................35 Deep Power-Down Mode..................................................35 Power and Reset Considerations ............................................36 8.5.1 Power-Up / Down Characteristics ......................................36 8.5.2 RP# Connected to System Reset .....................................36 8.5.3 VCC, VPP and RP# Transitions ......................................36 8.5.4 Reset Specifications ...............................................37 Power Supply Decoupling..................................................37
Functional Overview ...........................................................8
Package Information ..........................................................12
Ballout and Signal Descriptions ................................................15
Maximum Ratings and Operating Conditions......................................20
Electrical Specifications .......................................................22
AC Characteristics ...........................................................25
Power and Reset Specifications ................................................35
Device Operations ............................................................39
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Bus Operations .......................................................... 39 9.1.1 Read ........................................................... 39 9.1.2 Write ........................................................... 39 9.1.3 Output Disable .................................................... 39 9.1.4 Standby......................................................... 40 9.1.5 Reset ........................................................... 40 Read Mode ............................................................. 41 10.1.1 Read Array....................................................... 41 10.1.2 Read Identifier .................................................... 41 10.1.3 CFI Query ....................................................... 42 10.1.4 Read Status Register............................................... 42 10.1.4.1 Clear Status Register....................................... 43 Program Mode .......................................................... 43 10.2.1 12-Volt Production Programming...................................... 43 10.2.2 Suspending and Resuming Program................................... 44 Erase Mode ............................................................ 44 10.3.1 Suspending and Resuming Erase ..................................... 45 Flexible Block Locking .................................................... 49 11.1.1 Locking Operation................................................. 50 11.1.1.1 Locked State ............................................. 50 11.1.1.2 Unlocked State............................................ 50 11.1.1.3 Lock-Down State.......................................... 50 Reading Block-Lock Status................................................. 50 Locking Operations during Erase Suspend .................................... 51 Status Register Error Checking ............................................. 51 128-Bit Protection Register................................................. 51 11.5.1 Reading the Protection Register...................................... 52 11.5.2 Programming the Protection Register.................................. 52 11.5.3 Locking the Protection Register....................................... 52 VPP Program and Erase Voltages ........................................... 52 11.6.1 Program Protection................................................ 53
10.0 Modes of Operation........................................................... 41 10.1
11.0 Security Modes .............................................................. 49 11.1
Appendix A Write State Machine States...............................................54 Appendix B Flow Charts ...........................................................56 Appendix C Common Flash Interface.................................................62 Appendix D Additional Information ..................................................70 Appendix E Ordering Information....................................................71
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Revision History
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
January 2005 5
Intel® Advanced+ Boot Block Flash Memory (C3)
Date of Revision
Version Updated 64Mb product offerings. Updated 16Mb product offerings.
Description
Revised and corrected DC Characteristics Table. Added mechanicals for Easy BGA. Minor text edits throughout document.
Complete technical update. Corrected information in the Device Geometry Details table, address 0x34. Updated the layout of the datasheet. Fixed typo for Standby power on cover page. Added lead-free line items to Table 37 "Product Information Ordering Matrix" on page 72. Added specification for 8Mb 0.13 micron device. Added 0.13 micron to Table 37 "Product Information Ordering Matrix" on page 72. Converted datasheet to new template. Deleted Description in Table 4. Deleted Note in Figure 5.
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Introduction
This datasheet contains the specifications for the Intel® Advanced+ Boot Block Flash Memory (C3) device family, hereafter called the C3 flash memory device. These flash memories add features such as instant block locking and protection registers that can be used to enhance the security of systems.
Nomenclature
0x 0b Byte Word KW or Kword Mword Kb KB Mb MB APS CSP CUI OTP PR PRD PLR RFU SR SRD WSM Hexadecimal prefix Binary prefix 8 bits 16 bits 1024 words 1, 048, 576 words 1024 bits 1024 bytes 1, 048, 576 bits 1, 048, 576 bytes Automatic Power Savings Chip Scale Package Command User Interface One Time Programmable Protection Register Protection Register Data Protection Lock Register Reserved for Future Use Status Register Status Register Data Write State Machine
Conventions
The terms pin and signal are often used interchangeably to refer to the external signal connections on the package for chip scale package (CSP) the term ball is used. Group Membership Brackets: Square brackets will be used to designate group membership or to define a group of signals with similar function (i.e. A21:1, SR4:1) Set: When referring to registers, the term set means the bit is a logical 1. Clear: When referring to registers, the term clear means the bit is a logical 0. Block: A group of bits (or words) that erase simultaneously with one block erase instruction. Main Block: A block that contains 32 Kwords. Parameter Block: A block that contains 4 Kwords.
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Functional Overview
This section provides an overview of the Intel® Advanced+ Boot Block Flash Memory (C3) device features and architecture.
Product Overview
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 1.
Block Diagram
C3 Flash Memory Device Block Diagram
DQ 0-DQ 15
VCCQ Output Buffer Input Buffer
Outp ut M ulti ple xer
Status Register
Da ta Re gi ster
Identifier Register
I / O Logic CE# WE# OE# RP# WP#
Power Reduction Control
Data Comparator
Command User Interface
AMAX:MIN
Y-Decoder Input Buffer 4 -KWor d Para mete r B loc k
Y-Gating / Sensing 4 -KWor d Para mete r B loc k 32- KWord M ain Blo ck
Write State Machine 32- KWord M ain Blo ck
Program / Erase Voltage Switch
Address Latch
X-Decoder
VCC GND
Address Counter
Memory Map
The Intel® Advanced+ Boot Block Flash Memory (C3) device is asymmetrically blocked, which enables system code and data integration within a single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. See Table 1, "Top Boot Memory Map" on page 10 and Table 2, "Bottom Boot Memory Map" on page 11 for details.
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 1.
Size (KW) Blk
Top Boot Memory Map
8-Mbit Memory Addressing (Hex) 7F0007FFFF 7E0007EFFF 7D0007DFFF 7C0007CFFF 7B0007BFFF 7A0007AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF .. 10000-17FFF 8000-0FFFF 0000-07FFF Size (KW) Blk 16-Mbit Memory Addressing (Hex) FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF .. 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) Blk 32-Mbit Memory Addressing (Hex) 1FF0001FFFFF 1FE0001FEFFF 1FD0001FDFFF 1FC0001FCFFF 1FB0001FBFFF 1FA0001FAFFF 1F90001F9FFF 1F80001F8FFF 1F00001F7FFF 1E80001EFFFF 1E00001E7FFF 1D80001DFFFF .. 10000-17FFF 08000-0FFFF 00000-07FFF Size (KW) Blk 64-Mbit Memory Addressing (Hex)
3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF .. 10000-17FFF 08000-0FFFF 00000-07FFF
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 2.
Bottom Boot Memory Map
8-Mbit Memory Addressing (Hex) 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF .. 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32 32 32 32 .. 32 32 32 4 4 4 4 4 4 4 4 Blk 16-Mbit Memory Addressing (Hex) F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF .. 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32 32 32 32 .. 32 32 32 4 4 4 4 4 4 4 4 Blk 32-Mbit Memory Addressing (Hex) 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF .. 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Size (KW) 32 32 32 32 . 32 32 32 4 4 4 4 4 4 4 4 Blk 64-Mbit Memory Addressing (Hex) 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF .. 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 2.
Package Information
µBGA and VF BGA Package
µBGA and VF BGA Package Drawing and Dimensions
Ball A1 Corner
Top View - Bump Side down
Bottom View -Bump side up
A 1 A2 A Seating Plan
Side View
Note: Drawing not to scale
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M (.25) Package Body Length 16M (.25 / .18 / .13) 32M (.25 / .18 / .13) Package Body Length 64M (.18) Package Body Width 8M (.25) Package Body Width 16M (.25 / .18 / .13) 32M (.18 / .13) Package Body Width 32M (.25) Package Body Width 64M (.18) Pitch Ball (Lead) Count 8M, 16M Ball (Lead) Count 32M Ball (Lead) Count 64M Seating Plane Coplanarity Corner to Ball A1 Distance Along D 8M (.25) Corner to Ball A1 Distance Along D 16M (.25 / .18 / .13) 32M (.18 / .13) Corner to Ball A1 Distance Along D 64M (.18) Corner to Ball A1 Distance Along E 8M (.25) Corner to Ball A1 Distance Along E 16M (.25 / .18 / .13) 32M (.18 / .13) Corner to Ball A1 Distance Along E 32M (.25) Corner to Ball A1 Distance Along E 64M (.18)
Min 0.150 0.325 7.810 7.186 7.600 6.400 6.864 10.750 8.900
Millimeters Nom Max 1.000 0.665 0.375 7.910 7.286 7.700 6.500 6.964 10.850 9.000 0.750 46 47 48 1.330 1.018 1.225 1.375 1.607 3.550 2.625
Min 0.0059
Inches Nom
Max 0.0394
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 3.
TSOP Package
TSOP Package Drawing and Dimensions
See Notes 1, 2, 3 and 4
e E See Detail B
A1 Seating Plane
See Detail A
Detail A Detail B
A5568-02
Dimensions
Notes: 1. One dimple on package denotes Pin 1. 2. If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 4.
Easy BGA Package
Easy BGA Package Drawing and Dimension
Ball A1 Corner Ball A1 Corner
Top View - Ball side down
Bottom View - Ball Side Up
Seating Plane
Note: Drawing not to scale
Side View
Dimensions Table
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Symbol A A1 A2 b D E e N Y S1 S2 Millimeters Min Nom 0.250 0.330 9.900 12.900 0.780 0.430 10.000 13.000 1.000 64 1.500 3.000 0.530 10.100 13.100 Max 1.200 Notes Inches Min 0.0098 0.0130 0.3898 0.5079 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0591 0.1181 0.0209 0.3976 0.5157 Nom Max 0.0472
Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change.
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Ballout and Signal Descriptions
The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA packages. See Figure 5 on page 15, Figure 7 on page 17, and Figure 8 on page 18, respectively.
Figure 5.
48-Lead TSOP Package
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
Advanced+ Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 6.
Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-Mb and 32-Mb TSOP
Current M ark:
New M ark:
Note:
The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel® Advanced and Advanced + Boot Block 48L TSOP products will convert to a white ink triangle as a Pin 1 indicator. Products without the white triangle will continue to use a dimple as a Pin 1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability. Product will continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes shown in Table 3. 48-Lead TSOP
Extended 64 Mbit Extended 32 Mbit Extended 16 Mbit Extended
Table 3.
TE28F640C3TC80 TE28F640C3BC80
TE28F320C3TD70 TE28F320C3BD70 TE28F320C3TC70 TE28F320C3BC70 TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110
TE28F160C3TD70 TE28F160C3BD70 TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110
TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 7.
48-Ball µBGA and 48-Ball VF BGA Chip Scale Package (Top View, Ball Down)1, 2, 3
WE# 64M
RP# 32M A21
Notes: 1. Shaded connections indicate the upgrade address connections. Intel recommends to not use routing in this area. 2. A19 denotes 16 Mbit A20 denotes 32 Mbit A21 denotes 64 Mbit. 3. Unused address balls are not populated.
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 8.
64-Ball Easy BGA Package
64-Ball Easy BGA Package1, 2
2 A6 3 A18 4 VPP 5 6 7 8 A VCC GND A10 A15 B A17 A19(1) RP# DU A20(1) A11 A7 A5 WP# WE# DU A21(1) A12 DU DU DU DU A8 DU A14 C A13 D A9 E DQ8 DQ1 DQ9 DQ3 DQ12 DQ6 F CE# DQ0 DQ10 DQ11 DQ5 DQ14 DU G A0 H A22(2) OE# VCCQ VCC VSSQ DQ7 VCCQ DU VSSQ DQ2 DQ4 DQ13 DQ15 VSSQ A16 H DU VCCQ D7 VSSQ VCC VCCQ OE# A22(2) DU G A16 VSSQ D15 D13 DQ4 DQ2 VSSQ A0 DU F DU DU DQ14 DQ5 DQ11 DQ10 DQ0 CE# DU DU DQ6 DQ DQ3 DQ9 DQ1 DQ8 12 A9 A8 DU DU DU DU A5 A4 A13 A12 A21(1) DU WE# WP# A7 A3 A14 A11 A20(1) DU RP# A19(1) A17 A2 A15 A10 GND VCC VPP A18 A6 A1 8 7 6 5 4 3 2 1
Top View Ball Side -
Bottom View - Ball Side
Notes: 1.A19 denotes 16 Mbit A20 denotes 32 Mbit A21 denotes 64 Mbit. 2. Unused address balls are not populated.
Table 4.
Symbol
Signal Descriptions
AMAX:0
Input
DQ15:0
Input
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 4.
Symbol
Signal Descriptions
Type Description RESET / DEEP POWER-DOWN: Active-low input.
Input
When RP# is at logic low, the device is in reset / deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on the rising edge of the WE# pulse. WRITE PROTECT: Active-low input.
Input
When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. When WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to the lock-down state. See Section 11.0, "Security Modes" on page 49 for details on block locking.
DEVICE CORE Power Supply: Supplies power for device operations. OUTPUT Power Supply: Output-driven source voltage. This ball can be tied directly to VCC if operating within VCC range. Ground: For all internal circuitry. All ground inputs must be connected. Do Not Use: Do not use this ball. This ball must not be connected to any power supplies, signals or other balls, it must be left floating. No Connect
VCC VCCQ GND DU NC
Power Power Power - -
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These ratings are stress ratings only. Operation beyond the "Operating Conditions" is not recommended, and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Parameter
Maximum Rating
Notes
Extended Operating Temperature During Read During Block Erase and Program Temperature under Bias Storage Temperature Voltage On Any Pin (except VCC and VPP) with Respect to GND VPP Voltage (for Block Erase and Program) with Respect to GND VCC and VCCQ Supply Voltage with Respect to GND Output Short Circuit Current -40 °C to +85 °C -40 °C to +85 °C -40 °C to +85 °C -65 °C to +125 °C -0.5 V to +3.7 V -0.5 V to +13.5 V -0.2 V to +3.6 V 100 mA 4 1 1, 2, 3
Table 5.
Operating Conditions
Temperature and Voltage Operating Conditions
Symbol Parameter Notes Min Max Units
TA VCC1 VCC2 VCCQ1 VCCQ2 VCCQ3 VPP1
Operating Temperature VCC Supply Voltage 1, 2 1, 2 1 I / O Supply Voltage
°C Volts
Volts
Supply Voltage
Volts
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Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 5.
Temperature and Voltage Operating Conditions
Symbol Parameter Notes Min Max Units
VPP2 Cycling Block Erase Cycling
Volts Cycles
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Electrical Specifications
Current Characteristics
Table 6.
DC Current Characteristics (Sheet 1 of 2)
Parameter
VCCQ Note
Input Load Current
Output Leakage Current VCC Standby Current for 0.13 and 0.18 Micron Product
VCC Standby Current for 0.25 Micron Product VCC Power-Down Current for 0.13 and 0.18 Micron Product
VCC Power-Down Current for 0.25 Product VCC Read Current for 0.13 and 0.18 Micron Product VCC Read Current for 0.25 Micron Product
VPP Deep PowerDown Current
VCC Program Current
VCC Erase Current
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 6.
DC Current Characteristics (Sheet 2 of 2)
VCC 2.7 V-3.6 V 2.7 V-3.6 V Typ Max 2.7 V-2.85 V 1.65 V-2.5 V Typ Max 2.7 V-3.3 V 1.8 V-2.5 V Typ Max Unit Test Conditions
Parameter
VCCQ Note
ICCES / ICCWS
VCC Erase Suspend Current for 0.13 and 0.18 Micron Product 1, 4, 5 VCC Erase Suspend Current for 0.25 Micron Product VPP Read Current 1, 4
VPP Program Current
VPP Erase Current
0.2 IPPES / IPPWS VCC Erase Suspend Current 1, 4 50
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 7.
DC Voltage Characteristics
VCC 2.7 V-3.6 V 2.7 V-3.6 V Min Max 2.7 V-2.85 V 1.65 V-2.5 V Min Max 2.7 V-3.3 V 1.8 V-2.5 V Min Max Unit Test Conditions
Parameter
VCCQ Note
VIL VIH VOL
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP LockOut Voltage VPP during Program / Erase Operations VCC Prog / Erase Lock Voltage VCCQ Prog / Erase Lock Voltage 1 1 1, 2
VCC 0.22 V VCCQ +0.3V 0.1
-0.4 VCCQ - 0.4V -0.1
0.4 VCCQ +0.3V 0.1
-0.4 VCCQ - 0.4V -0.1
0.4 VCCQ +0.3V 0.1
VOH VPPLK VPP1 VPP2
VCCQ -0.1V 1.0 1.65 11.4 3.6 12.6
VCCQ - 0.1V 1.0 1.65 11.4 3.6 12.6
VLKO2
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 8.
AC Characteristics
AC Read Characteristics
Read Operations-8-Mbit Density
Density Product 70 ns 2.7 V - 3.6 V Min (ns) Max (ns) 90 ns 3.0 V - 3.6 V Min (ns) Max (ns) 2.7 V - 3.6 V Min (ns) Max (ns) 8 Mbit 110 ns 3.0 V - 3.6 V Min (ns) Max (ns) 2.7 V - 3.6 V Min (ns) Max (ns)
Parameter
VCC Note
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 9.
Read Operations-16-Mbit Density
Density Product 16 Mbit
70 ns 2.7 V-3.6 V Min (ns) Max (ns)
80 ns 2.7 V-3.6 V Min (ns) Max (ns)
90 ns 3.0 V-3.6 V Min (ns) Max (ns) 2.7 V-3.6 V Min (ns) Max (ns)
110 ns 3.0 V-3.6V Min (ns) Max (ns) 2.7 V-3.6V Min (ns) Max (ns)
Notes
Parameter
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 10.
Read Operations-32-Mbit Density
Density Product 32 Mbit
70 ns 2.7 V-3.6 V Min (ns) Max (ns)
90 ns 2.7 V-3.6 V Min (ns) Max (ns)
100 ns 3.0 V-3.3 V Min (ns) Max (ns) 2.7 V-3.3 V Min (ns) Max (ns)
110 ns 3.0 V-3.3 V Min (ns) Max (ns) 2.7 V-3.3 V Min (ns) Max (ns)
Notes
Parameter
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 11.
Read Operations - 64-Mbit Density
Density Product # Sym Parameter VCC Note 2.7 V-3.6 V Min Max 2.7 V-3.6 V Min Max 70 ns 64 Mbit 80 ns Unit
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay RP# to Output Delay CE# to Output in Low Z OE# to Output in Low Z CE# to Output in High Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First
Figure 9.
Read Operation Waveform
R1 R2 Address A R3 CE# E R4 OE# G WE# W R7 R6 Data D / Q R5 RST# P R10 R9 R8
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 12.
AC Write Characteristics
Write Operations-8-Mbit Density
Density Product # Sym Parameter 3.0 V - 3.6 V VCC 2.7 V - 3.6 V Note 70 Min (ns) Min (ns) 90 Min (ns) Min (ns) 110 Min (ns) 70ns 80 8 Mbit 90 ns 110 ns 100
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 13.
Write Operations-16-Mbit Density
Density Product 70 ns 80 ns 16 Mbit 90 ns 80 70 Min 80 Min Min 90 Min Min 110 ns 100 110 Min Unit
Parameter VCC
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 14.
Write Operations-32-Mbit Density
Density Product 70 ns 90 ns 90 70 Min 90 Min Min 100 Min Min 32 Mbit 100 ns 110 ns 100 110 Min Unit
Parameter VCC
3.0 V - 3.6 V6 2.7 V - 3.6 V Note
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width
W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 15.
Write Operations-64-Mbit Density
Density 64 Mbit 80 ns Note Min Unit
Symbol
Parameter VCC
Product 2.7 V - 3.6 V
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14
tPHWL / tPHEL tELWL / tWLEL tWLWH / tELEH tDVWH / tDVEH tAVWH / tAVEH tWHEH / tEHWH tWHDX / tEHDX tWHAX / tEHAX tWHWL / tEHEL tVPWH / tVPEH tQVVL tBHWH / tBHEH tQVBL tWHGL
RP# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low WE# (CE#) Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High CE# (WE#) Hold Time from WE# (CE#) High Data Hold Time from WE# (CE#) High Address Hold Time from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) Going High VPP Hold from Valid SRD WP# Setup to WE# (CE#) Going High WP# Hold from Valid SRD WE# High to OE# Going Low
Figure 10.
Write Operations Waveform
W5 Address A W6 CE# E W3 W2 WE# W OE# G W4 Data D / Q W1 RP# P W10 Vpp V W7 W9 W8
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 16.
Erase and Program Timings
VPP Symbol Parameter Note Typ Max Typ Max 1.65 V-3.6 V 11.4 V-12.6 V Unit
tBWPB tBWMB
4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time for 0.13 and 0.18 Micron Product
tWHQV1 / tEHQV1
Word Program Time for 0.25 Micron Product 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency
tWHQV2 / tEHQV2 tWHQV3 / tEHQV3 tWHRH1 / tEHRH1 tWHRH2 / tEHRH2
Figure 11.
AC I / O Test Conditions
AC Input / Output Reference Waveform
VCCQ Input 0V
Note:
Test Points
Output
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Intel® Advanced+ Boot Block Flash Memory (C3)
Figure 12.
Transient Equivalent Testing Load Circuit
VCCQ R1
Device Under Test
Out CL R2
Note:
See Table 17 for component values.
Table 17.
Test Configuration Component Values for Worst-Case Speed Conditions
Test Configuration CL (pF) R1 (k) R2 (k)
VCCQMin Standard Test
Note:
CL includes jig capacitance.
Device Capacitance
Table 18.
Device Capacitance
CIN COUT
Input Capacitance Output Capacitance
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Power and Reset Specifications
Intel® flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep powerdown mode for ultra-low current consumption. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.
Active Power (Program / Erase / Read)
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices.
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from the memory array and the address lines are idle, APS circuitry places the device in a mode where typical current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read.
Standby Power
Deep Power-Down Mode
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Intel® Advanced+ Boot Block Flash Memory (C3)
Power and Reset Considerations
Power-Up / Down Characteristics
To prevent any condition that may result in a spurious write or erase operation, Intel recommends to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down together. Intel also recommends that you power-up VPP with or after VCC has reached VCCmin. Conversely, VPP must powerdown with or slightly before VCC. If VCCQ and / or VPP are not connected to the VCC supply, then VCC must attain VCCmin before applying VCCQ and VPP. Device inputs must not be driven before supply voltage reaches VCCmin. Power supply transitions must only occur when RP# is low.
RP# Connected to System Reset
The use of RP# during system reset is important with automated program / erase devices since the system reads from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU / flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset during power-up / down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after VCC transitions above VLKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read-array mode by the Read Array command if access to the flash-memory array is desired.
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Table 19.
Reset Specifications
VCC 2.7 V - 3.6 V Symbol Parameter Min Max Unit Notes
tPLPH tPLRH1 tPLRH2
RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) RP# Low to Reset during Block Erase RP# Low to Reset during Program
Figure 13.
Reset Operations Waveforms
tPHQV tPHW L tPHEL
t PLRH
t PLPH
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers should consider the following three supply current issues:
· Standby current levels (ICCS) · Read current levels (ICCR) · Transient peaks produced by falling and rising edges of CE#.
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Intel® Advanced+ Boot Block Flash Memory (C3)
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Device Operations
Bus Operations
The Intel® Advanced+ Boot Block Flash Memory (C3) device performs read, program, and erase operations in-system through the local CPU or microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of the flash device. Table 20 on page 39 summarizes these bus operations.
Table 20.
Bus Operations
Mode RP# CE# OE# WE# DQ15:0
Read Write Output Disable Standby Reset
Note:
VIL VIL VIL VIH X
VIL VIH VIH X X
VIH VIL VIH X X
DOUT DIN High-Z High-Z High-Z
When performing a read cycle, CE# and OE# must be asserted WE# and RP# must be deasserted. CE# is the device selection control when active low, it enables the flash memory device. OE# is the data output control when low, data is output on DQ15:0. See Figure 9, "Read Operation Waveform" on page 28.
Write
A write cycle occurs when both CE# and WE# are low RP# and OE# are high. Commands are issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever occurs first. See Figure 10, "Write Operations Waveform" on page 32.
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. DQ15:0 are placed in a high-impedance state.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during a Program or Erase operation, the device continues to consume active power until the Program or Erase operation is complete.
Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from reset before a write cycle can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, the Status Register is set to 0x80, and all blocks are locked. See Figure 13, "Reset Operations Waveforms" on page 37. If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be aborted the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. The abort process goes through the following sequence: 1. When RP# goes low, the device shuts down the operation in progress, a process which takes time tPLRH to complete. 2. After time tPLRH, the part will either reset to read-array mode (if RP# is asserted during tPLRH) or enter reset mode (if RP# is deasserted after tPLRH). See Figure 13, "Reset Operations Waveforms" on page 37. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL / tPHEL must be observed before a Read or Write operation is initiated, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, it is important to assert RP# during a system reset. When the system comes out of reset, the processor reads from the flash memory. Automated flash memories provide status information when read during Program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel® flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Modes of Operation
Read Mode
The flash memory has four read modes (read array, read identifier, read status, and CFI query) and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations. Table 22, "Command Bus Operations" on page 46 and Table 23, "Command Codes and Descriptions" on page 47 summarize the commands used for these modes. Appendix A, "Write State Machine States" on page 54 is a comprehensive chart showing the state transitions.
Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the device is in read array mode, four control signals control data output.
WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH)
In addition, the address of the desired location must be applied to the address pins. If the device is not in read-array mode, as would be the case after a Program or Erase operation, the Read Array command (0xFF) must be issued to the CUI before array reads can occur.
Read Identifier
The read-identifier mode outputs three types of information: the manufacturer / device identifier, the block locking status, and the protection register. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 21 retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF).
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 21.
Device Identification Codes
Address1 Item Base Offset Data Description
Manufacturer ID
Block
0x0089 0x88C0 0x88C1 0x88C2 0x88C3 8-Mbit Top Boot Device 8-Mbit Bottom Boot Device 16-Mbit Top Boot Device 16-Mbit Bottom Boot Device 32-Mbit Top Boot Device 32-Mbit Bottom Boot Device 64-Mbit Top Boot Device 64-Mbit Bottom Boot Device Block is unlocked Block is locked Block is not locked-down Block is locked down
Device ID
Block
0x01 0x88C4 0x88C5 0x88CC 0x88CD
Block Lock Status2
Block Lock-Down Status2 Protection Register Lock Status Protection Register
Multiple reads required to read the entire 128-bit Protection Register.
Notes: 1.The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 38 in a bottom boot device, set the address to 0x0F8000 plus the offset (0x02), i.e. 0x0F8002. Then examine DQ0 of the data to determine if the block is locked. 2.See Section 11.2, "Reading Block-Lock Status" on page 50 for valid lock status.
CFI Query
The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query Command (0x98). The CFI data structure contains information such as block size, density, command set, and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix C, "Common Flash Interface, " retrieve the specified information. To return to read-array mode, issue the Read Array command (0xFF).
Read Status Register
The Status Register indicates the status of device operations and the success / failure of that operation. The Read Status Register (0x70) command causes subsequent reads to output data from the Status Register until another command is issued. To return to reading from the array, issue a Read Array (0xFF) command. The Status Register bits are output on DQ7:0. The upper byte, DQ15:8, outputs 0x00 when a Read Status Register command is issued.
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Intel® Advanced+ Boot Block Flash Memory (C3)
The contents of the Status Register are latched on the falling edge of OE# or CE# (whichever occurs last) which prevents possible bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register will not indicate completion of a Program or Erase operation. When the WSM is active, SR7 will indicate the status of the WSM the remaining bits in the Status Register indicate whether the WSM was successful in performing the preferred operation See Table 24, "Status Register Bit Definition" on page 48.
Clear Status Register
The WSM can set Status Register bits 1 through 7 and can clear bits 2, 6, and 7, but the WSM cannot clear Status Register bits 1, 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (0x50) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the Status Register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. The Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the Status Register.
Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup command (0x40) is issued to the CUI, followed by a second write that specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program preferred bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a "0." If users attempt to program "1"s, the memory cell contents do not change and no error occurs. The Status Register indicates programming status. While the program sequence executes, status bit 7 is "0." The Status Register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program-status bits must be checked. If the programming operation was unsuccessful, SR4 is set to indicate a program failure. If SR3 is set, then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR1 is set, a program operation was attempted on a locked block and the operation was aborted. The Status Register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed however, to prevent inadvertent Status Register reads, be sure to reset the CUI to read-array mode.
12-Volt Production Programming
When VPP is between 1.65 V and 3.6 V, all program and erase current is drawn through the VCC pin.
Note:
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Intel® Advanced+ Boot Block Flash Memory (C3)
When VPP is connected to a 12 V power supply, the device draws program and erase current directly from the VPP pin. This eliminates the need for an external switching transistor to control VPP. Figure 16 on page 53 shows examples of how the flash power supplies can be configured for various usage models. The 12 V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes however, it is not intended for extended use. You cna apply 12 V to VPP during Program and Erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
Suspending and Resuming Program
The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, issuing the Program Suspend command to the CUI requests that the WSM suspend the program sequence at predetermined points in the program algorithm. The device continues to output Status Register data after the Program Suspend command is issued. Polling SR7 and SR2 will determine when the program operation has been suspended (both will be set to "1"). The program-suspend latency is specified with tWHRH1 / tEHRH1. A Read-Array command can now be issued to the CUI to read data from blocks other than that which is suspended. The only other valid commands while program is suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume. After the Program Resume command is issued to the flash memory, the WSM will continue with the programming process and SR2 and SR7 will automatically be cleared. The device automatically outputs Status Register data when read (see Figure 18, "Program Suspend / Resume Flowchart" on page 57) after the Program Resume command is issued. VPP must remain at the same VPP level used for program while in program-suspend mode. RP# must also remain at VIH.
Erase Mode
To erase a block, issue the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0, " erase all bits within the block to "1, " then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the Status Register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. If the Erase operation was unsuccessful, SR5 of the Status Register will be set to a "1, " indicating an erase failure. If VPP is not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence instead, SR5 of the Status Register is set to indicate an erase error, and SR3 is set to a "1" to identify that VPP supply voltage is not within acceptable limits. After an Erase operation, clear the Status Register (0x50) before attempting the next operation. Any CUI instruction can follow after erasure is completed however, to prevent inadvertent statusregister reads, Intel recommends that you place the flash in read-array mode after the erase is complete.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Suspending and Resuming Erase
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 22.
Command Bus Operations
First Bus Cycle Command Notes Oper Addr Data Oper Addr Data Second Bus Cycle
Read Array Read Identifier CFI Query Read Status Register Clear Status Register Program Block Erase / Confirm Program / Erase Suspend Program / Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program
Write Write Write Write Write Write Write Write Write Write Write Write Write
0xFF 0x90 0x98 0x70 0x50 0x40 / 0x10 0x20 0xB0 0xD0 0x60 0x60 0x60 0xC0 Write Write Write Write BA BA BA PA 0x01 0xD0 0x2F PD Write Write PA BA PD D0H Read Read Read IA QA X ID QD SRD
Notes: 1.Following the Read Identifier or CFI Query commands, read operations output device identification data or CFI query information, respectively. See Section 10.1.2 and Section 10.1.3. 2.Either 0x40 or 0x10 command is valid, but the Intel standard is 0x40. 3.When writing commands, the upper data bus DQ8-DQ15 should be either VIL or VIH, to minimize current draw.
Bus operations are defined in Table 20, "Bus Operations" on page 39.
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 23.
Code (HEX)
Command Codes and Descriptions
Device Mode Command Description
Read Array
Program Set-Up
Erase Set-Up
Erase Confirm D0 Program / Erase Resume Unlock Block
Program Suspend Erase Suspend
Read Status Register Clear Status Register Read Identifier Block Lock,
Block Unlock, Block Lock-Down Set-Up Lock-Block Lock-Down CFI Query
Protection Program Set-Up Alt. Prog Set-Up Invalid / Reserved
Note:
See Appendix A, "Write State Machine States" for mode transition information.
Datasheet
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Intel® Advanced+ Boot Block Flash Memory (C3)
Table 24.
WSMS 7
Status Register Bit Definition
NOTES:
Before checking program or erase- status bits, check the Write State Machine bit first to determine Word Program or Block Erase completion. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1, " WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1, " WSM has attempted but failed to program a word / byte. The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1Min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the Status Register.
Note:
A Command-Sequence Error is indicated when SR4, SR5, and SR7 are set.
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Security Modes
Flexible Block Locking
Figure 14.
Block Locking State Diagram
Power-Up / Reset
Locked X01
LockedDown4, 5 011
Hardware Locked5 011
WP# Hardware Control
Unlocked X00
Software Locked 111
Unlocked 110
Software Block Lock (0x60 / 0x01) or Software Block Unlock (0x60 / 0xD0) Software Block Lock-Down (0x60 / 0x2F) WP# hardware control
Notes:
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) Order Number: 290645, Revision: 022
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Intel® Advanced+ Boot Block Flash Memory (C3)
Locking Operation
The locking status of each block can be set to Locked, Unlocked, or Lock-Down, each of which will be described in the following sections. See Figure 14, "Block Locking State Diagram" on page 49 and Figure 21, "Locking Operations Flowchart" on page 60. The following paragraph concisely summarizes the locking functionality.
Locked State
The default state of all blocks upon power-up or reset is locked (states 001 or 101). Locked blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked block will return an error on bit SR1. The state of a locked block can be changed to Unlocked or Lock Down using the appropriate software commands. An Unlocked block can be locked by writing the Lock command sequence, 0x60 followed by 0x01.
Unlocked State
Unlocked blocks (states 000, 100, 110) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 0x60 followed by 0xD0.
Lock-Down State
Reading Block-Lock Status
The Lock status of each block can be read in read-identifier mode of the device by issuing the readidentifier command (0x90). Subsequent reads at Block Address + 0x00002 will output the Lock status of that block. The Lock status is represented by DQ0 and DQ1:
· DQ0 indicates the Block Lock / Unlock status and is set by the Lock command and cleared by
the Unlock command. It is also automatically set when entering Lock Down.
· DQ1 indicates Lock-Down status and is set by the Lock-Down command. It cannot be cleared
by software-only by device reset or power-down. See Table 21, "Device Identification Codes" on page 42 for block-status information.
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Locking Operations during Erase Suspend
Changes to block-lock status can be performed during an erase-suspend by using the standard locking command sequences to Unlock, Lock, or Lock Down a block. This operation is useful in the case when another block needs to be updated while an Erase operation is in progress. To change block locking during an Erase operation, first issue the Erase Suspend command (0xB0), and then check the Status Register until it indicates that the Erase operation has been suspended. Next, write the preferred Lock command sequence to a block and the Lock status will be changed. After completing any preferred Lock, Read, or Program operations, resume the Erase operation with the Erase Resume command (0xD0). If a block is Locked or Locked Down during a Suspended Erase of the same block, the locking status bits will be changed immediately. But when the Erase is resumed, the Erase operation will complete. Locking operations cannot be performed during a Program Suspend. Refer to Appendix A, "Write State Machine States" on page 54 for detailed information on which commands are valid during Erase Suspend.
Status Register Error Checking
Using nested-locking or program-command sequences during Erase Suspend can introduce ambiguity into Status Register results. Since locking changes are performed using a two-cycle command sequence, for example, 0x60 followed by 0x01 to lock a block. Following the Block Lock, Block Unlock, or Block Lock-Down Setup command (0x60) with an invalid command will produce a Lock-Command error (SR4 and SR5 will be set to 1) in the Status Register. If a Lock-Command error occurs during an Erase Suspend, SR4 and SR5 will be set to 1 and will remain at 1 after the Erase is resumed. When Erase is complete, any possible error during the Erase cannot be detected by the Status Register because of the previous Lock-Command error. A similar situation happens if an error occurs during a Program-Operation error nested within an Erase Suspend.
128-Bit Protection Register
The C3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "match" the flash component with other system components, such as the CPU or ASIC, preventing device substitution. Application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program, as preferred. Once the customer segment is programmed, it can be locked to prevent further programming.
Datasheet
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Intel® Advanced+ Boot Block Flash Memory (C3)
Reading the Protection Register
The protection register is read in the Read-Identifier mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Figure 15, "Protection Register Mapping" retrieve the specified information. To return to ReadArray mode, issue the Read Array command (0xFF).
Programming the Protection Register
The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data and program the specified location. The allowable addresses are listed in Table 21, "Device Identification Codes" on page 42. See Figure 22, "Protection Register Programming Flowchart" on page 61. Attempting to program to a previously locked protection register segment will result in a Status Register error (Program Error bit SR4 and Lock Error bit SR1 will be set to 1).
Note:
Do not attempt to address Protection Program commands outside the defined protection register address space status register can be indeterminate.
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming bit 1 of the PR-LOCK location to 0. See Figure 15, "Protection Register Mapping" on page 52. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a Status Register error (Program Error bit SR4 and Lock Error bit SR1 will be set to 1). Protection register lockout state is not reversible.
Figure 15.
Protection Register Mapping
64-bit Segment (User-Programmable)
0x85 0x84
128-Bit Protection Register 0
64-bit Segment (Intel Factory-Programmed)
0x81 PR Lock Register 0 0x80
VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V-3.6 V range. For fast production programming, 12 V programming can be used. See Figure 16, "Example Power Supply Configurations" on page 53.
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Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3)
Program Protection
In addition to the flexible block locking, the VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When VPP is below or equal to VPPLK, any Program or Erase operation will result in an error, prompting the corresponding Status Register bit (SR3) to be set.
Figure 16.
Example Power Supply Configurations
System Supply 12 V Supply 10 K 12 V Fast Programming Absolute Write Protection With V System Supply
(Note 1)
System Supply
VCC VPP
Prot# (Logic Signal)
VCC VPP
Low-Voltage Programming V PPLK PP Absolute Write Protection via Logic Signal System Supply
VCC VPP
Low-Voltage Programming
12 V Supply Low Voltage and 12 V Fast Programming
Note: 1.A resistor can be used if the VCC supply can sink adequate current based on resistor value. See AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture for details.
Datasheet
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Intel® Advanced+ Boot Block Flash Memory (C3)
Appendix A Write State Machine States
Table 25 and Table 26 show the Write State Machine command state transitions based on incoming commands.
Table 25. Write State Machine States
Command Input (and Next State) Data When Read Array Status Config CFI Status Status Status Status Status Status Status Status Status Array Config CFI Status Status Status Status Status Array Config CFI