Matched Switching Characteristics, Qualification Accordance With
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
Matched Switching Characteristics,
Qualification Accordance With
AEC-Q100 Qualified Automotive Applications Customer-Specific Configuration Control Supported Along With Major-Change Approval Wide Range Digital Analog Signal Levels Digital: Analog: VP-P Resistance, (Typ) Over VP-P Signal Input Range High Resistance, Channel Leakage +100 (Typ) Logic-Level Conversion Digital Addressing Signals (VDD Switch Analog Signals VP-P (VDD
(Typ) Very Quiescent Power Dissipation Under Digital-Control Input Supply Conditions, (Typ) Binary Address Decoding Chip 5-V, 10-V, 15-V Parametric Ratings 100% Tested Quiescent Current Maximum Input Current Over Full Package Temperature Range, 25°C Break-Before-Make Switching Eliminates Channel Overlap
Applications
Analog Digital Multiplexing
Demultiplexing
Analog-to-Digital (A/D)
Digital-to-Analog (D/A) Conversion Signal Gating
Contact factory details. Q100 qualification data available request.
description/ordering information
CD4051B, CD4052B, CD4053B analog multiplexers digitally-controlled analog switches that have impedance very leakage current. Control analog signals VP-P achieved digital signal amplitudes controlled; level differences above least required). example, -13.5 analog signals from -13.5 controlled digital inputs These multiplexer circuits dissipate extremely quiescent power over full supply-voltage ranges, independent logic state control signals. When logic high present inhibit (INH) input, channels off. ORDERING INFORMATION
SOIC TSSOP SOIC -40°C 125°C TSSOP SOIC TSSOP PACKAGE Reel 2500 Reel 2000 Reel 2500 Reel 2000 Reel 2500 Reel 2000 ORDERABLE PART NUMBER CD4051BQM96Q1 CD4051BQPWRQ1 CD4053BQM96Q1 TOP-SIDE MARKING CD4051Q CM051BQ CD4052Q CD4052Q CD4053Q CD4053Q
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Product Preview Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
description/ordering information (continued)
CD4051B single eight-channel multiplexer that three binary control inputs inhibit input. three binary signals select eight channels turned connect eight inputs output. CD4052B differential four-channel multiplexer that binary control inputs inhibit input. binary input signals select four pairs channels turned connect analog inputs outputs. CD4053B triple two-channel multiplexer with three separate digital control inputs inhibit input. Each control input selects pair channels, which connected single-pole, double-throw configuration. When these devices used demultiplexers, CHANNEL IN/OUT terminals outputs, common (COM OUT/IN) terminals inputs.
CD4051 PACKAGE (TOP VIEW) CD4052 PACKAGE (TOP VIEW)
CHANNEL CHANNEL OUT/IN CHANNEL CHANNEL
CHANNEL CHANNEL CHANNEL CHANNEL
CHANNEL CHANNEL OUT/IN CHANNEL CHANNEL
CHANNEL CHANNEL OUT/IN CHANNEL CHANNEL
CD4053 PACKAGE (TOP VIEW)
IN/OUT IN/OUT IN/OUT OUT/IN IN/OUT
OUT/IN OUT/IN IN/OUT IN/OUT
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
Function Tables
CD4051 INPUTS CHANNEL None
don't care CD4052 INPUTS don't care CD4053 INPUTS don't care CHANNEL None CHANNEL None
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
logic diagram (positive logic)
CD4051B CHANNEL
Logic-Level Conversion Binary 1-of-8 Decoder With Inhibit
OUT/IN
inputs protected CMOS protection network. CD4052B CHANNEL
Logic-Level Conversion
OUT/IN
Binary 1-of-4 Decoder With Inhibit
OUT/IN
CHANNEL
inputs protected CMOS protection network.
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
logic diagrams (positive logic) (continued)
CD4053B
IN/OUT Logic-Level Conversion Binary 1-of-2 Decoders With Inhibit OUT/IN OUT/IN OUT/IN
inputs protected standard CMOS protection network.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, (voltages referenced terminal) -0.5 input voltage range -0.5 input current, input Package thermal impedance, (see Note package 73°C/W package 108°C/W Maximum junction temperature, 150°C Lead temperature (during soldering): distance 1/16 1/32 inch (1,59 0,79 from case 265°C Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE package thermal impedance calculated accordance with JESD 51-7.
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
recommended operating conditions
Supply voltage Operating free-air temperature UNIT
electrical characteristics, VSUPPLY unless otherwise noted (see Note
Quiescent device current Signal Input (Vis) Output (Vos) Drain-to-source ON-state resistance ON-state resistance difference between switches Input/output leakage current (switch off) Input capacitance channel (MAX) channels (COM OUT/IN) (Max), Note CD4051 Output capacitance Feedthrough capacitance Propagation delay (signal input output) CD4052 CD4053 Cios VIS(p-p) VDD, ±0.1 1300 ±10-5 ±0.1 1050 LIMITS INDICATED TEMPERATURES 25°C -40°C 125°C 3000 0.04 0.04 0.04 0.08 UNIT
PARAMETER
TEST CONDITIONS
NOTES: Peak-to-peak voltage symmetrical about Determined minimum feasible leakage measurement automatic testing
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
electrical characteristics, VSUPPLY unless otherwise noted (see Note (continued)
LIMITS INDICATED TEMPERATURES 25°C -40°C 125°C UNIT
PARAMETER
TEST CONDITIONS
Control (Address Inhibit), Input voltage through through VSS, channels through through VSS, channels Figure Figure Figure Figure Figure ±0.1 ±10-5 ±0.1
Input high voltage
Input current Address-to-signal (channels OFF) propagation delay Inhibit-to-signal (channel turning propagation delay Inhibit-to-signal (channel turning OFF) propagation delay Input capacitance, address inhibit input
tpd1
tpd2
tpd3
NOTES: Peak-to-peak voltage symmetrical about Determined minimum feasible leakage measurement automatic testing
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
electrical specifications
LIMITS INDICATED TEMPERATURES 25°C -3-dB cutoff frequency, channel (sine-wave input) OUT/IN, Note OUT/IN VSS, 20log VOS/VIS channel Note VSS, 1-kHz sine wave -40-dB feedthrough frequency (all channels OFF) OUT/IN, Note VSS, 20log VOS/VIS channel between channels, Note VSS, 20log VOS/VIS Between sections, Measured common VSS, 20log VOS/VIS Between sections, Measured channel VSS, 20log VOS/VIS Between sections, VSS, 20log VOS/VIS Between sections, Address inhibit signal crosstalk Note (square wave) CD4053 mVPEAK CD4052 CD4053 CD4052 CD4051 CD4053 CD4052 CD4051 Total harmonic distortion 0.12 0.12
PARAMETER
TEST CONDITIONS
UNIT
-40-dB signal crosstalk frequency
NOTES: Peak-to-peak voltage symmetrical about Both ends channel
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
TYPICAL CHARACTERISTICS
CHANNEL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE
Channel ON-State Resistance Channel ON-State Resistance 25°C -55°C Supply Voltage (VDD VEE) 125°C 125°C 25°C -55°C -7.5 -2.5
CHANNEL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE
Supply Voltage (VDD VEE)
Input Signal Voltage
92CS-27326RI
Input Signal Voltage
92CS-27327RI
Figure
CHANNEL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE
Channel ON-State Resistance 25°C -7.5 -2.5
92CS-27330RI
Figure
CHANNEL ON-STATE RESISTANCE INPUT SIGNAL VOLTAGE
Channel ON-State Resistance Supply Voltage (VDD VEE) 125°C -7.5 -2.5 Input Signal Voltage 25°C -55°C
Supply Voltage (VDD VEE)
Input Signal Voltage
92CS-27329RI
Figure
Figure
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
TYPICAL CHARACTERISTICS
DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4051B)
Power Dissipation Package
255C Alternating Pattern Test Circuit CD4029
CHARACTERISTICS 1-OF-8 CHANNELS (CD4051B)
Output Signal Voltage
255C
CD4051
Input Signal Voltage
Switching Frequency
Figure
DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4052B)
Power Dissipation Package
255C Alternating Pattern
Figure
DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4053B)
255C Alternating Pattern
Power Dissipation Package
Test Circuit CD4029
CD4052
Test Circuit
CD4053
Switching Frequency
Switching Frequency
Figure
Figure
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
-7.5
NOTE: input logic levels VDD. analog signal (through swing from VDD.
Figure Typical Bias-Voltage Test Circuits
Turn-Off Time Turn-On Time
Turn-Off Time tPHZ
Turn-On Time
Figure Channel Turned Waveforms
Figure Channel Turned Waveforms
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
CD4052
CD4051
CD4052
CD4053
Figure Channel Leakage Current, Channel
CD4051
CD4052
CD4053
Figure Channel Leakage Current, Channels
Output Output Output
Clock
Clock
Clock
CD4051
CD4052
CD4053
Figure Propagation Delay, Address Input Signal Output
Output Output Output Clock
Clock
Clock
tPHL tPLH
tPHL tPLH
tPHL tPLH
CD4051
CD4052
CD4053
Figure Propagation Delay, Inhibit Input Signal Output
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
CD4052B
CD4053B
CD4051B
Measure Channels (e.g., Channel
Measure Channels (e.g., Channel
Measure Channels (e.g., Channel
Figure Input-Voltage Test Circuit (Noise Immunity)
CD4051 CD4053
CD4052
Figure Quiescent Device Current
Keithley Digital Multimeter 1-kW Range
Plotter
H.P. Moseley 7030A
Figure Channel ON-Resistance Test Circuit
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
PARAMETER MEASUREMENT INFORMATION
CD4051 CD4053 CD4051 CD4053
NOTE: Measure inputs sequentially both VSS. Connect unused inputs either VSS.
NOTE: Measure inputs sequentially both VSS. Connect unused inputs either VSS.
Figure Input Current
Channel VP-P Channel Channel Common
VP-P
Channel
Channel
Figure Feedthrough
VP-P
Figure Crosstalk Between Channels
Channel
Channel
Figure Crosstalk Between Duals Triplets (CD4052B, CD4053B)
Differential Signals
CD4052
CD4052
Communications Link
Differential Amplifier/Line Driver Differential Multiplexing
Differential Receiver
Demultiplexing
Figure Typical Time-Division Application CD4052B
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CD4051B CD4052B CD4053B CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION
APPLICATION INFORMATION
applications where separate power sources drive signal inputs, current capability should exceed VDD/RL effective external load). This provision avoids permanent current flow clamp action supply when power applied removed from CD4051B, CD4052B, CD4053B.
CD4051B CD4556 CD4051B CD4051B
Common Output
Figure 24-to-1 Multiplexer Addressing
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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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