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DESCRIPTIO Smallest Pin-Compatible Single DACs: LTC2606: Bits LTC


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LTC2606/LTC2616/LTC2626 16-/14-/12-Bit Rail-to-Rail DACs with Interface
DESCRIPTIO
Smallest Pin-Compatible Single DACs: LTC2606: Bits LTC2616: Bits LTC2626: Bits Guaranteed 16-Bit Monotonic Over Temperature Selectable Addresses 400kHz I2CInterface Wide 2.7V 5.5V Supply Range Power Operation: 270µA Power Down 1µA, High Rail-to-Rail Output Drive (±15mA, Min) Double-Buffered Data Latches Asynchronous Update LTC2606/LTC2616/LTC2626: Power-On Reset Zero Scale LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset Midscale Tiny (3mm 3mm) 10-Lead Package
LTC2606/LTC2616/LTC2626 single 16-, 14and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs 10-lead package. They have built-in high performance output buffers guaranteed monotonic. These parts establish board-density benchmarks 14-bit DACs advance performance standards output drive load regulation single-supply, voltage-output DACs. parts 2-wire, compatible serial interface. LTC2606/LTC2616/LTC2626 operate both standard mode (clock rate 100kHz) fast mode (clock rate 400kHz). asynchronous update (LDAC) also included. LTC2606/LTC2616/LTC2626 incorporate power-on reset circuit. During power-up, voltage outputs rise less than 10mV above zero scale; after power-up, they stay zero scale until valid write update take place. power-on reset circuit resets LTC2606-1/LTC2616-1/ LTC2626-1 midscale. voltage outputs stay midscale until valid write update take place.
registered trademarks Linear Technology Corporation. other trademarks property their respective owners.
APPLICATIO
Mobile Communications Process Control Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
INPUT REGISTER INTERFACE
REGISTER
16-BIT
VOUT
CONTROL LOGIC
(LSB)
ADDRESS DECODE LDAC
2606
Differential Nonlinearity (LTC2606)
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
2606
VREF 4.096V
26061626f
LTC2606/LTC2616/LTC2626 ABSOLUTE RATI (Note
Operating Temperature Range: LTC2606C/LTC2616C/LTC2626C 70°C LTC2606I/LTC2616I/LTC2626I 40°C 85°C 0.3V 0.3V Maximum Junction Temperature 125°C Storage Temperature Range 65°C 125°C Lead Temperature (Soldering, sec). 300°C
PACKAGE/ORDER ATIO
VIEW LDAC VOUT
ORDER PART NUMBER LTC2606CDD LTC2606IDD LTC2606CDD-1 LTC2606IDD-1 PART MARKING LAJX LAJW
PACKAGE 10-LEAD (3mm 3mm) PLASTIC
TJMAX 125°C, 43°C/W EXPOSED (PIN MUST SOLDERED
Consult Marketing parts specified with wider operating temperature ranges.
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Performance Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Load Regulation CONDITIONS
ELECTRICAL CHARACTERISTICS
Zero-Scale Error Offset Error Temperature Coefficient Gain Error Gain Temperature Coefficient
(Note (Note (Note VREF Midscale IOUT 15mA Sourcing IOUT 15mA Sinking VREF 2.7V, Midscale IOUT 7.5mA Sourcing IOUT 7.5mA Sinking Code (Note
ORDER PART NUMBER LTC2616CDD LTC2616IDD LTC2616CDD-1 LTC2616IDD-1 PART MARKING LBPQ LBPR
ORDER PART NUMBER LTC2626CDD LTC2626IDD LTC2626CDD-1 LTC2626IDD-1 PART MARKING LBPS LBPT
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 ±0.5
UNITS Bits Bits LSB/mA LSB/mA LSB/mA LSB/mA µV/°C %FSR ppm/°C
0.025 0.125 0.05 0.125 0.05 0.25 0.25
±0.1 ±0.7 ±8.5
±0.1 ±0.7 ±8.5
±0.1 ±0.7 ±8.5
26061626f
LTC2606/LTC2616/LTC2626
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), VOUT unloaded, unless otherwise noted. (Note
SYMBOL ROUT PARAMETER Power Supply Rejection Output Impedance Short-Circuit Output Current CONDITIONS ±10% VREF Midscale; -15mA IOUT 15mA VREF 2.7V, Midscale; -7.5mA IOUT 7.5mA 5.5V, VREF 5.5V Code: Zero Scale; Forcing Output Code: Full Scale; Forcing Output 2.7V, VREF 2.7V Code: Zero Scale; Forcing Output Code: Full Scale; Forcing Output
ELECTRICAL CHARACTERISTICS
0.05 0.06
0.15 0.15 0.3VCC
UNITS
Reference Input Input Voltage Range Resistance Capacitance IREF Reference Current, Power Down Mode Power Supply Positive Supply Voltage Supply Current
Normal Mode Powered Down Specified Performance (Note (Note Powered Down (Note Powered Down (Note
0.001
0.340 0.27 0.35 0.10 -0.5 0.7VCC
Digital (Note Level Input Voltage (SDA SCL) High Level Input Voltage (SDA SCL) VIL(LDAC) Level Input Voltage (LDAC) VIH(LDAC) VIL(CAn) VIH(CAn) RINH RINL RINF CCAX High Level Input Voltage (LDAC) Level Input Voltage High Level Input Voltage Resistance from Resistance from Resistance from Float Level Output Voltage Output Fall Time Pulse Width Spikes Suppressed Input Filter Input Leakage Capacitance Capacitive Load Each Line External Capacitive Load Address Pins
(Note 4.5V 5.5V 2.7V 5.5V 2.7V 5.5V 2.7V 3.6V Test Circuit Test Circuit Test Circuit Test Circuit Test Circuit Sink Current VIH(MIN) VIL(MAX), 10pF 400pF (Note
0.15VCC 0.85VCC
26061626f
0.1CB
0.1VCC 0.9VCC
LTC2606/LTC2616/LTC2626
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Performance Settling Time (Note ±0.024% (±1LSB Bits) ±0.006% (±1LSB Bits) ±0.0015% (±1LSB Bits) ±0.024% (±1LSB Bits) ±0.006% (±1LSB Bits) ±0.0015% (±1LSB Bits) 0.75 1000 0.75 1000 V/µs nV/Hz nV/Hz µVP-P CONDITIONS LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1 UNITS
ELECTRICAL CHARACTERISTICS
Settling Time 1LSB Step (Note Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth Output Voltage Noise Density Output Voltage Noise
0.75 1000 Midscale Transition 1kHz 10kHz 0.1Hz 10Hz
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (See Figure (Notes
SYMBOL PARAMETER 2.7V 5.5V fSCL Clock Frequency tHD(STA) Hold Time (Repeated) Start Condition tLOW Period Clock tHIGH High Period Clock tSU(STA) Set-Up Time Repeated Start Condition tHD(DAT) Data Hold Time tSU(DAT) Data Set-Up Time Rise Time Both Signals Fall Time Both Signals tSU(STO) Set-Up Time Stop Condition tBUF Free Time Between Stop Start Condition Falling Edge Clock Input Byte LDAC High Transition LDAC Pulse Width CONDITIONS
CHARACTERISTICS
Note Absolute maximum ratings those values beyond which life device impaired. Note Linearity monotonicity defined from code code where resolution given 0.016(2N/VREF), rounded nearest whole code. VREF 4.096V linearity defined from code code 65,535. Note Digital inputs VCC. Note Guaranteed design production tested. Note Inferred from measurement code (LTC2606/LTC2606-1), code (LTC2616/LTC2616-1) code (LTC2626/LTC2626-1) full scale.
0.1CB 0.1CB
UNITS
(Note (Note
Note VREF 4.096V. stepped scale scale scale scale. Load parallel with 200pF GND. Note VREF 4.096V. stepped ±1LSB between half scale half scale Load parallel with 200pF GND. Note Maximum VCC(MAX) 0.5V Note capacitance line Note values refer VIH(MIN) VIL(MAX) levels. Note These specifications apply LTC2606/LTC2606-1, LTC2616/LTC2616-1, LTC2626/LTC2626-1.
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LTC2606/LTC2616/LTC2626 TYPICAL PERFOR CHARACTERISTICS
LTC2606
Integral Nonlinearity (INL)
(LSB) (LSB) 16384 32768 CODE 49152 65535
2606
VREF 4.096V
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
2606
(LSB)
Temperature
(LSB) -0.2 -0.4 -0.6 -0.8 -1.0 TEMPERATURE (°C) (NEG) (POS)
(LSB)
VREF 4.096V
(NEG)
(LSB)
Settling ±1LSB
VOUT 100µV/DIV CLOCK DATA BYTE 9.7µs
2V/DIV
VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
2606
Differential Nonlinearity (DNL)
VREF 4.096V
Temperature
VREF 4.096V
(POS)
(NEG)
TEMPERATURE (°C)
2606
VREF
5.5V (POS)
VREF
5.5V
(POS) (NEG) -0.5 -1.0 -1.5
VREF
2606
VREF
2606
Settling Full-Scale Step
VOUT 100µV/DIV
12.3µs CLOCK DATA BYTE
2V/DIV
2µs/DIV
2606
5µs/DIV SETTLING ±1LSB VREF 4.096V CODE 65535 STEP AVERAGE 2048 EVENTS
2606
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LTC2606/LTC2616/LTC2626 TYPICAL PERFOR CHARACTERISTICS
LTC2616
Integral Nonlinearity (INL)
(LSB) (LSB) -0.6 4096 8192 CODE 12288 16383
2606
VREF 4.096V
LTC2626
Integral Nonlinearity (INL)
(LSB)
VREF 4.096V
(LSB)
-0.5 -1.0
-1.5 -2.0 1024 2048 CODE 3072 4095
2606
Differential Nonlinearity (DNL)
VOUT 100µV/DIV
Settling ±1LSB
VREF 4.096V
-0.2 -0.4
2V/DIV
CLOCK DATA BYTE 2µs/DIV VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
8.9µs
2606
-0.8 -1.0 4096 8192 CODE 12288 16383
2606
Differential Nonlinearity (DNL)
VREF 4.096V
Settling ±1LSB
6.8µs VOUT 1mV/DIV CLOCK DATA BYTE 2µs/DIV VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
2606
-0.2 -0.4 -0.6 -0.8 -1.0 1024 2048 CODE 3072 4095
2606
2V/DIV
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LTC2606/LTC2616/LTC2626 TYPICAL PERFOR CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Current Limiting
0.10 0.08 0.06 0.04 CODE MIDSCALE VREF VREF
VOUT (mV)
OFFSET ERROR (mV)
VOUT
0.02 -0.02 -0.04 -0.06 -0.08 -0.10 IOUT (mA) VREF VREF
Zero-Scale Error Temperature
ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR)
OFFSET ERROR (mV)
TEMPERATURE (°C)
Gain Error
GAIN ERROR (%FSR)
(nA)
-0.1 -0.2
-0.3 -0.4
2606
Load Regulation
CODE MIDSCALE -0.2 -0.4 -0.6 -0.8 -1.0 IOUT (mA) VREF VREF
Offset Error Temperature
TEMPERATURE (°C)
2606
2606
2606
Gain Error Temperature
Offset Error
-0.1 -0.2 -0.3
-0.4
TEMPERATURE (°C)
2606
2606
Shutdown
2606
2606
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LTC2606/LTC2616/LTC2626 TYPICAL PERFOR CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Large-Signal Response Midscale Glitch Impulse
TRANSITION FROM MS-1
VOUT 0.5V/DIV
VREF 1/4-SCALE 3/4-SCALE 2.5µs/DIV
2606
Headroom Rails Output Current
VOUT IOUT (mA) SINKING SINKING
VOUT
Supply Current Logic Voltage
(µA) LOGIC VOLTAGE (µA) SWEEP LDAC
Power-On Reset Glitch
VOUT 10mV/DIV CLOCK DATA BYTE TRANSITION FROM MS-1
1V/DIV
PEAK VOUT 10mV/DIV
2V/DIV
2.5µs/DIV
2606
250µs/DIV
2606
Power-On Reset Midscale
VREF
SOURCING
SOURCING
1V/DIV
500µs/DIV
2606
2606
Supply Current Logic Voltage
SWEEP HYSTERESIS 370mV
LOGIC VOLTAGE
2606
2606
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LTC2606/LTC2616/LTC2626 TYPICAL PERFOR CHARACTERISTICS
LTC2606/LTC2616/LTC2626
Multiplying Bandwidth
VOUT 10µV/DIV
VREF (DC) VREF (AC) 0.2VP-P CODE FULL SCALE 100k FREQUENCY (Hz)
2606
Short-Circuit Output Current VOUT (Sinking)
10mA/DIV
5.5V VREF 5.6V CODE VOUT SWEPT 1V/DIV
2606
10mA/DIV
Output Voltage Noise, 0.1Hz 10Hz
SECONDS
2606
Short-Circuit Output Current VOUT (Sourcing)
5.5V VREF 5.6V CODE FULL SCALE VOUT SWEPT 1V/DIV
2606
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LTC2606/LTC2616/LTC2626
FUNCTIONS
(Pin Chip Address this VCC, leave floating select slave address part (Table (Pin Serial Data Bidirectional Pin. Data shifted into acknowledged pin. This high impedance while data shifted Open drain N-channel output during acknowledgment. requires pull-up resistor current source VCC. (Pin Serial Clock Input Pin. Data shifted into rising edges clock. This high impedance requires pull-up resistor current source VCC. (Pin Chip Address this VCC, leave floating select slave address part (Table (Pin Chip Address this VCC, leave floating select slave address part (Table (Pin Reference Voltage Input. VREF VCC. VOUT (Pin Analog Voltage Output. output range VREF. (Pin Analog Ground. (Pin Supply Voltage Input. 2.7V 5.5V. LDAC (Pin 10): Asynchronous Update. falling edge this input after four bytes have been written into part immediately updates register with contents input register. this input without complete 32-bit (four bytes including slave address) data write transfer part does update output. Software power-down disabled when LDAC low. Exposed (Pin 11): Ground. Must soldered ground.
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LTC2606/LTC2616/LTC2626
BLOCK DIAGRA
INPUT REGISTER INTERFACE CONTROL LOGIC REGISTER 16-BIT VOUT ADDRESS DECODE LDAC
2606
TEST CIRCUITS
Test Circuit Test Circuit
VIH(CAn)/VIL(CAn)
RINH/RINL/RINF
2606
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tLOW tHD(STA) tHD(DAT) tHIGH
2606
tSU(DAT) tHD(STA) tBUF
DIAGRA
VOLTAGE LEVELS REFER VIH(MIN) VIL(MAX) LEVELS
LTC2606/LTC2616/LTC2626
Figure
SLAVE ADDRESS DATA BYTE DATA BYTE
DATA BYTE
START
2606 F02A
LDAC
Figure
CLOCK DATA BYTE LDAC
2606 F02b
Figure
tSU(STA)
tSU(STO)
26061626f
LTC2606/LTC2616/LTC2626
OPERATIO
Power-On Reset
LTC2606/LTC2616/LTC2626 clear outputs zero scale when power first applied, making system initialization consistent repeatable. LTC2606-1/ LTC2616-1/LTC2626-1 voltage outputs midscale when power first applied. some applications, downstream circuits active during power-up, sensitive nonzero outputs from during this time. LTC2606/ LTC2616/LTC2626 contain circuitry reduce poweron glitch; furthermore, glitch amplitude made arbitrarily small reducing ramp rate power supply. example, power supply ramped 1ms, analog outputs rise less than 10mV above ground (typ) during power-on. Power-On Reset Glitch Typical Performance Characteristics section. Power Supply Sequencing voltage (Pin should kept within range 0.3V VREF 0.3V (see Absolute Maximum Ratings). Particular care should taken observe these limits during power supply turn-on turn-off sequences, when voltage (Pin transition. Transfer Function digital-to-analog transfer function VOUT(IDEAL) VREF where decimal equivalent binary input code, resolution VREF voltage (Pin Serial Digital Interface LTC2606/LTC2616/LTC2626 communicate with host using standard 2-wire interface. Timing Diagrams (Figures show timing relationship signals bus. lines, SCL, must high when use. External pull-up resistors current sources required these lines. value these pull-up resistors dependent
power supply obtained from specifications. operating fast mode, active pull-up will necessary capacitance greater than 200pF. LTC2606/LTC2616/LTC2626 receive-only (slave) devices. master write LTC2606/LTC2616/ LTC2626. LTC2606/LTC2616/LTC2626 respond read from master. START STOP Conditions When use, both must high. master signals beginning communication slave device transmitting START condition. START condition generated transitioning from high while high. When master finished communicating with slave, issues STOP condition. STOP condition generated transitioning from high while high. then free communication with another device. Acknowledge Acknowledge signal used handshaking between master slave. Acknowledge (active LOW) generated slave lets master know that latest byte information received. Acknowledge related clock pulse generated master. master releases line (HIGH) during Acknowledge clock pulse. slave-receiver must pull down line during Acknowledge clock pulse that remains stable during HIGH period this clock pulse. LTC2606/LTC2616/LTC2626 respond write master this manner. LTC2606/LTC2616/ LTC2626 acknowledge read (retains HIGH during period Acknowledge clock pulse). Chip Address state CA0, decides slave address part. pins CA0, each three states: VCC, float. This results selectable addresses part. slave address assignments shown Table
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LTC2606/LTC2616/LTC2626
OPERATIO
FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT
Table Slave Address
FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT
GLOBAL ADDRESS
addition address selected address pins, parts also respond global address. This address allows common write LTC2606, LTC2616 LTC2626 parts accomplished with 3-byte write transaction bus. global address 7-bit on-chip hardwired address selectable CA0, CA2. addresses corresponding states CA0, global address shown Table maximum capacitive load allowed address pins (CA0, CA2) 10pF, these pins driven during address detection determine they floating.
Write Word Protocol master initiates communication with LTC2606/ LTC2616/LTC2626 with START condition 7-bit slave address followed Write LTC2606/ LTC2616/LTC2626 acknowledges pulling clock 7-bit slave address matches address parts (set CA0, CA2) global address. master then transmits three bytes data. LTC2606/LTC2616/LTC2626 acknowledges each byte data pulling line clock each data byte transmission. After receiving three complete bytes data, LTC2606/LTC2616/LTC2626 executes command specified 24-bit input word. more than three data bytes transmitted after valid 7-bit slave address, LTC2606/LTC2616/LTC2626 acknowledge extra bytes data (SDA high during clock). format three data bytes shown Figure first byte input word consists 4-bit command four don't care bits. next bytes consist 16-bit data word. 16-bit data word consists 16-, 12-bit input code, LSB, followed don't care bits (LTC2606, LTC2616 LTC2626 respectively). typical LTC2606 write transaction shown Figure command assignments (C3-C0) shown Table first four commands table consist write update operations. write operation loads 16-bit data word from 32-bit shift register into input register. update operation, data word copied from input register register converted analog voltage output. update operation also powers been power-down mode. data path registers shown Block Diagram. Power-Down Mode power-constrained applications, power-down mode used reduce supply current whenever output needed. When power-down, buffer amplifier, bias circuit reference input disabled draws essentially zero current. output into
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LTC2606/LTC2616/LTC2626
OPERATIO
Table
COMMAND* Write Input Register Update (Power Register Write Update (Power Power Down Operation
*Command codes shown reserved should used.
high impedance state, output passively pulled ground through resistors. Input- DACregister contents disturbed during power-down. channel into power-down mode using command 0100b. 16-bit data word ignored. supply reference currents reduced almost zero when powered down; effective resistance becomes high impedance input (typically 1G). Normal operation resumed executing command which includes update, shown Table performing asychronous update (LDAC) described next section. powered voltage output updated. When powereddown state powered updated, normal settling delayed. main bias generation circuit block been
Write Word Protocol LTC2606/LTC2616/LTC1626
SLAVE ADDRESS DATA BYTE DATA BYTE
INPUT WORD
DATA BYTE
Input Word (LTC2606)
DATA BYTE
DATA BYTE
DATA BYTE
Input Word (LTC2616)
DATA BYTE
DATA BYTE
DATA BYTE
Input Word (LTC2626)
2606
DATA BYTE
DATA BYTE
DATA BYTE
Figure
automatically shut down addition amplifier reference input power delay time 12µs (for 30µs (for Asynchronous Update Using LDAC addition update commands shown Table LDAC asynchronously updates register with contents input register. Asynchronous update disabled when input word being clocked into part. complete input word been written part, LDAC causes register updated with contents input register. input word being written part, going pulse LDAC before completion three bytes data powers does cause output updated. LDAC remains after complete input word been written part, then LDAC recognized, command specified 24-bit word just transferred executed output updated. powered when LDAC taken low, independent activity bus. LDAC falling edge clock byte data, inhibits software power-down command that specified input word.
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LTC2606/LTC2616/LTC2626
OPERATIO
Voltage Output
rail-to-rail amplifier guaranteed load regulation when sourcing sinking 15mA (7.5mA 3V). Load regulation measure amplifier's ability maintain rated voltage accuracy over wide range load conditions. measured change output voltage milliampere forced load current change expressed LSB/mA. output impedance equivalent load regulation, derived from simply calculating change units from LSB/mA Ohms. amplifiers' output impedance 0.050 when driving load well away from rails. When drawing load current from either rail, output voltage headroom with respect that rail limited typical channel resistance output devices; e.g., when sinking 1mA, minimum output voltage 25mV. graph Headroom Rails Output Current Typical Performance Characteristics section. amplifier stable driving capacitive loads 1000pF. Board Layout excellent load regulation performance achieved part keeping "signal" "power" grounds separated internally reducing shared internal resistance. functions both node which reference output voltages referred return path power currents device. Because this, careful thought should given grounding scheme board layout order ensure rated performance. board should have separate areas analog digital sections circuit. This keeps digital signals away
from sensitive analog signals facilitates separate digital analog ground planes which have minimal capacitive resistive interaction with each other. Digital analog ground planes should joined only point, establishing system star ground close device's ground possible. Ideally, analog ground plane should located component side board, should allowed under part shield from noise. Analog ground should continuous uninterrupted plane, except necessary lead pads vias, with signal traces another layer. part should connected analog ground. Resistance from system star ground should possible. Resistance here will directly effective output impedance device (typically 0.050). Note that LTC2606/LTC2616/ LTC2626 more susceptible these effects than other parts their type; contrary, they allow layout-based performance improvements shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations rail-to-rail voltage output device, output limited voltages within supply range. Since analog output device cannot below ground, limit lowest codes shown Figure Similarly, limiting occur near full scale when tied VCC. VREF full-scale error (FSE) positive, output highest codes limits shown Figure full-scale limiting occur VREF less than FSE. Offset linearity defined tested over region transfer function where output limiting occur.
26061626f
SLAVE ADDRESS COMMAND DATA
DATA STOP
START
FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2606
VOUT
DON'T CARE
Figure Typical LTC2606 Input Waveform-Programming Output Full Scale
OPERATIO
LTC2606/LTC2616/LTC2626
26061626f
VREF
POSITIVE
LTC2606/LTC2616/LTC2626
VREF
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE
2606
OUTPUT VOLTAGE INPUT CODE
NEGATIVE OFFSET
INPUT CODE
Figure Effects Rail-to-Rail Operation Transfer Curve. Overall Transfer Function Effect Negative Offset Codes Near Zero Scale Effect Positive Full-Scale Error Codes Near Full Scale
OPERATIO
26061626f
LTC2606/LTC2616/LTC2626
PACKAGE DESCRIPTIO
Package 10-Lead Plastic (3mm 3mm)
(Reference 05-08-1699)
0.675 ±0.05 PACKAGE OUTLINE 0.25 0.05 0.50 2.38 ±0.05 SIDES) RECOMMENDED SOLDER PITCH DIMENSIONS 0.115 0.38 0.10 3.00 ±0.10 SIDES) MARK (SEE NOTE 0.200 0.75 ±0.05 2.38 ±0.10 SIDES) BOTTOM VIEW-EXPOSED NOTE: DRAWING MADE JEDEC PACKAGE OUTLINE M0-229 VARIATION (WEED-2). CHECK WEBSITE DATA SHEET CURRENT STATUS VARIATION ASSIGNMENT DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.15mm SIDE EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE 0.25 0.05 0.50 1.65 0.10 SIDES)
(DD10) 0403
3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 SIDES)
0.00 0.05
26061626f
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC2606/LTC2616/LTC2626
TYPICAL APPLICATIO
Demo Circuit Schematic. Onboard 20-Bit Measures Performance Parameters
LDAC VREF LTC2606 VOUT
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 LTC2600/LTC2610 LTC2620 LTC2601/LTC2611 LTC2621 LTC2602/LTC2612 LTC2622 LTC2604/LTC2614 LTC2624 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT Single 16-Bit VOUT DACs with Serial Interface SO-8 Parallel 5V/3V 16-Bit VOUT DACs Octal 10/8-Bit VOUT DACs 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output Octal 16-/14-/12-Bit VOUT DACs 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs 10-Lead Dual 16-/14-/12-Bit VOUT DACs 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs 16-Lead SSOP COMMENTS LTC1458: 4.5V 5.5V, VOUT 4.096V LTC1458L: 2.7V 5.5V, VOUT 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA 5V(3V), Power, Deglitched Power, Deglitched, Rail-to-Rail VOUT 2.7V 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling Step 250µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 250µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 300µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 250µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900 FAX: (408) 434-0507
0.1µF VREF FSSET 7.5k 100pF OUTPUT ZSSET
2606 TA01
0.1µF
LTC2421
26061626f LT/TP 1204 PRINTED
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004

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