Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 FU

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Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 FU

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FEATURES Nonvolatile Memory Preset Maintains Wiper Settings AD5231 Single, 1024 Position Resolution AD5232 Dual, Position Resolution AD5233 Quad, Position Resolution 10K, 50K, 100K Terminal Resistance Linear taper Settings Increment/Decrement Commands, Push Button Command Compatible Serial Data Input with Readback Function Single Supply ±2.5V Dual Supply Operation User EEMEM nonvolatile memory constant storage APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching Power Supply Adjustment Switch Setting
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
FUNCTIONAL BLOCK DIAGRAMS
RDAC1
RDAC1
EEMEM1
EEMEM
USER EEMEM
UTPUT FFER
EEMEM2
5232
RDAC1 RDAC1
GENERAL DESCRIPTION
AD5231/AD5232/AD5233 family provides single/dual-/quad-channel, digitally controlled variable resistor (VR) with resolutions 1024/256/64 positions respectively. These devices perform same electronic adjustment function potentiometer variable resistor. AD523X's versatile programming Micro Controller allows multiple modes operation adjustment. direct program mode predetermined setting RDAC register loaded directly from micro controller. Another mode operation allows RDAC register refreshed with setting previously stored EEMEM register. When changes made RDAC register establish wiper position, value setting saved into EEMEM executing EEMEM save operation. Once settings saved EEMEM register these values will transferred automatically RDAC register wiper position system power Such operation enabled internal preset strobe preset also accessed externally. basic mode adjustment increment decrement command controlling present setting Wiper position setting (RDAC) register. internal scratch RDAC register moved DOWN, step nominal terminal resistance between terminals A-and-B. This linearly changes wiper terminal resistance (RWB) position segment device's end-to-end resistance (RAB). exponential/logarithmic changes wiper setting, left/right shift command adjusts levels +/-6dB steps, which useful sound light alarm applications. AD523X available thin TSSOP package. parts guaranteed operate over extended industrial temperature range -40°C +85°C.
PrF, Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use; infringements patents other rights third parties, which result from use. license granted implication otherwise under patent patent rights Analog Devices.
RDAC2
CONTRO
BYTES USER
RDAC2
5233
RDAC1 RDAC1
RDAC2
CONTRO
RDAC2
USER
OUTPUT BUFFER
RDAC3
RDAC3
RDAC4
RDAC4
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax:617/326-8703 Analog Devices, Inc., 1999
PRELIMINARY TECHNICAL DATA AD5231/AD5232/AD5233 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K VERSIONS (VDD +3V±10% +5V±10% VSS=0V,
+VDD, -40°C +85°C unless otherwise noted.)
Parameter
Resistor Differential Nonlinearity2 Resistor Nonlinearity2 Nominal resistor tolerance Resistance Temperature Coefficent Wiper Resistance Wiper Resistance
Symbol
R-DNL R-INL RAB/T VW/T VWFSE VWZSE VA,B,W CA,B VDD/VSS IDD(PG) IDD(READ) PDISS
Conditions
RWB, VA=NC RWB, VA=NC 25°C, VDD,Wiper (VW) connect VDD, Wiper (VW) Connect V/R, V/R, AD5231/AD5232/AD5233
Units
ppm/°C Bits ppm/°C
CHARACTERISTICS RHEOSTAT MODE Specifications apply ±1/4 ±1/2
CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply Resolution Integral Nonlinearity3 Differential Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range4 Capacitance5 Capacitance5 Common-mode Leakage Current6 DIGITAL INPUTS OUTPUTS Input Logic High Input Logic Input Logic High Input Logic Output Logic High Output Logic High Output Logic Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current13 Negative Supply Current Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, Bandwidth -3dB Total Harmonic Distortion Settling Time Resistor Noise Voltage Crosstalk (CW1/CW2) BW_10K THDW eN_WB =1Vrms, f=1KHz VDD, VB=0V, final value 10K/50K/100K 1KHz VDD, Measure with adjacent making full scale change 0.003 1/3/6 nVHz GND, 2.5V, -2.5V ±10% ±2.25 ±2.75 0.01 with respect GND, with respect GND, with respect GND, with respect GND, RPULL-UP 2.2K 40µA, VLOGIC 1.6mA, VLOGIC MHz, measured GND, Code Half-scale MHz, measured GND, Code Half-scale VDD/2 0.01 ±1/2 ±1/4
Code Half-scale Code Full-scale Code Zero-scale
0.002
NOTES: bottom table next page.
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA AD5231/AD5232/AD5233 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K VERSIONS +3V±10% +5V±10% =0V,
+VDD, -40°C +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Units
INTERFACE TIMING CHARACTERISTICS applies parts(Notes Clock Cycle Time Input Clock Pulse Width Clock level high Setup Time Data Setup Time From Positive transition Data Hold Time From Positive transition Shutdown Time Rise Clock Rise Setup High Pulse Width Propagation Delay10 20pF Store Nonvolatile EEMEM Save Time11 Applies Command line acquire line release Rise Fall Startup Time Setup Time period period) Preset Pulse Width (Asynchronous) Preset Response Time tPRESP pulsed then high NOTES:
Typicals represent average readings +25°C +5V. Resistor position nonlinearity error R-INL deviation from ideal value measured between maximum resistance minimum resistance wiper positions. R-DNL measures relative step change from ideal between successive positions. Parts guaranteed monotonic. VDD/R both VDD=+3V VDD=+5V. measured with RDAC configured potentiometer divider similar voltage output converter. VSS. specification limits ±1LSB maximum Guaranteed Monotonic operating conditions. Resistor terminals have limitations polarity with respect each other. Guaranteed design subject production test. Common mode leakage current measure leakage from terminal common mode bias level PDISS calculated from (IDD VDD) (ISS VSS). dynamic characteristics +5V. timing diagram location measured values. input control voltages specified with tR=tF=2.5ns(10% timed from voltage level 1.5V. Switching characteristics measured using both +5V. Propagation delay depends value VDD, RPULL_UP, applications text. only instruction commands 9,10, CMD_8 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms Dual Supply Operation primarily affects terminals. Read Mode current continuous.
Timing Diagram
SDO1 SDO2
Figure Timing Diagram
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Absolute Maximum Rating +25°C, unless
otherwise noted) .-0.3, .0V, .+7V GND.VSS, Intermittent .±20mA Continuous. ±1.3mA Digital Inputs Output Voltage Operating Temperature Range -40°C +85°C Maximum Junction Temperature MAX) +150°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, sec) +300°C Package Power Dissipation (TJMAX Thermal Resistance TSSOP-16 150°C/W TSSOP-24 128°C/W
Ordering Guide
Model
AD5231BRU10 AD5231BRU10-REEL7 AD5231BRU50 AD5231BRU50-REEL7 AD5231BRU100 AD5231BRU100-REEL7 AD5232BRU10 AD5232BRU10-REEL7 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRU100 AD5232BRU100-REEL7 AD5233BRU10 AD5233BRU10-REEL7 AD5233BRU50 AD5233BRU50-REEL7 AD5233BRU100 AD5233BRU100-REEL7
Number Channels
Ohm)
Temp Range
-40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C -40/+85°C
Package Description
TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24 TSSOP-24
Package #Devices Mark Option Container
RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 1,000 1,000 1,000 1,000 1,000 1,000
AD5231/AD5232/AD5233 contains 9,646 transistors. size: mil, 7,993
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5231 CONFIGURATION
AD5232 CONFIGURATION
AD5231 FUNCTION DESCRIPTION Name Description
Non-Volatile Digital Output ADDR(O1) data position Serial Input Register clock pin. Shifts time positive clock edges. Serial Data Input Pin. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands activate output. Instruction operation Truth Table. Other commands shift previously loaded pattern delayed clock pulses. This allows daisy-chain operation multiple packages. Ground pin, logic ground reference. Negative Supply. Connect zero volts single supply applications. Used digital input during factory test mode. Leave floating connect VSS. terminal RDAC1. Wiper terminal RDAC1, ADDR(RDAC1) terminal RDAC1. Positive Power Supply Pin. Should input-logic HIGH voltage. Write Protect Pin. When active prevents changes present contents except retrieving EEMEM contents RESET. Hardware over ride preset pin. Refreshes scratch register with current contents EEMEM register. Factory default loads midscale 200H until EEMEM loaded with value user activated rising logic high transition) Serial Register chip select active low. Serial register operation takes place when returns logic high. Ready. Active-high open drain output. Identifies completion commands Non-Volatile Digital Output ADDR(O2) data position
AD5232 FUNCTION DESCRIPTION Name Description
Serial Input Register clock pin. Shifts time positive clock edges. Serial Data Input Pin. Shifts time positive clock edges. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands activate output. Instruction operation Truth Table. Other commands shift previously loaded pattern delayed clock pulses. This allows daisy-chain operation multiple packages. Ground pin, logic ground reference Negative Supply. Connect zero volts single supply applications. terminal RDAC1. Wiper terminal RDAC1, ADDR(RDAC1) terminal RDAC1. terminal RDAC2. Wiper terminal RDAC2, ADDR(RDAC2) terminal RDAC2. Positive Power Supply Pin. Should input-logic HIGH voltage. Write Protect Pin. When active low, prevents changes present contents, except retrieving EEMEM content RESET. Hardware over ride preset pin. Refreshes scratch register with current contents EEMEM register. Factory default loads midscale until EEMEM loaded with value user activated logic high transition). Serial Register chip select active low. Serial register operation takes place when returns logic high. Ready. Active-high open drain output. Identifies completion commands
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5233 CONFIGURATION
AD5233 FUNCTION DESCRIPTION Name Description
Non-Volatile Digital Output ADDR(O1) data position Serial Input Register clock pin. Shifts time positive clock edges. Serial Data Input Pin. Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands activate output. Instruction operation Truth Table. Other commands shift previously loaded pattern delayed clock pulses. This allows daisy-chain operation multiple packages. Ground pin, logic ground reference Negative Supply. Connect zero volts single supply applications. terminal RDAC1. Wiper terminal RDAC1, ADDR(RDAC1) terminal RDAC1. terminal RDAC2. Wiper terminal RDAC2, ADDR(RDAC2) terminal RDAC2. terminal RDAC3. Wiper terminal RDAC3, ADDR(RDAC3) terminal RDAC3. terminal RDAC4. Wiper terminal RDAC4, ADDR(RDAC4) terminal RDAC4. Positive Power Supply Pin. Should input-logic HIGH voltage. Write Protect Pin. When active low, prevents changes present contents, except retrieving EEMEM content RESET. Hardware over ride preset pin. Refreshes scratch register with current contents EEMEM register. Factory default loads midscale until EEMEM loaded with value user activated logic high transition). Serial Register chip select active low. Serial register operation takes place when returns logic high. Ready. Active-high open drain output. Identifies completion commands Non-Volatile Digital Output ADDR(O2) data position
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
OPERATIONAL OVERVIEW
AD5231/32/33 digital potentiometer family designed operate true variable resistor replacement device analog signals that remain within terminal voltage range VSS<VTERM<VDD. basic voltage range limited |VDD VSS| 5.5V. Control digital potentiometer allows both scratch register (RDAC register) changes made, well 100,000 nonvolatile electrically erasable memory (EEMEM) register operations. EEMEM update process takes approximately 20.2ms, during this time shift register locked preventing changes from taking place. flags completion this EEMEM save. EEMEM retention designed last years 85°C, which equivalent years 55°C, without refresh. scratch register changed incrementally using software controlled Increment/Decrement instruction Shift Left/Right instruction command. Once Increment, Decrement Shift command been loaded into shift register subsequent strobes will repeat this command. This useful push button control applications. Alternately scratch register programmed with position value using standard serial interface mode loading representative data word. scratch register loaded with current contents nonvolatile EEMEM register under program control. system power default value scratch memory value previously saved EEMEM register. factory EEMEM preset value midscale. scratch (wiper) register loaded with current contents nonvolatile EEMEM register under hardware control pulsing pin. Beware that pulse first sets wiper midscale when brought logic zero, then positive transition logic high, reloads wiper register with contents EEMEM. Similarly, saved EEMEM value will automatically retrieved scratch register during system power serial data output available daisy chaining readout internal register contents. serial input data register uses 24-bit instruction/address/data WORD. Write protect (WP) disables changes current content scratch register regardless commands, except that EEMEM setting retrieved using commands Therefore, write-protect (WP) provides hardware EEMEM protection feature. DIGITAL INPUT/OUTPUT CONFIGURATION digital inputs protected high input impedance that driven directly from most digital sources. which active logic low, tied directly they being used. pins open drain digital outputs where pull-up resistors needed only using these functions. resistor value range optimizes power switching speed trade off. SERIAL DATA INTERFACE AD523X family contains four-wire compatible digital interface (SDI, SDO, CLK). features this interface include: Independently Programmable Read Write registers Direct parallel refresh RDAC wiper registers from corresponding internal EEMEM registers Increment Decrement instructions each RDAC wiper register Left right Shift RDAC wiper registers achieve level changes Nonvolatile storage present scratch RDAC register values into corresponding EEMEM register Extra bytes user addressable electrical-erasable memory serial interface contains three different word formats support single AD5231, dual AD5232, quad AD5233 digital potentiometer devices. AD5232 AD5233 16-bit serial data word loaded first, while AD5231 uses 24-bit serial word loaded first. format compatible word shown Table Command Bits (Cx) control operation digital potentiometer according command instructions shown Table Address Bits (Ax) determine which register activated. Data Bits (Dx) values that loaded into decoded register. last instruction executed prior period programming activity should OPeration (NOP) instruction. This will place internal logic circuitry minimum power dissipation state.
MMAND UNTER MMAND PROCESSOR ADDRESS DECODE
Figure Equivalent Digital Input-Output Logic equivalent serial data input output logic shown figure open drain output disabled whenever chip select logic high. interface used slave modes CPHA=1, CPOL=1 CPHA=0, CPOL=0. CPHA CPOL refer control bits, which dictate timing following microprocessors/Micro Converters: ADuC812/824, M68HC11, MC68HC16R1/916R1.
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table AD5232 AD5233 16-bit Serial Data Word AD5232 AD5233
Table AD5231 24-bit Serial Data Word AD5231 Command bits identified address bits data bits Command instruction codes defined tables
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table AD5231 Instruction/Operation Truth Table
Inst Instruction Byte ADDR ADDR ADDR ADDR Data Byte Data Byte Operation
Operation (NOP): nothing Write contents EEMEM(ADDR) RDAC(ADDR) Register SAVE WIPER SETTING: Write contents RDAC(ADDR) EEMEM(ADDR) Write contents Serial Register Data Byte EEMEM(ADDR) Decrement 6dB: Right Shift contents RDAC(ADDR), stops "Zeros". Decrement 6dB: Right Shift contents RDAC Registers, stops "Zeros". Decrement contents RDAC(ADDR) "One", stops "Zeros". Decrement contents RDAC Register "One", stops "Zeros". RESET: Load RDACs with their corresponding EEMEM previously-saved values Write contents EEMEM(ADDR) Serial Register Data Byte Write contents RDAC(ADDR) Serial Register Data Byte Write contents Serial Register Data Byte RDAC(ADDR) Increment 6dB: Left Shift contents RDAC(ADDR), stops "Ones". Increment 6dB: Left Shift contents RDAC Registers, stops "Ones". Increment contents RDAC(ADDR) "One", stops "Ones". Increment contents RDAC Register "One", stops "Ones".
ADDR
ADDR ADDR ADDR ADDR
ADDR
NOTES: output shifts-out last 16-bits data clocked into serial register daisy chain operation. Exception: following Instruction selected internal register data will present data byte Instructions following must full 24-bit data word completely clock contents serial register. RDAC register volatile scratch register that refreshed power from corresponding non-volatile EEMEM register. increment, decrement shift commands ignore contents shift register Data Byte Execution Operation column noted table takes place when strobe returns logic high.
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table AD5232 Instruction/Operation Truth Table
Inst Instruction Byte ADDR ADDR ADDR ADDR Data Byte Operation
Operation (NOP): nothing Write contents EEMEM(ADDR) RDAC(ADDR) Register SAVE WIPER SETTING: Write contents RDAC(ADDR) EEMEM(ADDR) Write contents Serial Register Data Byte EEMEM(ADDR) Decrement 6dB: Right Shift contents RDAC(ADDR) stops "Zeros". Decrement 6dB: Right Shift contents RDAC Registers, stops "Zeros". Decrement contents RDAC(ADDR) "One", stops "Zeros". Decrement contents RDAC Registers "One", stops "Zeros". RESET: Load RDACs with their corresponding EEMEM previously-saved values Write contents EEMEM(ADDR) Serial Register Data Byte Write contents RDAC(ADDR) Serial Register Data Byte Write contents Serial Register Data Byte RDAC(ADDR) Increment 6dB: Left Shift contents RDAC(ADDR), stops "Ones". Increment 6dB: Left Shift contents RDAC Registers, stops "Ones". Increment contents RDAC(ADDR) "One", stops "Ones". Increment contents RDAC Registers "One", stops "Ones".
ADDR
ADDR ADDR ADDR ADDR
ADDR
NOTES: output shifts-out last 8-bits data clocked into serial register daisy chain operation. Exception: following Instruction selected internal register data will present data byte Instructions following must full 16-bit data word completely clock contents serial register. RDAC register volatile scratch register that refreshed power from corresponding non-volatile EEMEM register. increment, decrement shift commands ignore contents shift register Data Byte Execution Operation column noted table takes place when strobe returns logic high.
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table AD5233 Instruction/Operation Truth Table
Inst Instruction Byte ADDR ADDR ADDR ADDR Data Byte Operation
Operation (NOP): nothing Write contents EEMEM(ADDR) RDAC(ADDR) Register SAVE WIPER SETTING: Write contents RDAC(ADDR) EEMEM(ADDR) Write contents Serial Register Data Byte EEMEM(ADDR) Decrement 6dB: Right Shift contents RDAC(ADDR), stops "Zeros". Decrement 6dB: Right Shift contents RDAC Registers, stops "Zeros". Decrement contents RDAC(ADDR) "One", stops "Zeros". Decrement contents RDAC Registers "One", stops "Zeros". RESET: Load RDACs with their corresponding EEMEM previously-saved values Write contents EEMEM(ADDR) Serial Register Data Byte Write contents RDAC(ADDR) Serial Register Data Byte Write contents Serial Register Data Byte RDAC(ADDR) Increment 6dB: Left Shift contents RDAC(ADDR), stops "Ones". Increment 6dB: Left Shift contents RDAC Registers, stops "Ones". Increment contents RDAC(ADDR) "One", stops "Ones". Increment contents RDAC Registers "One", stops "Ones".
ADDR
ADDR ADDR ADDR ADDR
ADDR
NOTES: output shifts-out last 8-bits data clocked into serial register daisy chain operation. Exception: following Instruction selected internal register data will present data byte Instructions following must full 16-bit data word completely clock contents serial register. wiper only positions that correspond lower 6-bits register data. RDAC register volatile scratch register that refreshed power from corresponding non-volatile EEMEM register. increment, decrement shift commands ignore contents shift register Data Byte Execution Operation column noted table takes place when strobe returns logic high.
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Latched Digital Outputs pair digital outputs, available AD5231, AD5233 parts that provide nonvolatile logic logic setting. standard CMOS logic outputs shown figure These outputs ideal replace functions often provided switches. addition, they used drive other standard CMOS logic controlled parts that need occasional setting change.
OUTPUTS
Detail Programmable Potentiometer Operation actual structure RDAC designed emulate performance mechanical potentiometer. RDAC contains string connected resistor segments, with array analog switches that wiper connection several points along resistor array. number points resolution device. example, AD5232 connection points allowing provide better than 0.5% setability resolution. Figure provides equivalent diagram connections between three terminals that make channel RDAC. will always while switches SW(0) SW(2N-1) will time depending upon resistance step decoded from Data Bits. Note there wiper resistances, resistance contributed must accounted output resistance. terminals A-to-wiper, resistances SWX. Similarly, resistances terminals B-to-Wiper.
Figure Logic Outputs Using Additional internal Nonvolatile EEMEM AD523x family devices contains additional internal user storage registers (EEMEM) saving constants other 8-bit data. Table provides address internal storage registers shown functional block diagrams EEMEM1, EEMEM2, EEMEMn, bytes USER EEMEM. Table EEMEM Address EEMEM Address (ADDR) 0000 0001 0010 0011 0100 0101 1111 AD5231 (16B) RDAC USER USER USER USER USER EEMEM Contents each device EEMEM(ADDR) AD5232 (8B) RDAC1 RDAC2 USER USER USER USER USER AD5233 (8B) RDAC1 RDAC2 RDAC3 RDAC4 USER USER
DECO
Figure Equivalent RDAC structure
TEST CIRCUITS Figures define test conditions used product specification's table.
NOTES: RDAC data stored EEMEM locations transferred their corresponding RDAC REGISTER Power when following instructions executed Inst#1 Inst#8. data stored EEMEM locations transferred their corresponding DIGITAL REGISTER Power when following instructions executed Inst#1 Inst#8. USER data internal nonvolatile EEMEM registers available store retrieve constants using Inst#3 Inst#9 respectively. AD5231 EEMEM locations bytes each (16-bits) data, while AD5232 AD5233 byte each (8-bits).
Figure Potentiometer Divider Nonlinearity error test circuit (INL, DNL)
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Figure Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure X14. Incremental Resistance Test Circuit
Figure Wiper Resistance test Circuit
Figure X15. Common Mode Leakage current test circuit
TYPICAL PERFORMANCE GRAPHS Figure X10. Power supply sensitivity test circuit (PSS, PSSR)
Figure X11. Inverting Gain test Circuit
Figure X12. Non-Inverting Gain test circuit
Figure X13. Gain Frequency test circuit
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
OUTLINE DIMENSIONS
Dimensions shown inches (mm)
Information contained this Preliminary data sheet describes product early definition stage. There guarantee that information contained here will become final product present form. latest information contact Walt Heinzer/Analog Devices, Santa Clara, TEL(408)382-3107; (408)382-2708; walt.heinzer@analog.com

Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233 FU

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