128K CMOS DUAL-PORT STATIC MODULE IDT7M1001 IDT7M1003 FEATUR

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128K CMOS DUAL-PORT STATIC MODULE IDT7M1001 IDT7M1003 FEATUR

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128K CMOS DUAL-PORT STATIC MODULE
IDT7M1001 IDT7M1003
FEATURES
High-density 1M/512K CMOS Dual-Port Static module Fast access times: -Commercial 40ns -Military 50ns Fully asynchronous read/write operation from either port Full on-chip hardware support semaphore signaling between ports Surface mounted (leadless chip carriers) components 64-pin sidebraze (Dual In-line Package) Multiple pins maximum noise immunity Single (±10%) power supply Input/outputs directly TTL-compatible
CONFIGURATION(1)
R/WL
SEML
A10L A11L A12L A13L A14L A15L A16L
R/WR
SEMR
A10R A11R A12R A13R A14R A15R A16R
IDT7M1001/IDT7M1003 128K 8/64K highspeed CMOS Dual-Port Static module constructed multilayer ceramic substrate using eight IDT7006 (16K Dual-Port RAMs FCT138 decoders depopulated using only four IDT7006s decoders. This module provides independent ports with separate control, address, pins that permit independent asynchronous access reads writes location memory. System performance enhanced facilitating port-to-port communication semaphore (SEM) "handshake" signaling. IDT7M1001/1003 module designed used stand-alone Dual-Port where on-chip hardware port arbitration needed. users responsibility ensure data integrity when simultaneously accessing same memory location from both ports. IDT7M1001/1003 module packaged multilayer co-fired ceramic 64-pin (Dual In-line Package) with dimensions only 3.2" 0.62" 0.38". Maximum access times fast 35ns over commercial temperature range available. inputs outputs IDT7M1001/1003 TTLcompatible operate from single supply. Fully asynchronous circuitry used, requiring clocks refreshing operation module. military module semiconductor components manufacured compliance with latest revision MILSTD-883, Class making them ideally suited applications demanding highest level performance reliability.
NAMES
Left Port (0-16)L (0-7)L R/WL
SEML
Right Port (0-16)R (0-7)R R/WR
SEMR
Description Address Inputs Data Inputs/Outputs Read/Write Enables Chip Select Output Enable Semaphore Control Power Ground
2804
2804
VIEW
NOTE: IDT7M1003 (64K version, Pins must connected proper operation module.
logo registered trademark
MILITARY COMMERCIAL TEMPERATURE RANGES
©1995
MARCH 1995
DSC-7066/5
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM 7M1001
L_A16 L_A15 L_A14
L_CS
74FCT138 74FCT138 R_CS
L_A0-13 L_OE L_R/W
L_I/O0-7
7006
7006
7006
L_SEM
7M1003
L_A15 L_A14
L_CS
74FCT138 74FCT138 R_CS
L_A0-13 L_OE L_R/W
L_I/O0-7
7006
7006
7006
L_SEM
7025
7006
7006
7006
7006 R_I/O0-7
R_R/W R_OE R_A0-13
R_A14 R_A15 R_A16 7006
R_SEM
2804
R_I/O0-7
R_R/W R_OE R_A0-13
R_A14 R_A15 7006
R_SEM
2804
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect Operating Temperature Temperature Under Bias Storage Temperature Output Current Commercial -0.5 +7.0 Military -0.5 +7.0 Unit
RECOMMENDED OPERATING TEMPERATURE SUPPLY VOLTAGE
Grade Military Ambient Temperature -55°C +125°C +70°C 5.0V 5.0V
2804
TBIAS TSTG IOUT
+125 +125
+125 +135 +150
Commercial
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
2804
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Min. -0.5
(1)b
Typ.
Max.
Unit
2804
CAPACITANCE(1) +25°C, 1.0MHz)
Symbol CIN1 CIN2 Parameter Input Capacitance
Test Conditions
Max.
Unit
NOTE: (min.) -3.0V pulse width less than 20ns.
Input Capacitance
(Data, Address, Other Controls)
COUT
Output Capacitance
(Data)
VOUT
2804
NOTE: This parameter guaranteed design tested.
ELECTRICAL CHARACTERISTICS
(VCC 10%, -55°C +125°C +70°C) Commercial Symbol ICC2 ICC1 ISB1 Parameter Dynamic Operating Current (Both Ports Active) Standby Supply Current (One Port Active) Standby Supply Current (TTL Levels) Full Standby Supply Current (CMOS Levels) Test Conditions Max., VIL, Outputs Open, fMAX Max., L_CS R_CS Outputs Open, fMAX Max., L_CS R_CS Outputs Open, fMAX L_SEM R_SEM -0.2V ISB2 L_CS R_CS -0.2V 0.2V 0.2V L_SEM R_SEM -0.2V Min. Max.
Military
Max.
Min. Max.(1) Max.(2) Unit 1130
NOTES: IDT7M1001 (128K version only. IDT7M1003 (64K version only.
2804
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS
(VCC=5.0V 10%, -55°C +125°C +70°C)
Symbol |ILI| |ILI| |ILO| Parameter Input Leakage (Address, Data Other Controls) Input Leakage SEM) Output Leakage (Data) Output Voltage Output High Voltage Test Conditions Max. Max.
IDT7M1001 Min. Max.
IDT7M1003 Min. Max.
Unit
2804
Max. VIH, VOUT -4mA
Min. Min.
TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V 1.5V 1.5V Figures
2804
DATAOUT DATAOUT
2804
2804
Figure Output Load
Figure Output Load (for tCLZ, tCHZ, tOLZ. tOHZ, tWHZ, tOW) *Including scope jig.
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS
(VCC 5.0V 10%, -55°C +125°C +70°C)
Symbol
Read Cycle tACS(2) tCLZ(1) tCHZ tOLZ
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time Address Access Time Chip Select Access Time Output Enable Access Time Output Hold From Address Change Chip Select Output Low-Z Chip Deselect Output High-Z Output Enable Output Low-Z Output Disable Output High-Z Chip Select Power-Up Time Chip Disable Power-Down Time
tOHZ
tPU(1) tPD(1) tSOP
Flag Update Pulse SEM)
Write Cycle tAS1(3) tAS2 tDH(4) tOHZ(1) tWHZ(1) tOW(1, tSWRD tSPS
Write Cycle Time Chip Select End-of-Write Address Valid End-of-Write Address Set-up Write Pulse Time Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Data Hold Time Output Disable Output High-Z Write Enable Output High-Z Output Active from End-of-Write
Flag Write Read Time Flag Contention Window
Port-to-Port Delay Timing tWDD(5) tDDD(5) Write Pulse Data Delay Write Data Valid Read Data Valid
2804
NOTES: This parameter guaranteed design tested. access VIH. access semaphore, VIL. tAS1= asserted simultaneously with after transition. controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns. Port-to-Port delay through cells from writing port reading port.
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM READ CYCLE (EITHER SIDE)(1,2,4)
ADDRESS
DATA
PREVIOUS DATA VALID
DATA VALID
2804
TIMING WAVEFORM READ CYCLE (EITHER SIDE)(1,3,5)
DATA CURRENT
DATA VALID
NOTES: HIGH Read Cycles Device continuously enabled. LOW. This waveform cannot used semaphore reads. Addresses valid prior coincident with transition LOW. LOW. access RAM, LOW, access semaphore, HIGH LOW. This parameter guaranteed design tested.
2804
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM WRITE CYCLE (R/W CONTROLLED TIMING)(1,3,5,8)
ADDRESS
WP(2)
DATA
DATA
DATA VALID
2804 NOTES: HIGH Read Cycles Device continuously enabled. LOW. LOW. This waveform cannot used semaphore reads. Addresses valid prior coincident with transition low. LOW. access RAM, LOW, LOW, access semaphore, HIGH LOW. Timing depends which enable signal asserted last. Timing depends which enable signal de-asserted first. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. HIGH during controlled write cycle, this requirement does apply write pulse width short specified tWP. This parameter guaranteed design tested.
TIMING WAVEFORM WRITE CYCLE CONTROLLED TIMING)(1,3,5,8)
ADDRESS
DATA
DATA VALID
2804 NOTES: must HIGH during address transitions. write occurs during overlap (tWP) memory array writing cycle. measured from earlier R/W) going HIGH write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition, outputs remain high-impedance state. Timing depends which enable signal asserted last. Timing depends which enable signal de-asserted first. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. HIGH during controlled write cycle, this requirement does apply write pulse short specified tWP. This parameter guaranteed design tested.
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
VALID ADDRESS
VALID ADDRESS
DATA
DATA VALID
DATA VALID
SWRD
WRITE CYCLE READ CYCLE
2804
NOTE: HIGH duration above timing (both write read cycle).
TIMING WAVEFORM SEMAPHORE CONTENTION(1,3,4)
MATCH
SIDE
MATCH
SIDE
2804
NOTES: LOW, L_CS R_CS HIGH. Semaphore Flag released form both sides (reads ones from both sides) cycle start. either left right port. opposite port from "A". This parameter measured from R/WA SEMA going HIGH SEMB going HIGH. tSPS violated, semaphore will fall positively side other, there guarantee which side will obtain flag.
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM WRITE WITH PORT-TO-PORT DELAY(1)
ADDR
MATCH
DATA
VALID
ADDR
MATCH
DATA
VALID
NOTE: L_CS R_CS LOW.
WRITE CYCLE LEFT PORT
READ CYCLE RIGHT PORT
2804
TRUTH TABLES TABLE NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
Outputs
I/O0 I/O7 High-Z DATAIN DATAOUT High-Z
Mode Deselected: Power Down Write Both Bytes Read Both Bytes Outputs Disabled
2804
NOTE: A12R
TABLE SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
I/O0 I/O7 DATAOUT DATAIN
Mode Read Data Semaphore Flag Write DIN0 into Semaphore Flag Allowed
2804
NOTE: A12R
SEMAPHORE OPERATION
more details regarding semaphores semaphore operations, please consult IDT7006 datasheet.
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS 7M1001
3.190 3.210 0.615 0.635
0.605 0.625 PIN1 0.010 0.050
VIEW
0.330 MAX.
0.380 MAX.
0.007 0.013
SIDE VIEW
0.035 0.060
0.015 0.022
0.100 TYP.
0.125 0.175
SIDE VIEW
BOTTOM VIEW
2804
7M1003
3.190 3.210 0.605 0.625 0.615 0.635
PIN1 0.010 0.070
VIEW
0.310 MAX.
0.380 MAX.
0.007 0.013
SIDE VIEW
0.035 0.060
0.015 0.022
0.100 TYP.
0.125 0.175
SIDE VIEW
BOTTOM VIEW
2804
IDT7M1001/1003 128K/64K CMOS DUAL-PORT STATIC MODULE
MILITARY COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX Device type Power Speed Package Process/ Temperature range BLANK Commercial (0°C +70°C) Military (-55°C +125°C) Semiconductor components compliant MIL-STD-883, Class Sidebraze (Dual In-line Package) (Commercial Only) Nanoseconds (Military Only) Standard Power
7M1001 128K Dual-Port Static Module 7M1003 Dual-Port Static Module
2804

128K CMOS DUAL-PORT STATIC MODULE IDT7M1001 IDT7M1003 FEATUR

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