Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER DUA
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PCM1750P PCM1750U
Dual CMOS 18-Bit Monolithic Audio ANALOG-TO-DIGITAL CONVERTER
DUAL 18-BIT LOW-POWER CMOS AUDIO CONVERTER FAST 4.5µs CONVERSION TIME INCLUDING VERY THD+N: -88dB Without External Adjust COMPLETE WITH INTERNAL REFERENCE DUAL FUNCTION CO-PHASE SAMPLED, ±2.75V AUDIO INPUTS CAPABLE CHANNEL OVERSAMPLING RATE RUNS SUPPLIES DISSIPATES 300mW COMPACT 28-PIN PLASTIC SOIC
DESCRIPTION
PCM1750 cost, dual 18-bit CMOS analog-to-digital converter optimized dynamic signal applications. PCM1750 features true co-phased inputs with internal sample/hold function each channel. PCM1750 also comes complete with internal reference. Total power dissipation less than 300mW using voltage supplies. maximum Total Harmonic Distortion Noise (-88dB max) 100% tested. very fast PCM1750 capable audio bandwidth oversampling rates both input channels simultaneously, providing greater freedom designers selecting input anti-aliasing filters. PCM1750 outputs serial data format that compatible with many digital filter chips comes packaged space saving 28-pin plastic SOIC.
Left Offset Left Left Left Reference CDAC Left Comp Latch Shift Register Control Logic SOUT Right Right Offset Right Right Comp CDAC Right Reference Latch 18-Bit 18-Bit
Clock Convert
International Airport Industrial Park Mailing Address: 11400 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP 1990 Burr-Brown Corporation
Tucson, 85734 Street Address: 6730 Tucson Blvd. Tucson, 85706 Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
PDS-1084B
PCM1750
Printed U.S.A. October, 1993
SBAS007
SPECIFICATIONS
ELECTRICAL
25°C, ±5.0V; +5.0V, unless otherwise noted. Where relevant, specifications apply both left right input/output channels. PCM1750P, PARAMETER RESOLUTION DYNAMIC RANGE ANALOG INPUT Input Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Full Power Input Bandwidth DIGITAL INPUT/OUTPUT Logic Family Logic Level: Output Data Format Convert Command Convert Command Pulse Width Conversion Time -60dB Referred Full Scale CONDITIONS ±2.75 CMOS Compatible ±5µA ±5µA ISOURCE 1.0mA ISINK 3.2mA +3.5 -0.3 +2.7 +1.5 UNITS Bits psrms
Throughput Including Sample/Hold(2)
+4.7 +0.2 +0.4 Serial, First, BTC(1) Positive Edge 20.8
DYNAMIC CHARACTERISTICS (20Hz 24kHz; data decimated Signal-to-Noise Ratio(3) Total Harmonic Distortion N(7) 1kHz (0dB) 1kHz (-20dB) 1kHz (-60dB) Channel Separation ACCURACY Gain Error Gain Mismatch (Bipolar Zero) Error(8) Error Mismatch Differential Linearity Error(9) Linearity Error Warm-up Time DRIFT (With Internal Reference) Gain Bipolar Zero DRIFT (Exclusive Internal Reference) Gain Bipolar Zero REFERENCE VREF Output (Pins 24): Voltage Current Impedance Accuracy Drift VREF Input (Pins P25): Impedance(11) POWER SUPPLY REJECTION POWER SUPPLY REQUIREMENTS Supply Voltage Range Supply Voltage Range +IA; Combined Supply Current Supply Current Power Dissipation TEMPERATURE RANGE Specification Operating Storage 192kHz(4); 1kHz (0dB)(5) Without External Adjustments 192kHz 192kHz 192kHz 192kHz; 1kHz (0dB) +108 ±0.5 ±0.002 ±0.003 dB(6) FSR(10) ppm/°C FSR/°C ppm/°C FSR/°C
Channel Channel Channel Channel
±2.0
70°C 70°C 70°C 70°C
70°C
+2.75 ±100
ppm/°C ±5.25 +5.25
VSUPPLY (12) ±4.75 +4.75 +VA; +5.0V -5.0V ±5.0V; +5.0V
0.03 ±5.00 +5.00
+100
NOTES: Binary Two's Complement coding. PCM1750 tested guaranteed 5.2µs, however will operate 4.5µs. dynamic performance guaranteed tested this conversion rate. Ratio SignalRMS (DistortionRMS NoiseRMS). converter sample frequency 48kHz; oversampling channel). converter input frequency (signal level). Referred input signal level. Ratio (DistortionRMS NoiseRMS) SignalRMS. Externally adjustable zero error. Differential non-linearity error bipolar major carry input code. Externally adjustable zero error. (10) Full scale range (5.50V). (11) Refer equivalent circuit Figure (12) Worst case operating condition. Refer typical performance curves.
PCM1750
ASSIGNMENTS
DESCRIPTION Analog Supply Voltage Analog Supply Voltage Serial Output (Left Channel) External Clock Input Analog Supply Voltage Digital Voltage Supply Digital Voltage Supply Digital Common Connection Analog Common Connection Digital Common Connection Convert Command Input Serial Output (Right Channel) Analog Supply Voltage Analog Supply Voltage Offset Adjust (Right Channel) Adjust (Right Channel) Analog Voltage Input (Right Channel; ±2.75V) Reference Voltage Input (Right Channel) Reference Voltage Output (Right Channel) Analog Common Connection Reference Voltage Decouple Reference Common Connection Analog Common Connection Reference Voltage Output (Left Channel) Reference Voltage Input (Left Channel) Analog Voltage Input (Left Channel; ±2.75V) Adjust (Left Channel) Offset Adjust (Left Channel) MNEMONIC SOUTL DCOM ACOM DCOM CONVERT SOUTR OFFADJR MSBADJR VINR VREFINR VREFOUTR ACOM VREFCAP RCOM ACOM VREFOUTL VREFINL VINL MSBADJL OFFADJL
ABSOLUTE MAXIMUM RATINGS
Analog Input Voltage (VIN) -0.3V 0.3V +VA; ACOM/DCOM ACOM/DCOM +VA; +14V ACOM DCOM Digital Inputs (pins DCOM -0.3V 0.3V Power Dissipation 400mW Lead Temperature, (soldering 10s) +300°C Junction Temperature 165°C Thermal Resistance, Plastic 80°C/W Thermal Resistance, Plastic SOIC 100°C/W NOTE: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. Exposure absolute maximum conditions extended periods affect device reliability.
PACKAGE INFORMATION
MODEL PCM1750P PCM1750U PACKAGE 28-Pin Plastic 28-Pin Plastic SOIC PACKAGE DRAWING NUMBER(1)
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
TYPICAL PERFORMANCE CURVES
25°C, ±5.0V; +5V, unless otherwise noted. Where relevant, specifications apply both left right input output channels.
THD+N FREQUENCY (With Digital Filter) -60dB
THD+N (dB)
THD+N FREQUENCY (Without Digital Filter) -60dB
THD+N (dB)
-40dB -20dB -100 Frequency (kHz)
-40dB
-20dB
-100 Frequency (kHz)
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
PCM1750
TYPICAL PERFORMANCE CURVES
(CONT)
25°C, ±5.0V; +5.0V, unless otherwise noted. Where relevant, specifications apply both left right input-output channels.
FREQUENCY (With Digital Filter)
FREQUENCY (Without Digital Filter)
(dB) (dB)
-100
-100
-110 Frequency (kHz)
-110 Frequency (kHz)
FREQUENCY (-5V SUPPLY)
FREQUENCY (+5V SUPPLIES)
SUPPLY
0.01 SUPPLY 0.001
0.01 BPZ: VSUPPLY
BPZ: VSUPPLY
0.001
0.0001 Frequency (Hz) 100k
0.0001 Frequency (Hz) 100k
TEMPERATURE (VREF Outputs) 2.80
Amplitude (dB)
850Hz (24kHz 2048 POINTS)
2.78
-100 -125 -150
VREF
2.76
2.74
2.72
2.70 Temperature
Frequency (kHz)
PCM1750
TYPICAL PERFORMANCE CURVES
(CONT)
25°C, ±VA; ±5V, unless otherwise noted. Where relevant, specifications apply both left right input-output channels.
20kHz (24kHz 2048 POINTS)
Amplitude (dB)
17kHz 21kHz (24kHz 16384 POINTS) -6dB
Amplitude (dB)
-100 -125 -150 Frequency (kHz)
-100 -125 -150 Frequency (kHz)
3.7kHz (96kHz 2048 POINTS)
Amplitude (dB)
52kHz (96kHz 2048 POINTS)
Amplitude (dB)
-100 -125 -150 Frequency (kHz)
-100 -125 -150 Frequency (kHz)
92kHz (96kHz 2048 POINTS)
88kHz 92kHz (96kHz 16384 POINTS)
Amplitude (dB)
-6dB
Amplitude (dB)
-100 -125 -150 Frequency (kHz)
-100 -125 -150 Frequency (kHz)
PCM1750
THEORY OPERATION
OVERVIEW PCM1750 dual 18-bit successive approximation CMOS analog-to-digital converter with serial data outputs designed especially digital audio similar applications. single-chip converter fabricated P-well CMOS process which includes poly-poly capacitors, lasertrimmable nichrome resistors, layers interconnect metal. dual converter employs switched capacitor architecture which provides separate, simultaneous (sample/hold) functions each input channel. separate each channel results desired feature called
VREF
co-phase sampling which means that both circuits switched same time into HOLD mode capture their respective input signals simultaneously. This eliminates phasing errors produced alternative architecture ADCs which sample input channels same time. Switched binary-weighted poly-poly capacitors used CDAC (capacitive digital-to-analog converter) configurations form successive approximation converter sec-
CDAC
(MSB) 20PF 10PF
Latch Comparator Data
Auto-Zeroed Comparator
P18,
VREF 2.75V 13.25k (+5V)
P19,
VREFIN
VREFOUT
150k
TDAC
(+5V)
P18,
P16,
VREFIN
120pF (Code dependent)
.01µF
Simplified VREFIN Circuit
C12T R12a (+5V) S12T Coff 100mV Soff 13.25k offb .01µF R12b Roffa P15,
Optional External Adjustment Circuitry
FIGURE PCM1750 Simplified Circuit Diagram.
PCM1750
tions PCM1750. other switched-capacitor TDACs (trim-DACs, which employ laser-trimmed nichrome resistors) also used provide small correction voltages latching comparators. These small correction voltages compensate ratio matching errors binary-weighted capacitors CDAC. comparators contain autozeroed preamplifier stages ahead latching amplifier stage produce bit, serial data stream that controls successive approximation algorithm each channel PCM1750. simplify user application, PCM1750 includes internal band-gap reference with fast settling buffer amplifiers drive CDACs. dual converters operate synchronously minimize digital noise conversion errors) using external system clock (normally standard 48kHz audio sampling rate). operating oversampling rate roll-off requirement input anti-aliasing filters relaxed. example, systems typically pole (low pass filter) whereas system smaller) order filter when appropriate digital filter such DF1750 used conjunction with sampling system. Oversampling also added benefit improved signal noise ratio total harmonic distortion. serial outputs, each
*Master System Clock
input channel, provide binary-two's-complement coded output optional external digital decimation filter when over sampling operation desired. optional companion digital filter, DF1750, described later installation application sections this product data sheet. separate product data sheet also available Burr-Brown DF1750 giving specifications performance diagrams associated with this digital filter. SAMPLE (TRACKING) MODE After each conversion, dual returns SAMPLE mode order track input signals. switches shown simplified circuit diagram Figure will then following states: connects connect VREF; connect plates capacitor arrays analog common; latching comparator switched into auto-zero mode closing AZ4. Notice that serves purposes: samples stores input signal CDAC. Storing VREF creates bipolar offset, enabling cover span from -VREF +VREF. noise well input offset voltage comparator removed autozeroing cycle which
(CONVERT)
(EXT
INTERNAL CONTROL
HOLD
SAMPLE
test time
test time
test time
(SOUT
(SOUT
Clock from optional digital filter chip (DF1750 decimation filter).
FIGURE PCM1750 Input/Output Timing Diagram.
PCM1750
occurs during SAMPLE period (see timing diagram shown Figure These errors stored coupling capacitors (CAZ1 CAZ4, shown Figure between gain stages. During SAMPLE period inputs gain stages latch grounded switches AZ4. Capacitors CAZ1 CAZ2 track amplified offset voltage gain stage capacitors CAZ3 CAZ4 same beginning conversion cycle, autozeroing switches open instantaneous amplified value both offset voltage low-frequency flicker noise stored coupling capacitors produce zero comparator offset during conversion cycle. SUCCESSIVE APPROXIMATION CONVERSION PROCESS timing diagram Figure illustrates successive approximation routine PCM1750. Control signals CONVERT derived from master system clock which comes from 256fS (256 base sampling frequency 48kHz) clock used optional digital filter. There clocks shown timing diagram because PCM1750 shown operating times standard 48kHz sample rate (192kHz). Several events occur rising edge CONVERT command. Switches AZ4, open switch reconnects capacitor, from
TREF *Optional Digital Filter Convert
analog common (see Figure This terminates comparator auto-zero cycle simultaneously switches (cophase sampling) both converters from tracking their respective input signals into HOLD mode, thus capturing instantaneous value (with small delay specified aperture time). start conversion cycle when switched analog common, sampled input signal will appear comparator input -VIN/2 2-to-1 capacitive divider action C18. somewhat similar manner, VREF transferred comparator input -VREF/2 create bipolar offset. 19-bit shift register, shown Figure controls testing bits dual ADCs beginning with bit-1 (MSB) proceeding time bit-18 (LSB), leaving those bits that don't cause cumulative value CDAC exceed original input value leaving those bits that Since bits both channels tested together, only shift register required control both ranks data latches. example, testing bit-2 proceeds following manner. positive pulse from second shift register element SR2, (see Figure applied bit-2 data latch gate. gate turn drives switches bit-2 beginning bit-2 test interval. Note that interval must long enough allow both comparator input settle comparator respond.
SOUT PARAMETER TREF) TREF) TREF) TREF) TREF) TREF) TCONV TREF) TREF (Sample Rate /64) DESCRIPTION Convert Command High Acquisition Time Convert Clock time Master Clock Input Clock High Clock Data Hold Time Data Setup Time Data Valid Time Conversion Throughput Time Digital Filter Clock 1302 1212 20.8 UNITS
NOMINAL
Note: nominal timing shown this diagram done automatically DF1750 digital filter. Only optional digital filter clock required when DF1750 used.
FIGURE PCM1750 Setup Hold Timing Diagram.
PCM1750
next rising edge CLKIN, test interval, comparator latch strobed, providing feedback logic level which tells second data latch bit-2 should kept rejected. This logic level stored data latch passed switch gate falling edge pulse from SR2. This decision keep reject bit-2 moves comparator input closer null condition, namely, zero potential. This sequential process continues bit-3 through bit-18 nulls comparator inputs within value limited total system noise resolution/speed comparator. Notice from timing diagram Figure that successive approximation algorithm operates synchronously with external clock minimize digitally-coupled switching noise from corrupting either sample-to-hold operation critical comparator decisions. serial output data streams derived synchronously from respective latched comparator outputs available after delay CLKIN cycle illustrated Figure serial output driver cells CMOS compatible. DIFFERENTIAL LINEARITY CALIBRATION understand calibration PCM1750 necessary discuss some characteristics poly-poly capacitors. Poly capacitors known have equal better stability matching properties when compared other precision components such thin film resistors. well
Serial Data From Latching Comparator Switches Left
controlled process, ratio matching typically 0.1% very respectable number untrimmed component. Even more impressive their ratio tracking versus temperature approximately 0.1ppm/°C. Achieving (differential linearity error) less than 16-bit level requires ratio matching more significant bits about 0.001%. Since untrimmed ratio matching poly capacitors about orders magnitude larger than this requirement, one-time factory calibration upper bits required described next section. Next, consider effect temperature ratio tracking 0.lppm/°C. Over 50°C span, will change less than 1LSB 18-bits; therefore, recalibration temperature extremes necessary. Because this excellent stability versus temperature (and versus time, also), one-time factory calibration correct initial more than satisfactory meeting accuracy requirements PCM1750. TDAC OPERATION Operation TDAC (trim DAC), which laser trimmed wafer level, described using bit-1 example. Switch (see Figure operates between voltage levels-a reference level voltage divider laser trimmable level R1a, R1b. differences these levels coupled capacitor minus input comparator generate correction voltage
Switches Left Switches Left
Data Latches Left Channel
19-Bit Shift Register
SR18
SR19
Control Logic
Data Latches Right Channel
Serial Data From Latching Comparator
Switches Right
Switches Right
Switches Right
FIGURE PCM1750 Successive Approximation Logic Diagram.
PCM1750
Digital Output
bit-1. switches CDAC switches TDAC operate concurrently with each other, that when decision made keep reject bit-1, same decision made correction voltage bit-1. Even though ratio stability nichrome resistors used TDAC good poly capacitors, inconsequential because correction voltage each limited range adjustment. major carry code change from 111.111 000.000; binary two's complement coding) typically ±1/2 16-bit level, which sufficient provide 90dB -30dB level distortion (-60dB input). applications requiring less major carry, provided each channel make external adjustment.
1FFFFH 1FFFEH
Gain Change Rotates Transfer Function
00001H 00000H 3FFFFH
-2.75
-20.98µV
+2.749979
Offset Change Shifts Transfer Function
0.00V
20001H 20000H Gain drift (mostly reference drift) rotates transfer function around bipolar zero code (00000HEX NOTE: power supply voltages change (mostly supply), transfer function rotates around BPZ. power supply rejection specification spec table.
DISCUSSION SPECIFICATIONS
RESOLUTION DYNAMIC RANGE theoretical resolution PCM1750 18-bits. maximum possible number output codes counts 18bits 262,144 108dB (calculated raising 18th power). relative accuracy converter, however, more function it's absolute linearity signalto-noise ratio than many bits resolution has. These more pertinent specifications described later this section. Dynamic range, usually defined digital audio converters, measure THD+N effective input signal level -60dB referred 0dB. PCM1750 this value typically 90dB minimum 88dB (for audio bandwidth 20Hz 24kHz, THD+N -60db typ, -28dB max; 1kHz 192kHz). Resolution also commonly used theoretical measure dynamic range, does take into account effects distortion noise signal levels. ANALOG INPUT RANGE analog input range PCM1750 bipolar ±2.75V (nominal). Table gives precise input/output voltage/code relationships PCM1750. Figure shows these same relationships graphical format. should noted that computed voltage input levels represent center values (the midpoint between code transitions). Output coding binary two's complement.
DIGITAL OUTPUT 262144 LSBs 1FFFFHEX 00000HEX 3FFFFHEX 20000HEX ANALOG INPUT Full Scale Range Minimum Step Size +Full Scale Bipolar Zero Bipolar Zero -1LSB -Full Scale VOLTAGE INPUT 5.50000000V 20.98083496µV +2.74997902V 0.00000000V -0.00002098V -2.75000000V
FIGURE Analog Input Digital Output Diagram. From Figure effects offset gain errors visualized. These errors change value response changes temperature and/or supply voltage. addition, gain error full scale range, FSR) changes direct proportion VREFIN voltage value. SAMPLE HOLD PARAMETERS Aperture Delay Uncertainty Aperture delay time required switch from SAMPLE HOLD mode. This time typically 10ns PCM1750 constant. Aperture uncertainty (jitter) amount uncertainty associated with aperture delay. Aperture uncertainty affects overall accuracy converter greatest maximum input frequency converter. formula determining maximum input frequency (fMAX) given error contribution aperture uncertainty fMAX tjitter 2N)-1 where tjitter aperture uncertainty desired (signal-to-noise ratio) expressed total number quantization levels. 15-bit SNR, therefore, would expressed 32768. Using typical PCM1750 aperture jitter 50psrms 15-bit level, fMAX 50ps 32768)-1 97.1kHz. This matches very closely with rated dynamic accuracy PCM1750 where THD+N -88dB max. This means typical aperture jitter PCM1750 only becomes factor when input signals exceed 97kHz and/or greater than bits desired. Input Bandwidth full power bandwidth PCM1750 that input frequency above which significant distortion observed (THD+N 10-bits -60dB full scale input signal). data sheet, this number specified typically being 500kHz. wideband operation (when digital filter used) additional full power bandwidth PCM1750
TABLE Analog Input Digital Output Relationships.
PCM1750
used purposely alias band-limited signal down into baseband converter. This technique called undersampling used directly down-convert intermediate frequency riding much higher carrier frequency. DIGITAL TIMING Input/Output Logic Compatibility Digital logic PCM1750 CMOS compatible. Digital outputs PCM1750 capable driving minimum standard input loads. Digital output coding binary two's complement. Table gives precise input/output voltage/code relationships PCM1750. Figure shows these same relationships graphical format. Convert Command External Clock Input conversion initiated positive going edge convert command. Although convert command return time (prior 50ns before rising edge 19th clock), typical convert command pulse width 81ns called Figure specified 192kHz sample rate (fS). reason pulse width spec reduce problems associated with digital logic feedthrough noise. return convert command logic level specified time interferes least with successive approximation process. Also, should noted that putting fast logic edges (<5ns) convert command (P11) external clock input (P4) cause logic feedthrough analog stages converter will result added distortion during sampling conversion process. Using optional DF1750 digital filter provides adequately slow transitions maintain full specification performance. necessary, external convert command line used slow fast logic edges. with convert command, external clock input positive edge triggered duty-cycle dependent other than improve digital feedthrough noise immunity. duty cycle clock used instead desired. Refer Figure recommended timing relationships. Regardless what clock duty cycle used, operations relating valid data clocking should synchronized rising edge clock input. Although there maximum conversion time called specification table, PCM1750 have considerably longer conversion cycle. Droop internal capacitors will ultimately determine what true maximum conversion time min/typ/max times shown Figure based minimum sample rate 48kHz, typical 192kHz, maximum 222kHz. specifications tested 192kHz. minimum sample rate assumption based clock periods that increase time between convert commands increases. sample rate down near utilized observing maximum clock cycle requirements spacing convert commands achieve lower sample rates. This means that time interval shown Figure does have maximum value.
Clock Lockout number clocks given PCM1750 beyond required normal operation. continuous clock used, clocks beyond 19th gated PCM1750's internal logic until next positive going edge convert command. converter also goes into sample (track) mode starting positive edge 19th clock until next positive edge convert command, regardless many additional clocks offered. ideal operation converter stops clock input after 19th during this critical signal acquisition time. This timing shown Figure critical timing aspect that must observed clock input other than recommended used, that ample time following positive edge convert command proceed next rising clock edge. this time shortened, most important bit-1 (MSB) decision, which finalized first clock edge after convert command, will adversely affected. other words, clock input cannot have rising edge during time interval shown Figure SIGNAL-TO-NOISE RATIO Another specification converters signal-to-noise ratio (SNR). this measurement, full-scale 1kHz signal applied sampling rate PCM1750 192kHz. performed digital output noise power non-harmonic audio-bandwidth frequency bins (20Hz 24kHz) summed expressed relation full-scale input signal. advantage using PCM1750 this oversampled mode with optional DF1750 digital decimation filter that converter noise spread over full 96kHz passband then suppressed digital filter stopband attenuation (from 24kHz 96kHz). This effectively increases PCM1750 when used audio bandwidth converter. other advantage that need higher-order anti-aliasing input filtering greatly reduced. specification PCM1750 total harmonic distortion plus noise (THD+N). terms signal measurement, THD+N ratio DistortionRMS NoiseRMS SignalRMS expressed PCM1750, THD+N 100% tested three specified input levels using production test setup shown Figure this measurement, with test, full-scale 1kHz signal applied sampling rate PCM1750 192kHz (which standard digital audio sample rate 48kHz). performed digital output total power audio-bandwidth frequency bins (20Hz 24kHz) summed expressed relation fullscale input signal. audio band, THD+N PCM1750 essentially flat frequencies input signal levels. Typical Performance Curves THD+N versus Frequency
PCM1750
plots shown four different input signal levels (with without decimation filter): 0dB, -20dB, -40dB, 60dB. CHANNEL SEPARATION test channel separation 1kHz signal sampled 192kHz placed input PCM1750 while other input held performed idle (0V) channel result checked insure that 1kHz tone suppressed minimum 96dB. GAIN OFFSET ERRORS Initial gain bipolar offset errors laser trimmed wafer level 100% final tested insure compliance with electrical specifications. Bipolar offset errors further reduced zero using optional offset adjustment circuitry shown connection diagram (Figure Gain errors adjusted varying VREF either channel converter. This accomplished either using adjustable external reference placing buffer amplifiers with adjustable gain between VREFOUT VREFIN shown Figure INTEGRAL DIFFERENTIAL LINEARITY Linearity Testing absolute linearity PCM1750 order bits more seen from versus Frequency plots Typical Performance Curves. every code converter must 15-bit linear achieve specified THD+N performance, very high percentage will that linear. same observation also applies differential linearity errors PCM1750. Because PCM1750 100% tested linearity specifications, minimum maximum specifications given integral differential linearity errors.
Missing Codes Operation missing codes specification given PCM1750 same reasons given above. PCM1750, however, typically fewer than codes (less than 0.01%) missing 14-bit resolution level. 100% missing codes specification cannot maintained above 12-bit level, although this very little impact overall dynamic performance (THD+N). missing codes that occur higher resolution levels bit-2 lower major carry transitions converter. There typically missing codes bits) around critical bipolar zero operation zone (±1/8 full scale range around bipolar zero 0V). critical bipolar differential linearity error reduced from initial value zero using optional adjustment circuitry shown connection diagram (Figure REFERENCE gain drift PCM1750 primarily drift associated with reference. Better drift performance achieved using external reference like ones explained applications section (Figures 8c). Typical Performance Curves plot VREF Output versus Temperature shows full range operation including initial error typical gain drift. Pertinent performance data found electrical specification table. Reference Bypass Both (VREFIN) should bypassed with 10µF 47µF tantalum capacitor. there important system reasons using PCM1750 reference externally, outputs must appropriately buffered, bypassed (see Figure
192kHz High Accuracy Sine Wave Generator Timing Control PCM1750 Pass Filter 1kHz Serial Data Left
Serial Data Right
Analyzer
Parametric Tester
FIGURE PCM1750 Production Test Setup.
PCM1750
POWER SUPPLY REJECTION Because architecture PCM1750, power supply rejection varies with input signal size. spec table value expressed relative terms percent percent change supply voltage. versus Frequency plot Typical Performance Curves show expressed versus increase power supply ripple frequency. PERFORMANCE OVER TEMPERATURE Specification Temperatures critical specifications tested 25°C. drift specification temperature range from +70°C. PCM1750 will operate over wider temperature range -40°C +85°C. Gain Offset Drift Although PCM1750 primarily meant dynamic applications, specifications also given more traditional drift parameters such temperature gain offset drift. primary cause drift PCM1750 bandgap reference. Much lower gain drift realized necessary using circuit similar external reference circuits shown Figure Also, refer Typical Performance Curves VREF Output versus Temperature.
Dynamic Performance Dynamic performance predominated absolute linearity PCM1750. Because excellent ratio tracking versus temperature poly-poly capacitors, there virtually change dynamic performance converter over temperature (primarily THD+N). dynamic specifications over temperature cannot guaranteed, however, they 100% tested.
INSTALLATION
ANTI-ALIASING FILTER prevent unwanted input signals from being aliased into passband converter, necessary suppress band signals above sampling frequency using low-pass filter. requirement antialiasing filter, however, reduced using oversampling techniques. raising sample rate converter factor even roll anti-aliasing filter reduced. Figure order, linear-phase, antialiasing filter implemented using low-cost dual audio amps. This filter will suppress frequencies above 96kHz 80dB. many applications order anti-aliasing filter will adequate when using PCM1750 oversampling mode.
Optional External Adjust
10µF*
SOUT Left DCOM ACOM DCOM Convert SOUT Right Offset Left Left Left Left Left ACOM Bypass ACOM Right Right Right 0.01µF 220pF 220pF 0.01µF 0.01µF 0.1µF (low leakage, ceramic) 10µF* 47µF 0.01µF
150k
10µF*
10µF* 47µF
Optional External Adjust
150k
Right Offset Right
High quality tantalum.
Connect directly ground plane
FIGURE PCM1750 Connection Diagram.
PCM1750
INPUT SIGNAL CONDITIONING Input Circuit Note resistors 220pF capacitors each analog input shown connection diagram (Figure This input circuit configuration required achieve optimum performance PCM1750. Various other component values will yield satisfactory results, resistor should never exceed 200. Buffer Amplifier avoid introducing distortion, PCM1750 input must driven active impedance source amps such NE5532, Burr-Brown OPA2604, equivalent ideal). EXTERNAL ADJUSTMENTS simplified circuit diagram (see Figure shows complete channels PCM1750. input switched capacitors, trim comparator detailed. trim switches activated whenever corresponding chosen during successive approximation routine. first bits have corresponding trim circuits. R12a R12b resistors laser trimmed wafer level necessary correct nonlinearities. nominal voltage internally generated VREF 2.75V relatively impedance, buffered voltage output. should noted that just connecting optional adjustment circuits will affect DLEs bipolar offsets since unlikely that initial potentiometer settings (even centered) would match factory trimmed null potentials. connected, potentiometers must properly adjusted.
Adjust adjust connects center R1a/R1b resistive divider bit-1. After laser trimming this point nominally 100mV. offset adjust pins should connected ground using 0.01µF capacitor, especially traces potentiometers long. adjust pins used, they should still bypassed ground. Since there internal resistors clamp diodes both ground offset adjust pins, there obvious limits their range adjustment. With nominal internal voltage these points +100mV, there will greater limitation making negative adjustments than positive. negative voltage either adjustment pin, however, acceptable diode drop (-0.6V) below ground. preferred method adjustment input small level signal adjust minimum THD+N. Offset Adjust offset adjust switch (SOFF) position controlled whether sample hold mode. Switching from sample hold effectively allows charge offsets associated with sampling process eliminated. Grounding input converter ahead possible front anti-aliasing filter example) then adjusting bipolar zero error will remove offsets associated with entire sampling system. LAYOUT CONSIDERATIONS Power Requirements Noise power supply lines degrade converter performance, especially noise spikes from switching power supply. Appropriate supplies filters must used. Although PCM1750 positive supplies have separate digital analog +5V, most applications digital supply pins should connected analog supply. they aren't connected together, potential latchup condition occur when power supplies turned same time. supply powered other not, PCM1750 latch draw excessive current. normal operation, this problem because both should connected together. However, during evaluation, incoming inspection, repair, etc., where potential "hot" socket exists, care should taken power PCM1750 only after been socketed. supplies should bypassed shown Figure bypass capacitors should placed close their respective supply pins possible. Additional .01µF capacitors placed parallel with larger value capacitors increase high-frequency rejection, generally they required when high quality tantalums used. 0.1µF capacitor between should leakage type (such ceramic) must close these pins possible reduce noise pickup.
VREF
10µF
VREF OUTR 5532
VREF
10µF
VREF OUTL 5532
FIGURE Circuit External Gain Adjustment Using Internal Reference.
PCM1750
PCM1750 sensitive supply voltages outside absolute maximum ratings shown specification tables. exceed negative supplies time irreversible damage occur. Note resistors series with each supply line (shown Figure-7) help protect part from severe damage supplies overranged momentarily. Grounding Requirements Because high resolution linearity PCM1750, system design problems such ground path resistance contact resistance become very important. ACOM DCOM pins separated internally PCM1750. eliminate unwanted ground loops, commons (both analog digital) should connected same low-impedance ground plane. This should analog ground plane separate from other high-frequency digital ground planes same board. analog digital commons PCM1750 connected different ground planes, care should taken keep them within 0.6V each other insure proper operation converter. ground plane usually best solution preserving dynamic performance reducing noise coupling into sensitive converter circuits. Where compromises must made, common return analog input signals should referenced ACOM pins. This will prevent voltage drops power supply returns from appearing series with input signal.
Coupling between analog input digital lines should minimized careful layout. instance, lines must cross, they should right angles. Parallel analog digital lines should separated from each other pattern connected common. external offset adjust potentiometers used, potentiometers related resistors should located close PCM1750 possible. Minimizing "Glitches" Coupling external transients into analog-to-digital converter cause errors which difficult debug. Care should taken avoid glitches during critical times sampling conversion process. Since PCM1750 internal sample/hold function, signal that switches into HOLD state (CONVERT going HIGH) critical, would sample/hold amplifier. CONVERT rising edge should have minimal ringing, especially during 20ns after rises.
APPLICATIONS
USING DIGITAL FILTER decimation filter available PCM1750 called DF1750. available 28-pin 40-pin SOIC package. this filter greatly eases implementation PCM1750 audio band applications.
VREF OUTR 2.5V MC1403 5532 0.1µF VREF 2.75V 10µF 5532
VREF OUTR
VREF 2.75V 10µF
5532 26.36k VREF 2.75V 10µF
REF102
5532 VREF 2.75V 10µF
VREF OUTL
VREF OUTL
FIGURE External Reference Circuit Using Standard 2.5V Reference.
FIGURE Noise, Drift External Reference Circuit.
PCM1750
FIGURE Complete Sampling Circuit with Anti-aliasing Digital Filter, (44.1kHz output data rate).
150k PCM1750P VINR SOUTR VREF CONVERT 7.32k DCOM ACOM 1000pF VREF VINL IBCK SOUTL DINL VDD2 10µF 10µF FSEN OW20 LRCK LRPOL 1000pF 1000pF 7.32k 150k 1000pF 3.48k AGND DGND 7.32k 0.01µ 0.01µ 3.92k 1.33k 220pF VREF OBPOL WDCK DINR VSS1 VSS2 Interleaved Digital Output 1000pF 0.1µ 3.48k ACOM ACOM IMOD DOUT VREF DCOM MUTE TEST 10pF 10pF SCSL2 SCSL1 CKEN 16.9344 7.32k 1000pF 220pF 0.01µF 3.92k 1.33k 0.01µF VDD1 1.00M DF1750P (28-PIN PKG)
PCM1750
1000pF
Right Channel Analog Input
3.92k
1.33k
7.32k
1000pF
7.32k
1000pF
3.48k
1000pF
Left Channel Analog Input
3.92k
1.33k
7.32k
7.32k
1000pF
3.48k
1000pF
Burr-Brown OPA2604 with ±15V supplies NE5532 equivalent with supplies).
USING EXTERNAL REFERENCE Normally VREFOUT connected directly VREFIN. typical value VREF versus Temperature shown Typical Performance Curves. better drift power supply rejection performance desired, external reference circuits shown Figures used. Note that decoupling capacitors still connected VREFIN. External gain adjustment possible using variable output options available some precision voltage references varying gain external buffer amplifiers. range acceptable external references from +2.0V 2.0V, with 2.5V types being most commonly available. Full scale input voltage range will ±VREFIN +2.5V VREFIN results ±2.5V input range). external reference used, must bypassed with least capacitors. SAMPLING SYSTEM Figure partial schematic demonstration fixture PCM1750 (orderable model number DEM1133). shows implementation order, linear-phase, anti-aliasing filter (22kHz low-pass); PCM1750P converter; digital decimation filter called
DF1750P. shown this schematic, included demo fixture, latched parallel data outputs with strobe serial digital interface format (SPDIF) data transmitter. Also included DEM1133 user breadboard areas application specific circuit implementation. CONNECTION WITH DIGITAL FILTER PCM1750 DF1750 combination connected serial ports most popular processor (such those made AT&T, Motorola, adding small amount external glue logic. Figures show timing diagram schematic this interface. this interface, processor must configured 32-bit word inputs. glue logic generates flag bit, first 32-bit word, that signifies either left right channel data. flag will left channel data high right channel data. DF1750 configured either 20-bit data, although only 16-bit data shown Figure After data transferred into processor must shifted toward order compensate clock delay glue logic.
LRCK (LRPOL WDCK Frame
Flag Enable
Clock
Data
DATA
DATA
Channel Flag (Right Channel)
FIGURE PCM1750/DF1750 Timing Diagram.
PCM1750
LRCK 74HC74 74HC08 74HC32
FIGURE PCM1750/DF1750 Schematic.
DSP16/DSP32C Data
PCM1750
74HC74 74HC74 74HC74 74HC04 74HC08 LRCK 74HC74 74HC74 74HC74 74HC74 74HC08 Frame Sync 74HC32 74HC08 74HC04 Clock
DF1750
DOUT
OBPOL
WDCK
LRPOL
TMS32020/C20/C25 DSP56001 ADSP-2102/2105 Data
DF1750
DOUT
OBPOL
WDCK
LRPOL
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device PCM1750P PCM1750U PCM1750U/1K
Status OBSOLETE ACTIVE ACTIVE
Package Type SOIC SOIC SOIC
Package Drawing
Pins Package Plan 1000 None None None
Lead/Ball Finish Call SNPB SNPB
Peak Temp Call Level-3-260C-168 Level-3-260C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan currently available please check latest availability information additional product content details. None: available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean "Pb-Free" addition, uses package materials that contain halogens, including bromine (Br) antimony (Sb) above 0.1% total product weight.
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDECindustry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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