Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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MK2058-01
Communications Clock Jitter Attenuator
MK2058-01 VCXO (Voltage Controlled Crystal Oscillator) based clock jitter attenuator designed system clock distribution applications. This monolithic combined with external inexpensive quartz crystal, used replace more costly hybrid VCXO retiming module. device accepts outputs same clock frequency selectable ranges covering MHz. dual input also provided. controlling VCXO frequency within phase-locked loop (PLL), output clock phase frequency locked input clock. Through selection external loop filter components, loop bandwidth damping factor tailored meet system clock requirements. loop bandwidth down range possible.
Features
Excellent jitter attenuation telecom clocks Also serves general purpose clock jitter
attenuator distributed system clocks recovered data video clocks
Input input reference clocks switching glitches output VCXO-based clock generation offers very jitter
phase noise generation
Output clock phase frequency locked
selected input reference clock
Fixed input output phase relationship +115ppm minimum crystal frequency pullability
range, using recommended crystal
Industrial temperature range power CMOS technology 20-pin SOIC package Single power supply
Block Diagram
Pullable Crystal
ISET
Input Clock ICLK2 Input Clock ICLK1 ISEL
Phase Detector Charge Pump
VCXO
Selectable Divider
SEL2:0
CHGP
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Assignment
CHGP SEL0 SEL1 SEL2
Output Clock Selection Table
SEL2 SEL1 SEL0
Input Output Range 0.64 1.68 15.75 6.75 13.5
Crystal Frequency 3072 ICLK ICLK ICLK ICLK 2048 ICLK 1716 ICLK ICLK ICLK ICLK ICLK ICLK ICLK
20-pin SOIC
Note: input programming: GND, VDD, Floating
Descriptions
Number
Name
CHGP ISET SEL2 SEL1 SEL0 ICLK2 ICLK1 ISEL
Type
Power Power Power Input Power Power Power Output Input Input Input Output Input Input Input Input Power
Crystal Input. Connect this specified crystal. Power Supply. Connect +3.3 Power Supply. Connect +3.3 Power Supply. Connect +3.3 VCXO Control Voltage Input. Connect this CHGP external loop filter shown this data sheet. Connect ground. Connect ground. Connect ground. Charge Pump Output. Connect this external loop filter VIN. Charge pump current setting node, connection setting resistor. Output Frequency Selection Determines output frequency table above. Internally biased VDD/2. Output Frequency Selection Determines output frequency table above. Internal pull-up resistor. Internal Connection. Clock Output. Output Frequency Selection Determines output frequency table above. Internal pull-up resistor. Input Clock Connection Connect input reference clock this pin. unused, connect ground. Input Clock Connection Connect input reference clock this pin. unused, connect ground. Input Selection. Used select which reference input clock active. input level selects ICLK1, high input level selects ICLK2. Internal pull-up resistor. Connect ground. Crystal Output. Connect this specified crystal.
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Functional MK2058-01 clock generator that generates output clock directly from internal VCXO circuit which works conjunction with external quartz crystal. VCXO controlled internal (Phase-Locked Loop) circuit, enabling device perform clock regeneration from input reference clock. MK2058-01 configured provide output clock that same frequency input clock. There selectable input output frequency ranges, each which submultiple supported quartz crystal frequency range. Please refer Output Clock Selection Table Page Most typical clock devices internal (Voltage Controlled Oscillator) output clock generation. using VCXO with external crystal, MK2058-01 able generate jitter, phase-noise output clock within bandwidth PLL. This serves provide input clock jitter attenuation enables stable operation with low-frequency reference clock. VCXO circuit requires external pullable crystal operation. External loop filter components enable configuration with loop bandwidth.
output clock will change reflect phase newly selected input controlled phase slope (rate phase change) influenced loop characteristics.
Quartz Crystal
important that correct type quartz crystal used with MK2058-01. Failure result reduced frequency pullability range, inability loop lock, excessive output phase jitter. MK2058-01 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed Layout Recommendations section must followed. frequency oscillation quartz crystal determined external load capacitance. MK2058-01 incorporates variable load capacitors on-chip which "pull", change, frequency crystal. crystals specified with MK2058-01 designed have zero frequency error when total on-chip stray capacitance achieve this, layout should short traces between MK2058-01 crystal. complete description recommended crystal parameters application note MAN05. list approved crystals located ICST site (www.icst.com).
Application Information
Input Output Frequency Configuration
MK2058-01 configured generate output frequency that equal input reference frequency. Clock frequencies that supported those which fall into ranges listed Output Clock Selection Table Page Input bits SEL2:0 according this table, external crystal frequency. nominal (center) frequency external crystal will integer multiple input output clock specified. Please refer Quartz Crystal section this page regarding external crystal requirements.
Loop Filter Components
analog circuits loop filter establish operating stability. MK2058-01 uses external loop filter components following reasons: Larger loop filter capacitor values used, allowing lower loop bandwidth. This enables lower input clock reference frequencies also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking desired. loop filter values user selected optimize loop response characteristics given application.
Input
Input serves select between alternate input reference clocks. Upon reselection input clock, clock glitches output clock will generated "fly-wheel" effect VCXO (the quartz crystal high-Q tuned circuit). When input clocks phase aligned, phase
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Referencing External Component Schematic this page, external loop filter made components RSET establishes charge pump current therefore influences loop filter characteristics. Design tools configuring loop filter found www.icst.com, including on-line PC-based calculators.
External Component Schematic
(Refer Crystal Tuning section)
Crystal
ISEL ICLK1 ICLK2 SEL0 SEL1 SEL2
CHGP ISET
RSET
Recommended Loop Filter Values Output Frequency Range Selection
Crystal
SEL2 SEL1 SEL0 Multiplier
RSET
Loop Bandwidth
(-3dB point)
Damping Factor
3072 2048 1716
Note: input programming: GND, VDD, Floating
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
"normalized" loop bandwidth calculated follows: "normalized" bandwidth equation above does take into account effects damping factor second pole. However, does provide useful approximation filter performance. loop damping factor calculated follows: Damping Factor Where: Value resistor loop filter (Ohms) Charge pump current (amps) (refer Charge Pump Current Table, below) Crystal multiplier shown above table Value capacitor loop filter (Farads) general rule, following relationship should maintained between components loop filter:
Series Termination Resistor
Clock output traces over inch should series termination. series terminate trace commonly used trace impedance), place resistor series with clock line, close clock output possible. nominal impedance clock output (The optional series termination resistor shown External Component Schematic.)
Decoupling Capacitors
with high-performance mixed-signal MK2058-01 must isolated from system power supply noise perform optimally. Decoupling capacitors 0.01µF must connected between each ground plane. further guard against interfering system supply noise, MK2058-01 should common connection power plane shown diagram next page. ferrite bead bulk capacitor help reduce lower frequency noise supply that lead output clock phase modulation.
Recommended Power Supply Connection Optimal Device Performance
onnection 3.3V lane Ferrite Bead
ecoupling apacitor (such Tantalum
Charge Pump Current Table
0.01 ecoupling apacitors
RSET
Charge Pump Current (ICP)
Crystal Load Capacitors
device crystal connections should include pads small capacitors from ground from ground, shown External Component Schematic. These capacitors used adjust stray capacitance board match nominally required crystal load capacitance. Because load capacitance only increased this trimming process, important keep stray capacitance minimum using very short traces (and via's) been crystal device.
Special considerations must made choosing loop components These recommendations found design tools section www.icst.com.
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
most cases load capacitors will required. They should stuffed prototype evaluation board indiscriminate these trim capacitors will typically cause more crystal centering error than their absence. need load capacitors later determined, values will fall within range. need for, value these trim capacitors only determined prototype evaluation. Please refer MAN05 procedure determine component values.
Applications Note MAN05 also referenced additional suggestions layout crystal section.
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please also refer Recommended Layout drawing page Each 0.01µF decoupling capacitor should mounted component side board close possible. vias should used between decoupling capacitor pin. trace should kept short possible, should trace ground via. Distance ferrite bead bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted just next device with short traces. traces should routed next each other with minimum spaces, instead they should separated away from other traces. minimize EMI, series termination resistor needed) should placed close clock output. optimum layout with components same side board, minimizing vias through other signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK2058-01. This includes signal traces just underneath device, layers adjacent ground plane layer used device.
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Recommended Layout
inim output clock jitter, ground plane ithin this entire area. route other traces from this area.
inim output clock jitter, device connections should bulk decoupling device (see text).
Legend:
round onnection
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2058-01. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5 VDD+0.5 +85°C +150°C 125°C 260°C
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current Input High Voltage, SEL2 Input Voltage, SEL2 Input High Voltage, ISEL, SEL1:0 Input Voltage, ISEL, SEL1:0 Input High Voltage, ICLK1, Input Voltage, ICLK1, Input High Current Input Current Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage Short Circuit Current VIN, VCXO Control Voltage Nominal Output Impedance
Symbol
ZOUT
Conditions
Clock outputs unloaded,
Min.
3.15
Typ.
Max.
3.45
Units
VDD-0.5
VDD/2+1 VDD/2-1
VDD-0.4
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Pull Range VCXO Crystal Nominal Frequency Input Jitter Tolerance Input pulse width Output Frequency Error Output Duty Cycle high time) Output Rise Time Output Fall Time Skew, Input Output Clock Cycle Jitter (short term jitter) Timing Jitter, Filtered Hz-1.3 (OC-3) Timing Jitter, Filtered kHz-1.3 (OC-3)
Symbol
FOUT
Conditions
Using recommended crystal
Min.
-115
Typ. Max. Units
+115
ICLK error Measured VDD/2, CL=15 2.0V CL=15 CL=15 Rising edges, CL=15 Referenced Mitel/Zarlink MT9045, Note Referenced Mitel/Zarlink MT9045, Note
Note Minimum high time input clock. Note Input reference 19.44 output from Mitel/Zarlink MT9045 device freerun mode (SEL2:0 111, 19.44 external crystal).
Thermal Characteristics
Parameter
Thermal Resistance Junction Ambient
Symbol
Conditions
Still flow flow
Min.
Typ.
Max. Units
°C/W °C/W °C/W °C/W
Thermal Resistance Junction Case
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2058-01 Communications Clock Jitter Attenuator
Package Outline Package Dimensions (20-pin SOIC, Mil. Wide Body)
Package dimensions kept current with JEDEC Publication
Millimeters Symbol Inches
-2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27
-0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050
Ordering Information
Part Order Number
MK2058-01SI MK2058-01SITR
Marking
MK2058-01SI MK2058-01SI
Shipping packaging
Tubes Tape Reel
Package
20-pin SOIC 20-pin SOIC
Temperature
+85° +85°
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2058-01
Revision 040204
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com

Communications Clock Jitter Attenuator MK2058-01 VCXO (Voltage Co

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